A system supporting distributed synchronous computing

Abstract

The present invention discloses a system supporting distributed synchronous computing, including a motion control device group including a multi-core DSP processor, which is interconnected through an SRIO bus, a single-board computer, a switching card, a synchronous control module, a dynamic load balancing module, and a cross-core direct connection channel, with downlink directional distribution and error detection and correction functions. The synchronous control module has five synchronization signals, each with different functions and an internal priority judgment and queuing mechanism. The single-board computer has a predictive data pre-fetching mechanism and an encryption chip. The cross-core direct connection channel is established with a specific process. The machine learning algorithm of the dynamic load balancing module has an adaptive update mechanism. The local clock of the motion control device can be calibrated. The present invention has many advantages, such as improving operating efficiency, ensuring accurate and orderly data transmission, coordinating system synchronous operation, protecting data security, avoiding network congestion, and improving data transmission accuracy.

Description

Technical Field

[0001] The present invention relates to the field of computing system architecture applications, and in particular to a system supporting distributed synchronous computing. Background Art

[0002] With the rapid development of information technology, distributed computing has been widely used in many fields, such as big data processing, cloud computing, and artificial intelligence. However, existing distributed computing systems still have some shortcomings in terms of data synchronization, real-time performance, and resource efficiency. Traditional distributed systems often rely on centralized control, which limits their scalability and flexibility. In addition, data transmission may experience delays and packet loss, affecting overall computing performance.

[0003] In common distributed synchronous computing system architectures, the coordination of devices involved in motion axis-related computation and control tasks is poor, resulting in low overall system efficiency. Furthermore, data processing is plagued by long wait times, and data transmission between devices lacks effective rules, which can easily lead to confusion and errors, impacting the normal operation of the system. Furthermore, common system architectures lack effective control and management mechanisms for synchronization signals, making it impossible to rationally arrange the processing sequence of synchronization signals for different functions, thus affecting the coordinated and synchronous operation of various parts of the system. Furthermore, it is difficult to maintain clock consistency between devices, and clock discrepancies can easily lead to computational errors. The lack of an effective clock calibration mechanism makes it impossible to meet the operational requirements of computing system architecture applications. Therefore, a system supporting distributed synchronous computing is proposed. Summary of the Invention

[0004] The present invention provides the following technical solution: a system supporting distributed synchronous computing, comprising:

[0005] A motion control device group, a single-board computer, a switch card, a synchronization control module, a dynamic load balancing module, and a cross-core direct connection channel. The motion control devices in the motion control device group are all equipped with a multi-core DSP processor, the multi-core DSP processor is used for distributed motion axis control, and the motion control devices in the motion control device group are interconnected via an SRIO bus.

[0006] A single-board computer configures system timing and shared data rules through a PCIE interface. The switch card includes an uplink data interface, a downlink data interface, and a shared data interface. Five synchronization signals, including Sync1-Sync5, are provided inside the synchronization control module. A machine learning algorithm is provided inside the dynamic load balancing module. Sync1 in the synchronization control module is used to trigger a DSP interrupt of a motion control device to perform calculations and send data. Sync2 in the synchronization control module is used to control the uplink and downlink data distribution timing of the switch card. Sync3 in the synchronization control module is used to trigger downstream device synchronization through a doorbell. Sync4 in the synchronization control module is used to control shared data broadcasting. Sync5 in the synchronization control module is used to convert a PCIE interrupt packet to trigger task scheduling of the single-board computer.

[0007] The motion control devices in the motion control device group are all equipped with local clocks. The single-board computer is equipped with a predictive data prefetching mechanism. The establishment of the cross-core direct connection channel includes the source motion control device marking the SRIO-ID of the target motion control device in the data packet header, and then transferring the data after parsing the ID through the switching card. Finally, the channel is automatically released after the transmission is completed.

[0008] Preferably, the uplink data interface packages the downstream device data according to the "grid" rule and broadcasts it to all motion control devices through SRIO, and the downlink data interface distributes the motion control device data to the downstream device in a targeted manner according to the routing ID.

[0009] Preferably, an encryption chip is installed inside the single-board computer. When the single-board computer configures system timing and shared data rules through the PCIE interface, data encryption is performed through the encryption chip and the AES algorithm inside the encryption chip.

[0010] Preferably, the uplink data interface of the switching card is provided with a flow control function, and adopts a token bucket algorithm to distribute data traffic according to the receiving capability of the upper-layer device. The token bucket algorithm sets the rate of token generation and the capacity of the bucket. Only when there are enough tokens can data be transmitted upward through the uplink data interface.

[0011] Preferably, the downlink data interface of the switching card is internally provided with an error detection and correction function, which uses cyclic redundancy check and Hamming code technology to detect whether there are errors in the data at the data receiving end and correct the erroneous data.

[0012] Preferably, the local clock inside the motion control device has a clock calibration function, and the clock calibration function is used to calibrate using the network time protocol and the GPS clock signal so that each local clock is kept consistent.

[0013] Preferably, the machine learning algorithm inside the dynamic load balancing module is provided with an adaptive update mechanism. By collecting the system's load data, which includes the task execution time and resource utilization of each device, the machine learning algorithm can adjust its own parameters and model structure according to these load data.

[0014] Preferably, the synchronization control module needs to have a priority judgment and queuing mechanism inside. The synchronization control module sets priorities for the 5 synchronization signals through its internal priority judgment and queuing mechanism, and can sort and process different synchronization signals according to preset priority rules.

[0015] In summary, compared with the prior art, the present invention provides a system supporting distributed synchronous computing, which has the following beneficial effects:

[0016] 1. The present invention uses a multi-core DSP processor in a motion control device group for distributed motion axis control. The devices are interconnected via an SRIO bus, which helps to efficiently perform motion axis-related calculations and control tasks, achieve collaborative work between devices, and improve the overall operating efficiency of the system. In addition, through the predictive data prefetching mechanism of the single-board computer, it is possible to obtain potentially useful data in advance, reduce data waiting time, and increase the speed of data processing, thereby accelerating the operating rhythm of the entire system. At the same time, the uplink data interface of the switching card packages and broadcasts data according to the grid rule, and the downlink data interface distributes data in a targeted manner according to the routing ID. This regularized data processing method ensures that data is transmitted accurately and orderly between different devices, reducing confusion and errors in data transmission.

[0017] 2. The present invention uses five synchronization signals inside the synchronization control module to respectively undertake different functions such as triggering interrupts, controlling timing, triggering downstream device synchronization, controlling shared data broadcasting, and triggering single-board computer task scheduling. It also has an internal priority judgment and queuing mechanism, which can reasonably arrange the processing order of synchronization signals to ensure the coordinated and synchronous operation of various parts of the system. In addition, the local clock inside the motion control device has a calibration function, and combined with the network time protocol and GPS clock signal, each local clock is kept consistent, providing a unified time reference for the system's distributed synchronous calculation, ensuring the time synchronization of different devices, and avoiding calculation errors caused by clock differences. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the system architecture structure of the present invention.

[0019] Figure 2 It is a schematic diagram of the structure of the switching card of the present invention.

[0020] Figure 3It is a structural diagram of the synchronous control module of the present invention. DETAILED DESCRIPTION

[0021] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0022] The present invention provides a technical solution, a system supporting distributed synchronous computing, comprising:

[0023] Motion control device group, single-board computer, switch card, synchronization control module, dynamic load balancing module and cross-core direct connection channel. The motion control devices in the motion control device group are equipped with multi-core DSP processors. The multi-core DSP processors are used for distributed motion axis control. The motion control devices in the motion control device group are interconnected through the SRIO bus.

[0024] The single-board computer configures system timing and shared data rules through the PCIE interface. The switch card includes an uplink data interface, a downlink data interface, and a shared data interface. The uplink data interface packages data received from downstream devices according to the grid rule and broadcasts it to all motion control devices through SRIO. The specific process of the grid rule packaging is as follows;

[0025] Data reception preparation: The uplink data interface of the switch card is in the state of waiting to receive data from the downstream device and is ready to be packaged according to the grid rule;

[0026] Data reception and grouping, the uplink data interface receives data units from the downstream device in sequence. These data units may be original data fragments sent in a certain order, and the received data are grouped according to the grid rule. Assume that the data is regarded as a continuous information stream, which is divided into four parts similar to the grid shape with a fixed number of bytes or data block size (this is just a conceptual division, and the actual division may be different according to the specific data structure and protocol). For example, every 4 consecutive data units are divided into a group, and the first and fourth data units are the upper left and lower right corners of the grid, and the second and third data units are the upper right and lower left corners of the grid;

[0027] Packing operation: Packing each data group divided according to the grid pattern. This may involve adding some identification information to identify the data grouping structure and order during the subsequent unpacking process. For example, a specific identifier is added to the beginning of each data group to indicate that it is a data group packed according to the grid pattern, and the order information of the data in the group is recorded. The packed data groups are combined to form a complete data packet, which can then be broadcast to all motion control devices via SRIO.

[0028] The downlink data interface distributes motion control device data to downstream devices in a targeted manner based on the routing ID. The downlink data interface of the switch card is internally equipped with an error detection and correction function. This function uses cyclic redundancy check and Hamming code technology to detect errors in the data at the receiving end and correct them.

[0029] The specific process of data error detection and correction is as follows:

[0030] Data reception preparation: The downlink data interface of the switch card distributes the motion control device data to the downstream device according to the routing ID. When the data reaches the data receiving end of the downlink data interface, the system prepares to start the error detection and correction function, which uses cyclic redundancy check and Hamming code technology;

[0031] Error detection steps: First, the cyclic redundancy check technology is used. The system calculates the received data according to the pre-set generator polynomial to obtain a CRC check code. The calculated CRC check code is then compared with the CRC check code attached to the received data. If the two check codes are the same, it is preliminarily determined that no error may have occurred during the data transmission process; if they are different, it indicates that there may be an error in the data. If the CRC detects that the data may have an error, the Hamming code technology is then activated for further detection. According to the encoding rules of the Hamming code, the data is analyzed to determine the location of the error (if an error exists);

[0032] Error correction steps: If the Hamming code detects an error and can determine the error location, the erroneous data bits are corrected according to the Hamming code's error correction rules. The corrected data will be considered correct data and continue to be transmitted or processed in the system. If the CRC test indicates that the data is probably correct or no error is found after the Hamming code test, the data will continue to be transmitted and processed in the system according to the normal process.

[0033] The synchronization control module is internally provided with five synchronization signals, including Sync1-Sync5. Sync1 in the synchronization control module is used to trigger the DSP interrupt of the motion control device to perform calculations and data distribution. Sync2 in the synchronization control module is used to control the uplink and downlink data distribution timing of the switch card. Sync3 in the synchronization control module is used to trigger the synchronization of downstream devices through the doorbell. Sync4 in the synchronization control module is used to control shared data broadcast. Sync5 in the synchronization control module is used to convert the PCIE interrupt packet to trigger the task scheduling of the single-board computer.

[0034] The dynamic load balancing module is internally equipped with a machine learning algorithm, which has an adaptive update mechanism. By collecting system load data, including the task execution time and resource utilization of each device, the machine learning algorithm can adjust its own parameters and model structure based on this load data. The specific process of the above steps is as follows;

[0035] Load data collection: The system determines the range of devices for which load data needs to be monitored, covering various devices in the distributed synchronous computing system architecture, such as motion control equipment groups, single-board computers, and switch cards. Load data is then collected for each device. Task execution time is obtained by recording the time it takes for the device to start executing a task and complete it. In terms of resource utilization, for example, for multi-core DSP processors, the CPU usage rate, memory usage rate, and other resource usage ratios are monitored. These task execution time and resource utilization data are collected and summarized as load data.

[0036] Data processing and analysis: Preprocess the collected load data, such as removing outliers (such as unreasonable data caused by temporary equipment failures or sudden interference) and formatting the data to meet the input requirements of the machine learning algorithm. Depending on the characteristics of the machine learning algorithm, specific features may be extracted from the load data. For example, features related to the task type can be extracted from the task execution time data to better analyze the impact of different types of tasks on the system load. The processed load data is input into the machine learning algorithm, which evaluates the current load status of the system based on the existing model structure and parameters to determine whether the system load is balanced and which devices are overloaded or underloaded.

[0037] Parameter and model structure adjustment: If the evaluation results show that the system load is unbalanced, the machine learning algorithm decides how to adjust its own parameters based on predefined strategies. For example, if the task execution time of a device is too long and the resource utilization rate is too high, the algorithm may decide to adjust the weight parameters assigned to the device task. In some cases, if the current model structure cannot adapt well to the load changes, the algorithm will optimize the model structure. For example, adding or reducing hidden layers, adjusting the way neurons are connected, etc. According to the new parameters and model structure, tasks are reallocated or resource allocation strategies are adjusted to achieve system load balancing and improve the overall system performance. As the system runs, the above-mentioned process of load data collection, analysis and adjustment is repeated continuously, so that the machine learning algorithm can continuously adapt to the dynamic changes in the system load and continuously optimize the system's load balancing effect;

[0038] The motion control devices in the motion control device group are all equipped with local clocks. The single board computer is equipped with a predictive data prefetching mechanism. The specific process of the predictive data prefetching mechanism is as follows:

[0039] Data demand analysis: The single-board computer monitors the tasks it is currently executing and about to execute. This includes obtaining task-related information, such as task type and task priority, through interaction with other components (such as the synchronization control module and the dynamic load balancing module). Based on the task information, the data requirements associated with these tasks are analyzed. For example, if the task involves operating a device in the motion control device group, the computer determines the data that may need to be obtained from the device or other related devices, such as device status data, historical operation record data, etc.

[0040] Prefetch trigger judgment: Evaluate the current resource status of the single-board computer, including memory capacity, processing power, etc. Ensure that there are sufficient resources to perform the prefetch operation without affecting the currently ongoing task. Based on the data demand analysis results and resource evaluation, determine whether the prefetch conditions are met. Prefetch conditions may include the importance of the data (such as data that is critical to the high-priority task to be executed), the cost of obtaining the data (such as low cost from the local cache and high cost from the remote device), etc. If the prefetch conditions are met, such as there is sufficient memory space and the data is very important to the task to be executed, the prefetch operation is triggered;

[0041] Data prefetch execution: Determine the data source that needs to prefetch data. This may be data in other motion control devices, switch cards, or local storage, and send a prefetch request to the data source. If the data source is another device, send a request through the corresponding interface (such as PCIE interface or SRIO bus). The request contains the data identification information that needs to be prefetched, such as the address and type of the data. Receive the data returned from the data source and cache it in the local cache of the single-board computer. During the caching process, some preprocessing may be performed on the data, such as data format conversion, so that subsequent tasks can use it quickly;

[0042] Prefetch data update and management: Regularly check the validity of prefetched data. Since the system status may change, the prefetched data may become outdated. For example, if the status of a device changes, the previously prefetched status data of the device may no longer be accurate. If the prefetched data is invalid, re-trigger the prefetch operation based on the new demand and update the data in the local cache. Alternatively, if there is new data demand and the local cache has sufficient space, the new data can be directly prefetched and some of the old data can be replaced.

[0043] The local clocks inside the motion control devices have a clock calibration function. Through the clock calibration function, the network time protocol and GPS clock signals are used for calibration to keep the local clocks consistent. The specific steps of the above process are as follows:

[0044] Clock calibration preparation: The local clock inside each motion control device in the motion control device group is initialized and starts timing when the device is started. The predictive data prefetching mechanism of the single-board computer operates normally, which is independent of but simultaneous with the local clock calibration process.

[0045] Clock calibration signal acquisition: The motion control device sends a request to the Network Time Protocol server through the network connection to obtain the NTP signal. This NTP signal contains precise time information and serves as a reference for calibrating the local clock. For motion control devices with GPS reception function, the GPS receiver receives the GPS clock signal, which also carries high-precision time data and can be used to calibrate the local clock.

[0046] Clock calibration operation: The motion control device compares the current time of the local clock with the time in the received NTP signal and GPS clock signal (if any), calculates the time deviation between the local clock and the standard time (NTP or GPS time), and based on the calculated time deviation, the clock calibration function inside the motion control device begins to adjust the local clock. If the local clock is faster than the standard time, the clock frequency is reduced or other appropriate methods are used to slow down the local clock time to be consistent with the standard time. If the local clock is slower than the standard time, the clock frequency is increased or similar adjustment methods are used to make the local clock time catch up with the standard time. The above comparison and adjustment steps are repeated continuously to ensure that the local clocks inside each motion control device in the entire motion control device group remain consistent. In this way, in the distributed synchronous computing system architecture, each motion control device can operate based on a consistent local clock, avoiding calculation and control errors caused by clock differences;

[0047] The SBC has an internal encryption chip. When the SBC configures the system timing and shared data rules through the PCIE interface, the encryption chip and its internal AES algorithm are used to encrypt data. The specific process of the above steps is as follows:

[0048] Data preparation: The single-board computer obtains data related to configuring system timing and shared data rules through the PCIE interface. This data may include various system parameters, device identification, and other information;

[0049] Encryption preparation: The encryption chip inside the single-board computer is initialized before data encryption. The necessary configuration information, such as key length and encryption mode, is loaded. The AES algorithm inside the encryption chip is initialized and the specific encryption operation mode, such as Electronic Codebook (ECB) mode or Cipher Block Chaining (CBC) mode, is determined based on the preset standard (such as AES-128, AES-192, or AES-256).

[0050] Encryption operation: According to the requirements of the AES algorithm, if the data length exceeds the block size specified by the algorithm (such as 128 bits), the data is divided into several fixed-size blocks. The encryption chip encrypts each data block according to the AES algorithm. During the encryption process, the data block is encrypted using a pre-set key (this key is securely stored inside the encryption chip). For each data block, multiple rounds of encryption operations are performed (for example, AES-128 may require 10 rounds of encryption operations) to obtain the encrypted data block;

[0051] Encrypted data processing: The single-board computer uses encrypted data to configure system timing and shared data rules. When this encrypted data is transmitted and processed within the system, it can ensure data security and privacy, preventing data from being stolen or tampered with during the configuration process.

[0052] The establishment of a cross-core direct connection channel involves the source motion control device marking the SRIO-ID of the target motion control device in the data packet header, then parsing the ID through the switch card for data transfer, and finally automatically releasing the channel after the transmission is completed;

[0053] The uplink data interface of the switch card is equipped with a flow control function and adopts a token bucket algorithm to distribute data traffic according to the receiving capability of the upper-layer device. The token bucket algorithm sets the token generation rate and the bucket capacity. Only when there are enough tokens can data be transmitted upward through the uplink data interface. The specific process of the above steps is as follows;

[0054] Token bucket initialization: Two key parameters of the token bucket are determined based on the receiving capabilities of the upper-layer device: the token generation rate (r) and the bucket capacity (C). For example, if the upper-layer device can receive 100 data units per second, the token generation rate r can be set to 100 tokens per second, and the bucket capacity C can be set to 200 tokens (assuming a value) based on factors such as the system cache capacity.

[0055] Token generation and accumulation: The token bucket continuously generates tokens at the set token generation rate r. For example, tokens are added to the bucket at a rate of r per second. The generated tokens accumulate in the bucket but will not exceed the bucket capacity C. If the bucket is full, the newly generated tokens will be discarded.

[0056] Data transmission determination: When data arrives at the uplink data interface of the switch card and is ready to be transmitted to the upper-layer device, flow control determination is required to check whether there are enough tokens in the token bucket to allow data transmission. If the data size is n data units, it is necessary to check whether there are at least n tokens in the bucket. For example, if a data packet requires 5 tokens, but there are only 3 tokens in the bucket, the data packet cannot be transmitted temporarily.

[0057] Data transmission and token consumption: If there are enough tokens in the bucket (the number of tokens is greater than or equal to the number of tokens required for the data), the data is allowed to be transmitted to the upper layer device through the uplink data interface. When transmitting data, the number of tokens corresponding to the data size is consumed. For example, after transmitting a data packet that requires 5 tokens, the number of tokens in the bucket is reduced by 5;

[0058] Continuous monitoring and adjustment: Continuously monitor the data traffic through the uplink data interface, including data arrival rate and transmission volume. Based on system operation and changes in the receiving capabilities of upper-layer devices, the token generation rate r and bucket capacity C may need to be adjusted. For example, if the receiving capabilities of upper-layer devices increase, the value of r can be appropriately increased to allow for more data transmission.

[0059] The synchronization control module needs to have a priority judgment and queuing mechanism. The synchronization control module uses its internal priority judgment and queuing mechanism to set the priority of the five synchronization signals and can sort and process different synchronization signals according to the preset priority rules. The specific process of the above steps is as follows;

[0060] Priority rules: Based on the system architecture and the functions of each synchronization signal, determine the importance of each synchronization signal in system operation. For example, Sync1 is used to trigger the DSP interrupt of the motion control device, perform calculations and send data, which is critical to the normal operation of the motion control device; Sync2 controls the uplink and downlink data distribution timing of the switching card, affecting the order of data transmission, etc. Based on the importance of the function, preset priority rules are established. Assuming that the priority order is based on the degree of impact on the key functions of the system, the established priority order is: Sync1>Sync2>Sync3>Sync4>Sync5;

[0061] Priority setting: The synchronization control module identifies 5 synchronization signals: Sync1-Sync5, and marks the corresponding priority for each synchronization signal according to the preset priority rules. For example, Sync1 is marked with the highest priority and Sync5 is marked with the lowest priority;

[0062] Queuing mechanism: When synchronization signals arrive at the synchronization control module, they enter the corresponding queue according to their priority tags. High-priority signals enter the head of the queue, and low-priority signals enter the tail of the queue. For example, Sync1 will be placed at the head of the queue, while Sync5 will be placed at the tail of the queue.

[0063] Sorting and processing: The synchronization control module processes synchronization signals in the order of the queue, starting from the head, with high-priority synchronization signals processed first. For example, Sync1 is processed first, executing its functions of triggering the DSP interrupt of the motion control device, performing calculations, and sending data. During the processing of high-priority signals, if a low-priority signal arrives, the low-priority signal must wait until the high-priority signal is processed before being processed in order. For example, while processing Sync1, Sync5 arrives. Sync5 must wait until Sync1 is processed before processing Sync5 according to the queue order (converting Sync5 into a PCIE interrupt packet to trigger the task scheduling of the single-board computer). During system operation, if the system status changes, such as changes in the task requirements of certain devices or failures, it may be necessary to dynamically adjust the priority rules, re-evaluate the importance of each synchronization signal based on the new system status, adjust the priority order, and re-mark the priority and re-queue accordingly, and then continue to process the synchronization signals in the new order.

[0064] This solution uses the multi-core DSP processor in the motion control device group for distributed motion axis control. The devices are interconnected through the SRIO bus, which helps to efficiently perform motion axis-related calculations and control tasks, realize collaborative work between devices, and improve the overall operating efficiency of the system. In addition, through the predictive data prefetching mechanism of the single-board computer, it can obtain data that may be used in advance, reduce data waiting time, and increase the speed of data processing, thereby speeding up the operation rhythm of the entire system. At the same time, the uplink data interface of the switching card packages and broadcasts data according to the grid rule, and the downlink data interface distributes data in a targeted manner according to the routing ID. This regularized data processing method ensures that data is transmitted accurately and orderly between different devices, reducing confusion and errors in data transmission.

[0065] This solution uses five synchronization signals inside the synchronization control module to respectively undertake different functions such as triggering interrupts, controlling timing, triggering downstream device synchronization, controlling shared data broadcasting, and triggering single-board computer task scheduling. It also has an internal priority judgment and queuing mechanism, which can reasonably arrange the processing order of synchronization signals to ensure the coordinated and synchronous operation of various parts of the system. In addition, the local clock inside the motion control device has a calibration function. Combined with the network time protocol and GPS clock signal, the local clocks are kept consistent, providing a unified time base for the system's distributed synchronous calculations, ensuring the time synchronization of different devices, and avoiding calculation errors caused by clock differences.

[0066] This solution uses an internal encryption chip and AES algorithm to encrypt data when configuring system timing and shared data rules for the single-board computer, effectively protecting data security and privacy and preventing data from being stolen or tampered with during the configuration process. The uplink data interface of the switching card has a flow control function, and a token bucket algorithm is used to distribute traffic according to the receiving capacity of the upper-layer device to avoid network congestion caused by excessive data traffic and ensure the stability of data transmission. The error detection and correction function of the downlink data interface uses cyclic redundancy check and Hamming code technology to promptly detect and correct data errors and improve the accuracy of data transmission.

[0067] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0068] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A system supporting distributed synchronous computing, characterized in that: include: A motion control device group, a single-board computer, a switch card, a synchronization control module, a dynamic load balancing module, and a cross-core direct connection channel. The motion control devices in the motion control device group are all equipped with a multi-core DSP processor, the multi-core DSP processor is used for distributed motion axis control, and the motion control devices in the motion control device group are interconnected via an SRIO bus. A single-board computer (SBC) configured with system timing and shared data rules via a PCIE interface; a switch card including an uplink data interface, a downlink data interface, and a shared data interface; a synchronization control module internally configured with five synchronization signals, including Sync1-Sync5; and a dynamic load balancing module internally configured with a machine learning algorithm. Sync1 in the synchronization control module is used to trigger the DSP interrupt of the motion control device to perform calculations and data distribution. Sync2 in the synchronization control module is used to control the uplink and downlink data distribution timing of the switch card. Sync3 in the synchronization control module is used to trigger downstream device synchronization through the doorbell. Sync4 in the synchronization control module is used to control shared data broadcast. Sync5 in the synchronization control module is used to convert the PCIE interrupt packet to trigger the task scheduling of the single-board computer. The motion control devices in the motion control device group are all equipped with local clocks. The single-board computer is equipped with a predictive data prefetching mechanism. The establishment of the cross-core direct connection channel includes the source motion control device marking the SRIO-ID of the target motion control device in the data packet header, and then transferring the data after parsing the ID through the switching card. Finally, the channel is automatically released after the transmission is completed.

2. A system supporting distributed synchronous computing according to claim 1, characterized in that: The uplink data interface packages the downstream device data according to the grid rule when receiving the data, and broadcasts it to all motion control devices through SRIO. The downlink data interface distributes the motion control device data to the downstream device in a targeted manner according to the routing ID.

3. The system supporting distributed synchronous computing according to claim 1, characterized in that: An encryption chip is installed inside the single-board computer. When the single-board computer configures system timing and shared data rules through the PCIE interface, data encryption is performed through the encryption chip and the AES algorithm inside the encryption chip.

4. The system supporting distributed synchronous computing according to claim 1, wherein: The uplink data interface of the switching card is provided with a flow control function and adopts a token bucket algorithm to distribute data traffic according to the receiving capability of the upper-layer device. The token bucket algorithm sets the rate of token generation and the capacity of the bucket. Only when there are enough tokens can data be transmitted upward through the uplink data interface.

5. The system supporting distributed synchronous computing according to claim 1, characterized in that: The downlink data interface of the switching card is internally provided with an error detection and correction function, which uses cyclic redundancy check and Hamming code technology to detect whether there is an error in the data at the data receiving end and correct the erroneous data.

6. The system supporting distributed synchronous computing according to claim 1, characterized in that: The local clock inside the motion control device has a clock calibration function. Through the clock calibration function, the network time protocol and the GPS clock signal are used for calibration, so that each local clock is kept consistent.

7. The system supporting distributed synchronous computing according to claim 1, characterized in that: The machine learning algorithm within the dynamic load balancing module is provided with an adaptive update mechanism. By collecting the system's load data, which includes the task execution time and resource utilization of each device, the machine learning algorithm can adjust its own parameters and model structure according to the load data.

8. The system supporting distributed synchronous computing according to claim 1, characterized in that: The synchronization control module needs to have a priority judgment and queuing mechanism inside. The synchronization control module sets the priority of the 5 synchronization signals through its internal priority judgment and queuing mechanism, and can sort and process different synchronization signals according to preset priority rules.

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