Integrated circuit optimization method and device, electronic equipment, storage medium and product

Abstract

The invention relates to an optimization method and device of an integrated circuit, electronic equipment, a computer readable storage medium and a computer program product, and belongs to the field of computers. The optimization method of the integrated circuit comprises the following steps: acquiring an antenna effect check report of the integrated circuit; determining whether the integrated circuit has antenna effect violation according to the antenna effect check report; under the condition that the integrated circuit has the antenna effect violation, determining diode information required for repairing the antenna effect violation based on the antenna effect check report and a preset diode standard unit; wherein the diode information is used for optimizing and repairing the antenna effect violation of the integrated circuit. According to the method and the device, the diode information required for repairing the violation of the antenna effect can be quickly and accurately determined, the reduction of design iteration is facilitated, and repeated tests are avoided, so that the design period of chip design can be shortened.

Description

Technical Field

[0001] This application belongs to the field of computers, and particularly relates to an optimization method, device, electronic device, computer-readable storage medium, and computer program product for integrated circuits. Background Art

[0002] During the manufacturing process of chips, such as plasma etching, charges will be generated. In the plasma chamber, charges can flow from the wafer surface to the bulk silicon and then back to the plasma. At this time, conductive layers such as metal wires or polysilicon act like an antenna and will collect charges. The larger the antenna area, the more charges will be collected. When the accumulated charges reach a certain threshold, it may damage the transistor gate oxide, causing irreversible damage. This phenomenon is called the "antenna effect". With the continuous development of integrated circuit technology, metal interconnects are becoming more and more complex, the number of metal layers is increasing, and the thickness of the gate oxide layer is getting thinner, so the antenna effect is becoming more and more serious. Therefore, it is essential to repair the violations of the antenna effect in chip physical design. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide an optimization method, device, electronic device, computer-readable storage medium, and computer program product for integrated circuits, so as to quickly and accurately determine the diode information required to repair the antenna effect violation, which helps to reduce design iterations and avoid repeated experiments, thereby shortening the design cycle of chip design.

[0004] The embodiments of this application are implemented as follows:

[0005] In a first aspect, an embodiment of this application provides an optimization method for an integrated circuit, including: obtaining an antenna effect inspection report of the integrated circuit; determining whether there is an antenna effect violation in the integrated circuit according to the antenna effect inspection report; in the case where there is an antenna effect violation in the integrated circuit, determining the diode information required to repair the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell; wherein the diode information is used to optimize and repair the antenna effect violation of the integrated circuit.

[0006] In the above embodiments, it is possible to quickly determine whether there is an antenna effect violation in an integrated circuit according to the antenna effect inspection report. Since the antenna effect inspection report records the antenna effect violation information of the gate nodes of the transistors with antenna effect violations, therefore, in the case where there is an antenna effect violation in the integrated circuit, it is possible to directly determine the diode information required to repair the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell, without the need to use a loop to add one virtual diode each time to test whether the antenna effect violation in the integrated circuit still exists. If it does not exist, the process ends. If it still exists, another one is added and so on until there is no antenna effect violation. When a large number of diodes need to be added to repair the antenna effect violation, the number of loops will be very large, which will significantly increase the iteration time in large-scale chip projects. Therefore, the present application can quickly and accurately determine the diode information required to repair the antenna effect violation, which helps to reduce design iterations and avoid repeated experiments, thereby shortening the design cycle of chip design.

[0007] Combined with a possible implementation manner of the first aspect embodiment, the antenna effect inspection report includes: antenna effect violation information of the gate nodes of the transistors in the integrated circuit; determining the diode information required to repair the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell includes: obtaining the gate node names with antenna effect violations in the antenna effect inspection report; for each gate node name with an antenna effect violation, determining the diode information required to repair the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cell.

[0008] In the above embodiments, when determining the diode information required to repair the antenna effect violation, the gate node names with antenna effect violations in the antenna effect inspection report can be obtained first, and then, for each gate node name with an antenna effect violation, the diode information required to repair the antenna effect violation of the gate node name is determined based on the antenna effect violation information of the gate node name and the preset diode standard cell. In this way, the diode information required to repair the antenna effect violations of all gate node names can be output at one time, which is beneficial to improving the efficiency.

[0009] In a possible implementation manner combining with the embodiments of the first aspect, if the antenna effect violation includes an accumulative antenna violation, the antenna effect inspection report includes: antenna effect violation information of the gate node of the transistor in the integrated circuit; based on the antenna effect inspection report and a preset diode standard cell, determining the diode information required to repair the antenna effect violation, including: obtaining the gate node name with antenna effect violation in the antenna effect inspection report; performing redundancy removal processing on multiple antenna effect violation information with the same gate node name, and retaining the antenna effect violation information with the largest antenna violation ratio; for each gate node name with antenna effect violation after redundancy removal processing, based on the antenna effect violation information of the gate node name and the preset diode standard cell, determining the diode information required to repair the antenna effect violation of the gate node name.

[0010] In the above embodiment, when determining the diode information required to repair the antenna effect violation, the gate node name with antenna effect violation in the antenna effect inspection report can be obtained first, and then, redundancy removal processing is performed on multiple antenna effect violation information with the same gate node name. Finally, for each gate node name with antenna effect violation, based on the antenna effect violation information of the gate node name and the preset diode standard cell, the diode information required to repair the antenna effect violation of the gate node name is determined. In this way, the diode information required to repair the antenna effect violation of all gate node names can be output at one time, which is beneficial to improving efficiency. At the same time, due to the redundancy removal processing, the data processor can be reduced, which can further improve efficiency and reduce the interference of the diode information obtained from redundant data.

[0011] In a possible implementation manner combining with the embodiments of the first aspect, the diode information includes the number of diode standard cells; based on the antenna effect violation information of the gate node name and the preset diode standard cell, determining the diode information required to repair the antenna effect violation of the gate node name includes: obtaining the equivalent gate area of the preset diode standard cell; determining the target gate area required to repair the antenna effect violation based on the antenna effect violation information of the gate node name; according to the target gate area and the equivalent gate area of the preset diode standard cell, determining the number of diode standard cells required to repair the antenna effect violation of the gate node name.

[0012] In the above embodiments, when repairing the diode information required for the antenna effect violation of the gate node name, since the antenna effect violation information records the key information that can determine the number of required diode standard cells, the target gate area required for repairing the antenna effect violation can be determined based on the antenna effect violation information of the gate node name; according to the target gate area and the equivalent gate area of the preset diode standard cell, the number of required diode standard cells can be quickly determined. For example, if Ag’ represents the target gate area and Agj’ represents the equivalent gate area of the diode standard cell, the number of required diode standard cells can be determined by the quotient of Ag’ / Agj’.

[0013] Combined with a possible implementation manner of the first aspect embodiment, the antenna effect violation information includes: the gate node name, the area of the effective conductor connected to the gate node, the gate area of the transistor, and the antenna effect violation threshold, where the effective conductor refers to the conductor that is connected to the gate node and actually participates in collecting charges and can be transmitted to the gate node; determining the target gate area required for repairing the antenna effect violation based on the antenna effect violation information of the gate node name includes: determining the target gate area required for repairing the antenna effect violation according to the area of the effective conductor, the gate area, and the antenna effect violation threshold.

[0014] In the above embodiments, when the antenna effect violation information includes: the gate node name, the area of the effective conductor connected to the gate node, the gate area of the transistor, and the antenna effect violation threshold, the target gate area can be quickly determined. For example, if Ax represents the area of the effective conductor, Ag represents the gate area, f represents the antenna effect violation threshold, and Ag’ represents the target gate area, then Ag’ > Ax / f – Ag.

[0015] In a possible implementation manner combining with the embodiments of the first aspect, the preset diode standard cell includes a plurality of diode standard cells with different widths; determining the number of diode standard cells required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell includes: determining the number of first diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, where the first diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the target gate area among the plurality of diode standard cells; if the first remainder is not zero, determining the number of second diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the first remainder by the equivalent gate area of the second diode standard cell, where the first remainder is the remainder obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, and the second diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the first remainder among the plurality of diode standard cells.

[0016] In the above embodiment, two diode standard cells with different widths can be used to repair the antenna effect violation of the gate node name. For example, the above first diode standard cell and second diode standard cell can be used to repair the antenna effect violation of the gate node name. Since both the first diode standard cell and the second diode standard cell are diode standard cells that meet the requirements and have the largest equivalent gate area, this can minimize the number of added diodes while repairing the antenna effect violation of the gate node name, and can also reduce the gate area of the gate node after repair, that is, the above solution can balance the gate area of the gate node after repair and the number of diodes required for repair.

[0017] In a possible implementation manner combining with the embodiments of the first aspect, the method further includes: if the j-th remainder is not zero and the j-th diode standard cell is not the diode standard cell with the smallest equivalent gate area among the plurality of diode standard cells, determining the number of (j + 1)-th diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the j-th remainder by the equivalent gate area of the (j + 1)-th diode standard cell; where j is an integer greater than or equal to 2, the j-th remainder is the remainder obtained by dividing the (j - 1)-th remainder by the equivalent gate area of the j-th diode standard cell; the (j + 1)-th diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the j-th remainder among the plurality of diode standard cells; and ending until the (j + 1)-th remainder is zero, or the (j + 1)-th diode standard cell is the diode standard cell with the smallest equivalent gate area among the plurality of diode standard cells.

[0018] In the above embodiments, more diode standard cells with different widths can be used to repair the antenna effect violation of the repaired gate node name. By adopting the above implementation manner, while repairing the antenna effect violation of the repaired gate node name, the number of added diodes can be reduced as much as possible, and the gate area of the gate node after repair can be reduced as much as possible.

[0019] Combined with a possible implementation manner of the first aspect embodiment, the preset diode standard cell includes a plurality of diode standard cells with different widths; determining the number of diode standard cells required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell includes: determining the number of target diode standard cells required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the target diode standard cell, where the target diode standard cell is the diode standard cell with the smallest equivalent gate area among the plurality of diode standard cells.

[0020] In the above embodiments, by using the diode standard cell with the smallest equivalent gate area, the gate area of the gate node can be reduced as much as possible while repairing the antenna effect violation of the gate node name.

[0021] In a second aspect, an embodiment of the present application further provides an optimization device for an integrated circuit, including: an acquisition module, a detection module, and a determination module; the acquisition module is configured to acquire an antenna effect inspection report of the integrated circuit; the detection module is configured to determine whether the integrated circuit has an antenna effect violation according to the antenna effect inspection report; the determination module is configured to, when the integrated circuit has an antenna effect violation, determine diode information required to repair the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell; where the diode information is used to optimize and repair the antenna effect violation of the integrated circuit.

[0022] In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory and a processor, the processor is connected to the memory; the memory is configured to store a program; the processor is configured to call the program stored in the memory to execute the method provided by any possible implementation manner of the first aspect embodiment as described above.

[0023] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, characterized in that a computer program is stored thereon, and when the computer program is run by a processor, it executes the method provided by any possible implementation manner of the first aspect embodiment as described above.

[0024] Fifth aspect, an embodiment of the present application further provides a computer program product, where the computer program product includes a computer program, and when the computer program is executed by a processor, it implements the method provided by any possible implementation manner of the first aspect embodiment described above.

[0025] Other features and advantages of the present application will be described in the subsequent specification. The objectives and other advantages of the present application can be achieved and obtained through the structures specifically pointed out in the written specification and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. As shown in the drawings, the above-mentioned and other objectives, features, and advantages of the present application will become clearer.

[0027] Figure 1 FIG. shows a schematic flowchart of an optimization method for an integrated circuit provided by an embodiment of the present application.

[0028] Figure 2 FIG. shows an optimization method for an integrated circuit provided by an embodiment of the present application. Figure 1 FIG. shows a schematic diagram of the principle of the specific implementation of S3 in.

[0029] Figure 3 FIG. shows a schematic diagram of the implementation principle of an optimization method for an integrated circuit provided by an embodiment of the present application.

[0030] Figure 4 FIG. shows a schematic module diagram of an optimization device for an integrated circuit provided by an embodiment of the present application.

[0031] Figure 5 FIG. shows a schematic structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The following will describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, but cannot be used to limit the protection scope of the present application. Those skilled in the art can understand that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device.

[0034] Furthermore, the term "and / or" in the present application is only a relational term describing the relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three cases: A exists alone, A and B exist simultaneously, and B exists alone.

[0035] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the technical term "connection" may be a direct connection or an indirect connection through an intermediate medium.

[0036] In order to optimize and repair the antenna effect violation of an integrated circuit, it is necessary to accurately determine the diode information required to repair the antenna effect violation. Based on this, the embodiments of the present application provide an optimization method for an integrated circuit, which can quickly and accurately determine the diode information required to repair the antenna effect violation, helps to reduce design iterations and avoid repeated experiments, thereby shortening the design cycle of chip design. The following is combined with Figure 1 to illustrate the optimization method of the integrated circuit provided by the embodiments of the present application.

[0037] S1: Obtain an antenna effect inspection report of the integrated circuit.

[0038] In some possible implementation manners, the antenna effect inspection report of the integrated circuit can be obtained from a database. In this implementation manner, it is necessary to store the antenna effect inspection report of the integrated circuit in the database in advance for subsequent use. In some possible implementation manners, the format of the antenna effect inspection report can be ASCII (American Standard Code for Information Interchange) format.

[0039] In some other possible implementation manners, the integrated circuit can be checked for antenna effect on the integrated circuit verification platform based on the antenna effect checking rules provided by the foundry, and an antenna effect checking report of the integrated circuit can be obtained. An inspection report will be generated after the inspection, and the inspection report will record the antenna effect violation information of the gate nodes of all transistors in the integrated circuit.

[0040] Among them, the antenna effect checking report includes: the antenna effect violation information of the gate nodes of the transistors in the integrated circuit. Since there are multiple transistors in the integrated circuit, the antenna effect checking report can include multiple antenna effect violation messages. For cumulative antenna violations, there can be multiple antenna effect violation messages for the same gate node name.

[0041] In some possible implementation manners, the antenna effect violation information can include: the gate node name (which can be represented by NET), the area of the effective conductor connected to the gate node (which can be represented by Ax), the gate area of the transistor (which can be represented by Ag), the antenna effect violation threshold (which can be represented by f), etc. In some implementation manners, the antenna effect violation information can also include the antenna violation ratio of the gate node name (which can be represented by Ax / Ag), where the antenna violation ratio is the ratio of the area of the effective conductor to the gate area of the transistor, that is, the antenna violation ratio = the area of the effective conductor / the gate area of the transistor.

[0042] In some possible implementation manners, the antenna effect violation information can include: the gate node name, the target gate area required to repair the antenna effect violation of the gate node name, the antenna violation ratio of the gate node name, and the antenna effect violation threshold. The target gate area can be determined according to the area of the effective conductor, the gate area, and the antenna effect violation threshold. For example, using Ax to represent the area of the effective conductor, Ag to represent the gate area, f to represent the antenna effect violation threshold, and Ag' to represent the target gate area, then Ag' > Ax / f - Ag.

[0043] Among them, the effective conductor connected to the gate node refers to the conductor that is connected to the gate node and actually participates in collecting charges and can transmit them to the gate node. The effective conductor includes multi-layer metal wires or metal vias connected to the gate node. When the effective conductor connected to the gate node is a multi-layer metal wire, the antenna effect violation triggered by this gate node may be a cumulative antenna violation. Correspondingly, there can be multiple antenna effect violation messages for the same gate node name. When the effective conductor connected to the gate node is a metal via, the antenna effect violation triggered by this gate node may be a non-cumulative antenna violation.

[0044] S2: Determine whether the integrated circuit has an antenna effect violation according to the antenna effect checking report.

[0045] After obtaining the antenna effect inspection report, it is possible to determine whether there is an antenna effect violation in the integrated circuit according to the antenna effect inspection report. For example, the antenna violation ratio can be determined based on the antenna effect violation information; whether there is an antenna effect violation in the integrated circuit can be determined based on the antenna violation ratio. Among them, if the antenna violation ratio is greater than or equal to the antenna effect violation threshold, there is an antenna effect violation in the integrated circuit.

[0046] Among them, an antenna effect violation means that the ratio of the area of the effective conductor connected to the gate node of the transistor to the area of the gate is greater than the specified threshold f. The value of the specified threshold f is provided by the wafer foundry. Assume that the gate node of a certain transistor is connected to a total of L layers of conductors, and the effective conductor areas of the 1st to Lth layers of conductors are represented by A1, A2, ……, AL-1, AL respectively, and the gate area of the transistor is represented by Ag. Then the judgment criterion for whether there is an antenna effect violation at the gate node of this transistor is whether the value of (A1 + A2 + …… + AL) / Ag exceeds the threshold f. If it exceeds, there is an antenna effect violation; if it does not exceed, there is no violation.

[0047] In some other embodiments, it is possible to determine whether there is an antenna effect violation in the integrated circuit according to whether there is antenna effect violation information recorded in the antenna effect inspection report. If there is antenna effect violation information recorded in the antenna effect inspection report, it is determined that there is an antenna effect violation in the integrated circuit; otherwise, there is no antenna effect violation. In this embodiment, the antenna effect inspection report will only record the antenna effect violation information of the gate nodes of the transistors in the integrated circuit when it is determined that there is an antenna effect violation in the integrated circuit.

[0048] When there is an antenna effect violation in the integrated circuit, execute S3; when there is no antenna effect violation in the integrated circuit, end.

[0049] S3: Based on the antenna effect inspection report and the preset diode standard cell, determine the diode information required to repair the antenna effect violation.

[0050] When there is an antenna effect violation in the integrated circuit, the retrieval report can be parsed with a script. Based on the antenna effect inspection report and the preset diode standard cell, determine the diode information required to repair the antenna effect violation. Among them, the format of the output diode information can be the ASCII format, and its format can be the same as that of the antenna effect inspection report, so that the diode information can be loaded into EDA (Electronic Design Automation) later to visually present the information of the diodes that need to be added.

[0051] Among them, the diode information may include the number of diode standard cells. In addition, the diode information may further include the positions where diode standard cells need to be added subsequently, and these positions can be represented by gate node names. At this time, the diode information may include the gate node names and the number of diode standard cells to be added.

[0052] In some possible implementation manners, the implementation process of S3 may be: obtaining the gate node names (NETs) with antenna effect violations in the antenna effect inspection report; for each gate node name with an antenna effect violation, determining the diode information required to repair the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cells. The gate node names with antenna effect violations can be obtained first, and then for each gate node name with an antenna effect violation, the diode information required to repair the antenna effect violation of each gate node name can be determined one by one.

[0053] If the antenna effect violation includes cumulative antenna violations, in some possible implementation manners, the implementation process of S3 may further be: obtaining the gate node names with antenna effect violations in the antenna effect inspection report; performing redundancy removal processing on multiple antenna effect violation information of the same gate node name, and retaining the antenna effect violation information with the largest antenna violation ratio; for each gate node name with an antenna effect violation after the redundancy removal processing, determining the diode information required to repair the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cells. The gate node names with antenna effect violations can be obtained first, then the redundancy removal processing is performed, and then for each gate node name with an antenna effect violation, the diode information required to repair the antenna effect violation of each gate node name can be determined one by one.

[0054] Among them, the antenna effect violation includes cumulative antenna violations and non-cumulative antenna violations. Suppose the number of effective conductor layers connected by a certain NET is 8 layers, namely M1 to M8. If cumulative antenna effect violations start to occur at layer M6, then there will also be antenna effect violations at M7 and M8. The inspection report will record the antenna effect violation information accumulated to M6, M7, and M8 respectively, that is, the antenna effect violation of this NET will be recorded three times. When performing redundancy removal processing, only the antenna effect violation information accumulated to M8 needs to be obtained, and the redundant information of M7 and M6 is removed to facilitate subsequent calculations. Among them, the antenna violation ratio of the antenna effect violation information accumulated to M8 is the largest. For non-cumulative antenna violations, such as the antenna effect violation of metal vias, no special processing is required.

[0055] The optimization method shown in this application can be applicable to the repair of antenna effect violations of two inspection types, one is with cumulative effect and the other is without cumulative effect.

[0056] For subsequent processing, in a possible implementation, after redundancy removal processing, the NETs with antenna effect violations can be numbered, i.e., NET1, NET2, ……, NETi, where i represents the number of the NET. Subsequently, the diode information required to repair the antenna effect violation of each numbered NET can be determined one by one in the order of the numbers.

[0057] Taking the determination of the number of diode standard cells of a specific gate node name as an example, the diode information includes the number of diode standard cells. When determining the diode information required to repair the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cells, the process may include: obtaining the equivalent gate area of the preset diode standard cells; determining the number of diode standard cells required to repair the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the equivalent gate area of the preset diode standard cells. When determining the number of diode standard cells required to repair the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the equivalent gate area of the preset diode standard cells, it may be to first determine the target gate area required to repair the antenna effect violation based on the antenna effect violation information of the gate node name, and then determine the number of diode standard cells required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the preset diode standard cells.

[0058] In one embodiment, the preset diode standard cells may come from a standard cell library, such as the standard cell library provided by a foundry (fab). The standard cell library provides various types of diode standard cells for repairing antenna effect violations. Assume the area of such diode standard cells is S CELL , and the area of the active region (Diffusion) included in the diode standard cell is S DIFF , S DIFFThe larger the area, the stronger the ability to discharge charges. Therefore, for diode standard cells with the same area, choosing a diode standard cell with a larger active region can achieve higher benefits. At the same time, since the degree of each violation (antenna violation ratio) exceeding the threshold f is different, when selecting a diode standard cell, it can be selected according to the CPP (Contacted PolyPitch) width of the diode standard cell. For example, diode standard cells with three widths of 1CPP, 3CPP, and 5CPP can be selected. In this way, for larger violations (i.e., larger antenna violation ratios), the 5CPP diode standard cell can be added first, and when it is less than one 5CPP, the 3CPP or 1CPP diode standard cell can be added. For smaller violations (i.e., smaller antenna violation ratios), the 1CPP diode standard cell is added first. Among them, the larger the CPP width, the larger the area of the standard cell.

[0059] The preset diode standard cell can be a diode standard cell with a specified CPP width. In some possible implementation manners, the preset diode standard cell can include multiple diode standard cells with different widths (such as CPP widths).

[0060] Among them, the equivalent gate area of the preset diode standard cell is a normalized index for measuring the physical area of the diode standard cell, and it is the standardized area of the diode standard cell relative to the transistor gate area. For example, the S DIFF area of each diode standard cell can be converted into the equivalent gate area of the transistor according to a certain coefficient. The equivalent gate area of the diode standard cell can be represented by Agj’, where j can be an integer greater than or equal to 1 and can represent the number of the diode standard cell. For the three widths of 1CPP, 3CPP, and 5CPP diode standard cells in the above example, the equivalent gate areas are recorded as Ag1’, Ag2’, and Ag3’ in descending order.

[0061] In a possible implementation manner, if the antenna effect violation information includes: the gate node name, the area of the effective conductor connected to the gate node, the gate area of the transistor, and the antenna effect violation threshold, then the process of determining the target gate area required to repair the antenna effect violation based on the antenna effect violation information of the gate node name and the equivalent gate area of the diode standard cell can include: determining the target gate area required to repair the antenna effect violation according to the area of the effective conductor, the gate area, and the antenna effect violation threshold. For example, according to the principle of antenna effect violation, to repair the antenna effect violation, it is necessary that A X / Ag < f. Transforming the above formula gives Ax / f < Ag. Assuming that a diode with a target gate area of Ag’ is added at the violation to repair the violation, then Ax / f < Ag + Ag’, that is, the target gate area Ag’ > Ax / f – Ag.

[0062] When determining the number of diode standard cells required for the antenna effect violation of the repaired gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell, the quotient of Ag’ / Agj’ can be used to determine the number of diode standard cells required. For example, the number of diode standard cells required can be the ceiling of the quotient of Ag’ / Agj’.

[0063] In another possible implementation, if the antenna effect violation information includes: the gate node name, the target gate area required to repair the antenna effect violation of this gate node name, etc., then the process of determining the target gate area required to repair the antenna effect violation based on the antenna effect violation information of the gate node name may include: directly obtaining the target gate area required to repair the antenna effect violation of this gate node name in the antenna effect violation information.

[0064] In a possible implementation, the preset diode standard cell includes multiple diode standard cells with different widths. At this time, the process of determining the number of diode standard cells required for the antenna effect violation of the repaired gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell may include: determining the number of target diode standard cells required for the antenna effect violation of the repaired gate node name according to the target gate area and the equivalent gate area of the target diode standard cell, where the target diode standard cell is the diode standard cell with the smallest equivalent gate area among the multiple diode standard cells. Taking the diode standard cell including the three widths of 1CPP, 3CPP, and 5CPP as an example above, the target diode standard cell is 1CPP. Among them, the larger the CPP width, the larger the area of the standard cell. Using the diode standard cell with the smallest equivalent gate area can minimize the gate area of the repaired gate node while repairing the antenna effect violation of the gate node name.

[0065] In another possible implementation, the target diode standard cell can be the diode standard cell with the largest equivalent gate area among the multiple diode standard cells. At this time, 5CPP in the above example is the target diode standard cell. Using the diode standard cell with the largest equivalent gate area can minimize the number of added diodes while repairing the antenna effect violation of the gate node name.

[0066] In yet another possible implementation, the preset diode standard cell includes a plurality of diode standard cells with different widths. At this time, the process of determining the number of diode standard cells required to repair the antenna effect violation of the repair gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell may include: determining the number of first diode standard cells required to repair the antenna effect violation of the repair gate node name according to the quotient obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell; if the first remainder is not zero, determining the number of second diode standard cells required to repair the antenna effect violation of the repair gate node name according to the quotient obtained by dividing the first remainder by the equivalent gate area of the second diode standard cell.

[0067] Wherein, the first diode standard cell is the diode standard cell with the largest equivalent gate area among the plurality of diode standard cells but smaller than the target gate area, the first remainder is the remainder obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, and the second diode standard cell is the diode standard cell with the largest equivalent gate area among the plurality of diode standard cells but smaller than the first remainder. Taking the diode standard cells with the three widths of 1CPP, 3CPP, and 5CPP as an example above, assuming that the target gate area is greater than the equivalent gate area of 5CPP, the first diode standard cell is the diode standard cell of 5CPP. Similarly, if the first remainder is greater than the equivalent gate area of 3CPP, the second diode standard cell is the diode standard cell of 3CPP.

[0068] In the above embodiment, a plurality of diode standard cells with different widths can be used to repair the antenna effect violation of the repair gate node name. For example, the number of the first diode standard cells is the quotient obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, and the number of the second diode standard cells is the value obtained by rounding up the quotient obtained by dividing the first remainder by the equivalent gate area of the second diode standard cell.

[0069] In a possible implementation, the above optimization method further includes: if the j-th remainder is not zero and the j-th diode standard cell is not the diode standard cell with the smallest equivalent gate area among multiple diode standard cells, determining the number of the (j + 1)-th diode standard cells required to repair the antenna effect violation of the repaired gate node name according to the quotient obtained by dividing the j-th remainder by the equivalent gate area of the (j + 1)-th diode standard cell; ending until the (j + 1)-th remainder is zero, or the (j + 1)-th diode standard cell is the diode standard cell with the smallest equivalent gate area among multiple diode standard cells, where j can be an integer greater than or equal to 2, the j-th remainder is the remainder obtained by dividing the (j - 1)-th remainder by the equivalent gate area of the j-th diode standard cell; the (j + 1)-th diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the j-th remainder among multiple diode standard cells. The schematic diagram of this embodiment is as Figure 2 shown. If the third remainder obtained by dividing the second remainder by the equivalent gate area of the third diode standard cell is not zero, or the third diode standard cell is not the diode standard cell with the smallest equivalent gate area among multiple diode standard cells, the quotient and the fourth remainder obtained by dividing the third remainder by the equivalent gate area of the fourth diode standard cell will be continuously obtained, and so on, until the fourth remainder is zero, or the iteration reaches the diode standard cell with the smallest equivalent gate area among multiple diode standard cells and ends. Among them, the fourth diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the third remainder among multiple diode standard cells.

[0070] Taking the diode standard cells with three widths of 1CPP, 3CPP, and 5CPP as an example above, when determining the number of these three types of diode standard cells, Ag' can be divided by Ag1', and the integer quotient without carrying is denoted as K1. The remainder is then divided by Ag2', and the integer quotient without carrying is denoted as K2. The remainder is then divided by Ag3', and the integer quotient with carrying is denoted as K3. Then, through the above calculation, the numbers of the three types of diodes that need to be added are K1, K2, and K3 respectively. Assuming Ag' is 24.5 nm, Ag1', Ag2', and Ag3' are 5 nm, 3 nm, and 1 nm respectively, then K1 = 4, K2 = 1, and K3 = 2.

[0071] In a similar manner as above, the number of diode standard cells required to repair the antenna effect violation of each gate node name can be determined. After determining the number of diode standard cells of one gate node name, continue to determine the number of diode standard cells of the next gate node name until all gate node names are analyzed. After the analysis is completed, the number of diode standard cells required to repair each gate node name in ASCII format is output. Subsequently, diode standard cells can be added in the placement and routing tool according to the diode information in this ASCII format, thereby completing the optimization and repair of the integrated circuit.

[0072] In a possible implementation manner, the principle of the optimization method for the integrated circuit shown in the present application can be as Figure 3 shown. In this implementation manner, when there is an antenna effect violation in the integrated circuit, redundant processing can be performed on multiple antenna effect violation messages with the same gate node name in the inspection report, and the antenna effect violation message with the largest antenna violation ratio is retained. After that, each gate node name NET with an antenna effect violation after redundant processing is numbered, and then, in the order of the numbers, the diode information required to repair the antenna effect violation of each numbered gate node name is determined one by one until all the numbered gate node names are processed. Finally, the number and position of the diode standard cells required to repair each gate node name in ASCII format are obtained. Among them, Figure 3 the principle shown is only one of many method embodiments of the present application. Therefore, it cannot be understood as the only embodiment of the optimization method shown in the present application.

[0073] The embodiment of the present application also provides an optimization device for an integrated circuit, as Figure 4 shown. The optimization device for the integrated circuit includes: an acquisition module, a detection module, and a determination module.

[0074] Among them, the acquisition module is used to acquire the antenna effect inspection report of the integrated circuit.

[0075] The detection module is used to determine whether there is an antenna effect violation in the integrated circuit according to the antenna effect inspection report.

[0076] The determination module is used to determine the diode information required to repair the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell when there is an antenna effect violation in the integrated circuit, where the diode information is used to optimize and repair the antenna effect violation of the integrated circuit.

[0077] The antenna effect inspection report includes: the antenna effect violation information of the gate nodes of the transistors in the integrated circuit; the determination module is specifically used for: acquiring the gate node names with antenna effect violations in the antenna effect inspection report; for each gate node name with an antenna effect violation, determining the diode information required to repair the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cell.

[0078] If the antenna effect violates the inclusion of cumulative antenna violations, the antenna effect inspection report includes: antenna effect violation information of the gate nodes of transistors in the integrated circuit; a determination module, specifically configured to: obtain the names of the gate nodes with antenna effect violations in the antenna effect inspection report; perform redundancy removal processing on multiple antenna effect violation information of the same gate node name, and retain the antenna effect violation information with the largest antenna violation ratio; for each gate node name with antenna effect violations after redundancy removal processing, based on the antenna effect violation information of the gate node name and the preset diode standard cell, determine the diode information required to repair the antenna effect violation of the gate node name.

[0079] The diode information includes the number of diode standard cells; the determination module, specifically configured to: obtain the equivalent gate area of the preset diode standard cell; determine the target gate area required to repair the antenna effect violation based on the antenna effect violation information of the gate node name; based on the target gate area and the equivalent gate area of the preset diode standard cell, determine the number of diode standard cells required to repair the antenna effect violation of the gate node name.

[0080] The antenna effect violation information includes: the gate node name, the area of the effective conductor connected to the gate node, the gate area of the transistor, and the antenna effect violation threshold, where the effective conductor refers to the conductor that is connected to the gate node and actually participates in collecting charges and can transmit them to the gate node; the determination module, specifically configured to: determine the target gate area required to repair the antenna effect violation according to the area of the effective conductor, the gate area, and the antenna effect violation threshold.

[0081] The preset diode standard cell includes multiple diode standard cells with different widths; the determination module, specifically configured to: determine the number of first diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, where the first diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the target gate area among the multiple diode standard cells; if the first remainder is not zero, determine the number of second diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the first remainder by the equivalent gate area of the second diode standard cell, where the first remainder is the remainder obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, and the second diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the first remainder among the multiple diode standard cells.

[0082] The determination module is further specifically used for: if the jth remainder is not zero, and the jth diode standard unit is not the diode standard unit with the smallest equivalent gate area among the multiple diode standard units, determining the number of j+1th diode standard units required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the jth remainder by the equivalent gate area of ​​the j+1th diode standard unit; wherein j is an integer greater than or equal to 2, the jth remainder is the remainder obtained by dividing the j-1th remainder by the equivalent gate area of ​​the jth diode standard unit; the j+1th diode standard unit is the diode standard unit with the largest equivalent gate area among the multiple diode standard units but less than the jth remainder; until the j+1th remainder is zero, or the j+1th diode standard unit is the diode standard unit with the smallest equivalent gate area among the multiple diode standard units.

[0083] The preset diode standard unit includes multiple diode standard units with different widths; a determination module is specifically used to: determine the number of target diode standard units required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of ​​the target diode standard unit, wherein the target diode standard unit is the diode standard unit with the smallest equivalent gate area among the multiple diode standard units.

[0084] The integrated circuit optimization device provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0085] like Figure 5 As shown, Figure 5 The structure block diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device comprises: a transceiver, a memory, a communication bus and a processor.

[0086] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory is used to store computer programs, such as Figure 4 The software function module shown in is an optimization device for integrated circuits. The optimization device for integrated circuits includes at least one software function module that can be stored in the memory in the form of software or firmware or solidified in the operating system (OS) of the electronic device. The processor is used to execute the executable module stored in the memory, such as the software function module or computer program included in the optimization device for integrated circuits. For example, the processor is used to execute the above-mentioned optimization method for integrated circuits.

[0087] Among them, the memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0088] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit, a Multimedia Application Processor (MAP), a microprocessor, etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. Or the processor may also be any conventional processor, etc.

[0089] Among them, the above-mentioned electronic devices include, but are not limited to, computers, servers, etc.

[0090] The embodiments of the present application also provide a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium). A computer program is stored on the storage medium. When the computer program is run by a computer such as the above-mentioned electronic device, it executes the optimization method of the integrated circuit shown above.

[0091] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a computer, it executes the optimization method of the integrated circuit as described above.

[0092] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0093] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0094] In addition, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0095] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions for causing a computer device (which may be a personal computer, a laptop, a server, or an electronic device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0096] As described above, the above are only specific implementation manners of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. An optimization method for an integrated circuit, characterized in that, Including: Obtaining an antenna effect inspection report of an integrated circuit; Determining whether there is an antenna effect violation in the integrated circuit according to the antenna effect inspection report; When there is an antenna effect violation in the integrated circuit, determining diode information required for repairing the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell; Wherein, the diode information is used to optimize the repair of the antenna effect violation of the integrated circuit.

2. The optimization method according to claim 1, wherein The antenna effect inspection report includes: antenna effect violation information of the gate nodes of transistors in the integrated circuit; determining diode information required for repairing the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell, including: Obtaining the names of the gate nodes with antenna effect violations in the antenna effect inspection report; For each name of the gate node with an antenna effect violation, determining diode information required for repairing the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cell.

3. The optimization method according to claim 1, wherein If the antenna effect violation includes an accumulative antenna violation, the antenna effect inspection report includes: antenna effect violation information of the gate nodes of transistors in the integrated circuit; determining diode information required for repairing the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell, including: Obtaining the names of the gate nodes with antenna effect violations in the antenna effect inspection report; Performing redundancy removal processing on multiple antenna effect violation information of the same gate node name, and retaining the antenna effect violation information with the largest antenna violation ratio; For each name of the gate node with an antenna effect violation after the redundancy removal processing, determining diode information required for repairing the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cell.

4. The optimization method according to claim 2 or 3, characterized in that The diode information includes the number of diode standard cells; determining diode information required for repairing the antenna effect violation of the gate node name based on the antenna effect violation information of the gate node name and the preset diode standard cell, including: Obtaining the equivalent gate area of the preset diode standard cell; Determining the target gate area required for repairing the antenna effect violation based on the antenna effect violation information of the gate node name; Determining the number of diode standard cells required for repairing the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell.

5. The optimization method according to claim 4, characterized in that, The antenna effect violation information includes: the name of the gate node, the area of the effective conductor connected to the gate node, the gate area of the transistor, and the antenna effect violation threshold, wherein the effective conductor refers to the conductor that is connected to the gate node and actually participates in collecting charges and can transmit them to the gate node; Determining the target gate area required for repairing the antenna effect violation based on the antenna effect violation information of the gate node name, including: Determining the target gate area required for repairing the antenna effect violation according to the area of the effective conductor, the gate area, and the antenna effect violation threshold.

6. The optimization method according to claim 4, characterized in that The preset diode standard cell includes a plurality of diode standard cells with different widths; Determining the number of diode standard cells required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell includes: Determining the number of first diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, where the first diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the target gate area among the plurality of diode standard cells; If the first remainder is not zero, determining the number of second diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the first remainder by the equivalent gate area of the second diode standard cell, where the first remainder is the remainder obtained by dividing the target gate area by the equivalent gate area of the first diode standard cell, and the second diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the first remainder among the plurality of diode standard cells.

7. The optimization method according to claim 6, wherein The method further includes: If the j-th remainder is not zero and the j-th diode standard cell is not the diode standard cell with the smallest equivalent gate area among the plurality of diode standard cells, determining the number of (j + 1)-th diode standard cells required to repair the antenna effect violation of the gate node name according to the quotient obtained by dividing the j-th remainder by the equivalent gate area of the (j + 1)-th diode standard cell; where j is an integer greater than or equal to 2, the j-th remainder is the remainder obtained by dividing the (j - 1)-th remainder by the equivalent gate area of the j-th diode standard cell; the (j + 1)-th diode standard cell is the diode standard cell with the largest equivalent gate area but smaller than the j-th remainder among the plurality of diode standard cells; Ending until the (j + 1)-th remainder is zero, or the (j + 1)-th diode standard cell is the diode standard cell with the smallest equivalent gate area among the plurality of diode standard cells.

8. The optimization method according to claim 4, wherein The preset diode standard cell includes a plurality of diode standard cells with different widths; determining the number of diode standard cells required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the preset diode standard cell includes: Determining the number of target diode standard cells required to repair the antenna effect violation of the gate node name according to the target gate area and the equivalent gate area of the target diode standard cell, where the target diode standard cell is the diode standard cell with the smallest equivalent gate area among the plurality of diode standard cells.

9. An optimization device for an integrated circuit, characterized in that, Including: An acquisition module, configured to acquire an antenna effect inspection report of an integrated circuit; A detection module, configured to determine whether the integrated circuit has an antenna effect violation according to the antenna effect inspection report; A determination module, configured to, when the integrated circuit has an antenna effect violation, determine diode information required to repair the antenna effect violation based on the antenna effect inspection report and a preset diode standard cell; Wherein, the diode information is used to optimize and repair the antenna effect violation of the integrated circuit.

10. An electronic device, characterized in that, Comprising: A memory and a processor, the processor being connected to the memory; The memory is used for storing programs; The processor is used for calling the program stored in the memory to execute the method according to any one of claims 1-8.

11. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and when the computer program is run by a processor, the method according to any one of claims 1-8 is executed.

12. A computer program product, characterized in that, The computer program product includes a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1-8 is implemented.

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