Method and device for operating SPEC CPU in simulator user mode

Abstract

The invention discloses a method and device for operating an SPEC CPU in a simulator user mode. The method comprises the steps that a system operation environment is configured, and an SPEC CPU test suite, a cross compiling tool chain and a simulator are installed; compiling the SPEC CPU test suite through the cross compiling tool to obtain an executable file of a given instruction set architecture; obtaining an execution command and a verification command of the executable file, and summarizing to generate an execution script of the simulator in a user mode; and running the execution script. According to the method, the SPEC CPU can be completely operated in a simulator user mode, so that function verification and performance evaluation can still be performed on an instruction set, a compiler, a runtime library and the like in the absence of hardware, the verification and evaluation process is simplified, and meanwhile, the occupation of software resources is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer software, and particularly to a method and device for implementing the operation of SPEC CPU in the user mode of a simulator. Background Art

[0002] Benchmark programs are a set of programs specifically used for performance evaluation, which can well reflect the performance of a machine when running actual loads. The running time of the same benchmark program on different machines can be compared to evaluate its performance. For different application scenarios, different benchmark programs should be selected. However, there are also some defects in using benchmark programs for computer performance evaluation, because the performance of benchmark programs may be closely related to a small section of short code, and hardware system designers or compiler developers may perform special optimizations on these code segments, making the execution speed of this code very fast, so that accurate performance evaluation results cannot be obtained.

[0003] SPEC CPU is a standard performance test suite developed by the non-profit Standard Performance Evaluation Corporation (SPEC) for evaluating computing performance. Its test loads come from real user applications and can be used for testing various types of hardware. The SPEC CPU test suite is generally composed of the above-mentioned benchmark programs. To adapt to the development of computer hardware and software, SPEC CPU has gone through several generations of updates and iterations. Starting from the earliest SPEC CPU 92, SPEC CPU 95, 2000, and 2006 have been successively released. Currently, these versions have all retired, and SPEC officially no longer maintains the code. The current latest version is SPEC CPU 2017, which was released in 2017.

[0004] An emulator, such as the QEMU (Quick EMUlator) emulator, is a powerful open-source emulator that can simulate various hardware architectures, including x86, ARM, MIPS, etc. The support for the RISC-V instruction set by the QEMU emulator is also continuously evolving and improving. QEMU has two main operating modes: System mode and User mode. System mode is also known as the system mode. In this mode, QEMU can simulate the entire computer system, including the central processing unit and other peripheral devices. User mode is also known as the user mode. In this mode, QEMU only provides simulation of the instruction set and can run binary executable programs of different architectures on the host operating system. Compared with the system mode of QEMU, the user mode of QEMU has the advantages of simple operation and high execution efficiency, which is very useful for developing and testing cross-platform applications or porting software.

[0005] RISC-V is an emerging open-source reduced instruction set architecture first released by the University of California, Berkeley in 2010. It is born out of the various problems exposed by the long-term development of existing architectures (such as x86, ARM, MIPS, etc.) and conforms to the design requirements of modern information systems and the development trend of architectures. The RISC-V instruction set architecture is open-source, free, open, and free. Any organization and individual can freely and equally use the RISC-V instruction set architecture. At the same time, as a newly designed architecture from scratch, it absorbs the advantages of existing architectures and eliminates the consideration of historical legacy issues and the dependence on old technologies. The RISC-V instruction set architecture adopts a modular design, supports the expansion of the instruction set, and has strong system customization capabilities. The documentation of the RISC-V instruction set architecture is concise, and the learning threshold is lower. Therefore, in recent years, the research on the RISC-V instruction set architecture has become a hot topic in academia and industry, and many breakthrough results have emerged. Due to its advantages in resource dependence, low power consumption, ease of use, customizability, scalability, etc., it can efficiently, quickly, and at low cost complete system-level tasks in their respective fields.

[0006] In the construction and development of the hardware and software ecosystem based on the RISC-V instruction set architecture, it is often necessary to perform functional verification and performance evaluation on the instruction set, compiler, runtime library, etc. Using an emulator can still verify and evaluate the software of the RISC-V instruction set architecture in the absence of actual hardware. Due to the high recognition of SPEC CPU in the industry and its standardized design, it has become the preferred test benchmark in software verification and evaluation work.

[0007] However, in the existing technology, running SPEC CPU in the system mode of the simulator requires a large amount of memory and storage space, and also requires the support of a complete operating system. The test running time is too long and the operation is complex, which will discourage developers. Moreover, SPEC CPU lacks the interface of the simulator, so that currently it is still impossible to fully run SPEC CPU in the user mode of the simulator, and thus it is impossible to efficiently perform functional verification and performance evaluation on the target instruction set architecture, compiler, etc.

[0008] Therefore, in view of the above defects in the existing technology, it is very necessary to provide a method, device, system and computer-readable storage medium for realizing the running of SPEC CPU in the user mode of the simulator. Summary of the Invention

[0009] In view of the above problems in the existing technology, the present invention provides a method, device, system and computer-readable storage medium for realizing the running of SPEC CPU in the user mode of the simulator.

[0010] For this purpose, it includes the following aspects:

[0011] In a first aspect, a method for realizing the running of SPEC CPU in the user mode of the simulator includes:

[0012] S1, configuring the system running environment, installing the SPEC CPU test suite, cross-compilation toolchain and simulator;

[0013] S2, compiling the SPEC CPU test suite through the cross-compilation toolchain to obtain an executable file for a given instruction set architecture;

[0014] S3, obtaining the execution command and verification command of the executable file, and aggregating and generating an execution script for the simulator in the user mode;

[0015] S4, running the execution script.

[0016] Further, the simulator is a QEMU (Quick EMUlator) simulator.

[0017] Further, the given instruction set architecture is the RISC-V instruction set architecture.

[0018] Further, the given instruction set architecture is the ARM instruction set architecture.

[0019] Further, the step S2 of compiling the SPEC CPU test suite through the cross-compilation toolchain to obtain an executable file for a given instruction set architecture includes:

[0020] Modify the configuration file provided by the SPEC CPU test suite to make it applicable to cross-compiling target binaries for a second processor architecture on a first processor architecture, obtaining a modified configuration file;

[0021] Use the obtained modified configuration file to cross-compile the SPEC CPU test suite.

[0022] Further, in S3, obtain the execution command and verification command of the executable file, and summarize and generate an execution script for the simulator in user mode, including:

[0023] Obtain the execution command and verification command of the SPEC CPU test suite;

[0024] Write the corresponding execution module for the benchmark program of the SPEC CPU test suite in the user mode of the simulator;

[0025] Write the corresponding result verification module for the benchmark program of the SPEC CPU test suite in the user mode of the simulator;

[0026] Write the corresponding score calculation and report generation module for the benchmark program of the SPEC CPU test suite in the user mode of the simulator;

[0027] Based on the above execution module, result verification module, and score calculation and report generation module, construct the execution script for the simulator in user mode.

[0028] Further, the score calculation and report generation module includes functions for implementing the calculation of scores and overall performance metrics for each benchmark program.

[0029] In a second aspect, a device for implementing the operation of SPEC CPU in the user mode of a simulator includes:

[0030] A configuration unit for configuring the system running environment, installing the SPEC CPU test suite, cross-compilation toolchain, and simulator;

[0031] A compilation unit for compiling the SPEC CPU test suite through the cross-compilation tool to obtain an executable file for a given instruction set architecture;

[0032] A script generation unit for obtaining the execution command and verification command of the executable file, and summarizing and generating an execution script for the simulator in user mode;

[0033] A script execution unit for running the execution script.

[0034] In a third aspect, an operating system includes a processor and a memory. The processor executes computer instructions stored in the memory to implement the method for running SPEC CPU in the user mode of the simulator as described in any one of the above.

[0035] In a fourth aspect, a computer-readable storage medium is used to store non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a computer, the computer is caused to execute the method for running SPEC CPU in the user mode of the simulator as described in any one of the above.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] The method, device, system and computer-readable storage medium for running SPEC CPU in the user mode of the simulator provided by the present invention can completely run SPEC CPU in the user mode of the simulator, and thus efficiently perform functional verification and performance evaluation on the target instruction set architecture, compiler, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a flowchart of a method for running SPEC CPU in the user mode of the simulator according to an embodiment of the present invention.

[0039] Figure 2 is a structural diagram of the SPEC CPU2017 test suite according to an embodiment of the present invention.

[0040] Figure 3 is a schematic flow diagram of compiling the SPEC CPU test suite by the cross-compilation tool to obtain an executable file for a given instruction set architecture according to an embodiment of the present invention;

[0041] Figure 4 is a schematic flow diagram of obtaining the execution command and verification command of the executable file and summarizing them to generate an execution script for the simulator in the user mode according to an embodiment of the present invention;

[0042] Figure 5 is a structural diagram of a device for running SPEC CPU in the user mode of the simulator according to an embodiment of the present invention.

[0043] Figure 6 is a schematic structural diagram of a computer system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0045] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present invention, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0046] It should also be noted that the drawings provided in the following embodiments only schematically illustrate the basic concept of the present invention. The drawings only show the components related to the present invention, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0047] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0048] In the prior art, running SPEC CPU in the system mode of the emulator consumes a large amount of memory and storage space. At the same time, it requires the support of a complete operating system, the test running time is too long, and the operation is complex, which will discourage developers. Moreover, SPEC CPU lacks the interface of the emulator, so that currently it is still impossible to completely run SPEC CPU in the user mode of the emulator, and thus it is impossible to efficiently perform functional verification and performance evaluation on the target instruction set architecture, compiler, etc. In view of the above problems in the prior art, in one embodiment, a method for implementing the running of SPEC CPU in the user mode of the emulator is provided, including: configuring the system running environment, installing the SPEC CPU test suite, the cross-compilation toolchain and the emulator; compiling the SPEC CPU test suite through the cross-compilation tool to obtain an executable file for a given instruction set architecture; obtaining the execution command and the verification command of the executable file, and aggregating and generating an execution script for the emulator in the user mode; running the execution script. It can completely run SPEC CPU in the user mode of the emulator, and thus efficiently perform functional verification and performance evaluation on the target instruction set architecture, compiler, etc.

[0049] Figure 1 A method for implementing the running of SPEC CPU in the user mode of the emulator according to an embodiment of the present invention includes:

[0050] S1, configuring the system running environment, installing the SPEC CPU test suite, the cross-compilation toolchain and the emulator;

[0051] In one embodiment, as Figure 3 shown, in this step, install SPEC CPU2017, the RISC-V cross-compilation toolchain and qemu-riscv64 on the x86 test machine to form a software test environment; wherein, the emulator is the QEMU (Quick EMUlator) emulator; the given instruction set architecture is the RISC-V instruction set architecture; the SPEC CPU may also include any other version, and the present invention does not make specific limitations.

[0052] In addition to the QEMU (Quick EMUlator) emulator, the emulator also includes the Gem5 emulator, the VirtualBox emulator, etc.;

[0053] The given instruction set architecture, in addition to the RISC-V instruction set architecture, also includes instruction set architectures such as x86, ARM, and MIPS.

[0054] In one embodiment, the SPEC CPU2017 test suite is installed, which is one of the objective and reliable benchmark programs for current CPU performance evaluation. The SPEC CPU2017 test suite includes 43 benchmark programs, which are divided into 4 groups corresponding to 4 overall performance metrics, namely intspeed, fpspeed, intrate, and fprate. Each benchmark program contains multiple input sets (workloads). In the present invention, the above 43 benchmark programs will be sequentially executed serially in the QEMU user mode on the x86 host machine, the running time of each program will be recorded, the scores of each sub-item and the 4 overall performance metrics will be calculated, and finally a test report will be generated. As Figure 2 shown, the structural composition of the SPEC CPU2017 test suite is shown.

[0055] In one embodiment, the User mode of the QEMU emulator is also the user mode. In this user mode, the QEMU emulator only provides simulation of the instruction set and can run binary executable programs of different architectures on the host operating system. Compared with the system mode of the QEMU emulator, the user mode of the QEMU emulator has the advantages of simple operation and high execution efficiency, which is very useful for developing and testing cross-platform applications or porting software.

[0056] In one embodiment, for example, for the ARM instruction set architecture, this step is to install the SPECCPU2017, ARM cross-compilation toolchain, and the qemu-arm-static QEMU emulator on the test machine;

[0057] Similar operations are performed for other architectures and will not be elaborated here.

[0058] S2, compile the SPEC CPU test suite through the cross-compilation tool to obtain an executable file for a given instruction set architecture;

[0059] In one embodiment, the SPEC CPU2017 test suite is cross-compiled on the test machine to obtain a binary executable file for the specified architecture; the executable file can also be in other formats, such as ELF.

[0060] In one embodiment, as Figure 3 shown, step S2 specifically includes:

[0061] S21. Modify the configuration file provided by SPEC CPU2017 to make it applicable to cross-compiling target binaries for the second processor architecture on the first processor architecture, resulting in a modified configuration file. For example, modify the sample configuration file provided by SPEC CPU2017 to make it applicable to cross-compiling RISC-V target binaries on x86, resulting in a modified configuration file.

[0062] The modifications to the project mainly include the compiler path, -march parameter, and -sysroot parameter;

[0063] -march parameter

[0064] The -march parameter is used to specify the architecture of the target processor.

[0065] For example, in the RISC-V architecture, specify -march=rv64gc; in the ARM architecture, -march=armv7. (This is just an example, and it is determined according to the actual processor microarchitecture.)

[0066] -sysroot parameter

[0067] The -sysroot parameter is used to link to find the corresponding dynamic library. Especially in a cross-compilation environment, without the sysroot parameter, other parts of the parameters will become invalid, and the specified path cannot be added to the search path list of the link library, ultimately resulting in a "not found" error message.

[0068] For example, in the RISC-V architecture, specify -sysroot= / opt / riscv / sysroot.

[0069] S22. Use the modified configuration file obtained in step S21 and use the runcpu command to achieve cross-compilation of SPEC CPU2017;

[0070] runcpu -c my-gcc-linux-riscv.cfg --action=runsetup all

[0071] where my-gcc-linux-riscv.cfg is the configuration file obtained in S21; --action is specified as runsetup, which means only creating the run directory without running the benchmark programs; all means operating on all 43 benchmark programs.

[0072] S3. Obtain the execution command and verification command of the executable file, and summarize and generate the execution script of the simulator in user mode;

[0073] In one embodiment, obtain the execution command and verification command of the binary executable file of SPEC CPU2017, and summarize and generate an execution script in the user mode of the Qemu emulator. This script includes three parts: 1. Benchmark program execution module, 2. Program result verification module, 3. Score calculation and report generation module;

[0074] In one embodiment, as Figure 4 shown, step S3 specifically includes:

[0075] S31, obtain the execution command and verification command of the SPEC CPU test suite;

[0076] Enter the run directory of each benchmark program in SPEC CPU2017, and use the specinvoke -n command to obtain the execution command of the program; use specinvoke -n compare.cmd to obtain the verification command of the program, where the verification command is used to verify whether the program execution result is correct;

[0077] Taking the benchmark program 503.bwaves_r as an example, the execution command and verification command are shown as follows:

[0078]

[0079] The above code shows the execution command of 503.bwaves_r. 503.bwaves_r has 4 input sets (workloads), corresponding to 4 execution commands.

[0080]

[0081] The above code shows the verification command of 503.bwaves_r, corresponding to 4 input sets, and there are 4 result verification commands.

[0082] In this step, collect the execution commands and verification commands of 43 benchmark programs, that is, there are 43 groups of execution commands and 43 groups of verification commands. Add $SPEC / bin / harness / to the PATH ($SPEC is the root directory of SPEC CPU2017):

[0083] export PATH=”$SPEC / bin / harness / :$PATH”

[0084] S32, write the corresponding execution module of the benchmark program of the SPEC CPU test suite in the user mode of the emulator;

[0085] Benchmark program execution module for writing scripts: Summarize the 43 groups of execution commands obtained in step S31, where each execution command is executed using qemu-riscv, and use the time command to obtain the running time of each program;

[0086] Taking 503.bwaves_r as an example, the execution command is similar to the following code:

[0087]

[0088] The above shows the command for running 503.bwaves_r using qemu-riscv in the execution module;

[0089] S33. Write the corresponding result verification module of the benchmark program of the SPEC CPU test suite in the user mode of the simulator;

[0090] Benchmark program result verification module for writing scripts: Summarize the 43 groups of verification commands obtained in step S31 and write the benchmark program result verification module.

[0091] Taking 503.bwaves_r as an example, the verification command is as follows:

[0092]

[0093] The above shows the verification command for 503.bwaves_r in the benchmark program result verification module;

[0094] The verification result is saved in the out.cmp file. When the number of lines in the file is greater than 1, it means that the running result of the benchmark program is incorrect.

[0095] S34. Write the corresponding score calculation and report generation module of the benchmark program of the SPEC CPU test suite in the user mode of the simulator;

[0096] The score

[0097] The score calculation and report generation module includes the function of calculating the scores and overall performance indicators of each benchmark program.

[0098] Among them, the single benchmark program score calculation method includes, first, judging whether the verification of all workloads passes. If all pass, the benchmark program runs successfully. Then, add up the execution times of all workloads to obtain the execution time of the benchmark program, and obtain the score of the benchmark program through the following calculation formula:

[0099] time on a reference machine / time on the SUT

[0100] Among them, "time on a reference machine" is the running time of the benchmark program on the reference machine. Refer to the official SPEC CPU documentation; "time on the SUT" is the actual running time of the benchmark program in the above steps.

[0101] Among them, the overall performance metrics can be, for example, four overall performance metrics: speedint, speedfp, rateint, and ratefp. Each performance metric is the geometric mean of the scores of all benchmark programs in the group.

[0102] Finally, print out the scores of each benchmark program and the four overall performance metrics.

[0103] S35. Based on the above execution module, result verification module, and score calculation and report generation module, construct the execution script of the simulator in user mode.

[0104] S4. Run the execution script.

[0105] In one embodiment, in the user mode of the QEMU simulator, execute the execution script obtained in S3. Running the execution script in the user mode of the QEMU simulator to implement the complete process of SPEC CPU. Compared with the QEMU system mode, the QEMU user mode can run directly in the host environment, reducing the overhead of hardware resources and eliminating the need for the configuration of a complete software stack. At the same time, the execution efficiency is much higher.

[0106] In summary, the method for implementing the running of SPEC CPU in the user mode of the simulator provided by the present invention will greatly simplify the verification and evaluation process of the software of the given instruction set architecture because it uses the user mode of the simulator to run SPEC CPU.

[0107] Figure 5 This is a device for implementing the running of SPEC CPU in the user mode of the simulator of the present invention, including:

[0108] The test machine software configuration unit 1 is used to configure the system running environment, install the SPEC CPU test suite, cross-compilation toolchain, and simulator;

[0109] The RISC-V oriented CPU2017 cross-compilation unit 2 is used to compile the SPEC CPU test suite through the cross-compilation tool to obtain an executable file of the given instruction set architecture;

[0110] The QEMU user mode execution CPU2017 script generation unit 3 is used to obtain the execution command and verification command of the executable file, and summarize and generate the execution script of the simulator in the user mode;

[0111] A script execution unit, 4, for running the execution script.

[0112] In addition, an embodiment of the present invention may be a structural diagram of a device for implementing QEMU / RISC-V user mode to run SPEC CPU.

[0113] The foregoing embodiments describe methods and devices for implementing the operation of SPEC CPU in the user mode of the simulator. In a possible design, the foregoing methods, devices, and systems for implementing the operation of SPEC CPU in the user mode of the simulator may be integrated into an electronic device. The electronic device may include a processor and a memory.

[0114] The memory is used to store a program that supports the processor to execute the method for implementing the operation of SPEC CPU in the user mode of the simulator in any of the foregoing embodiments, and the processor is configured to execute the program stored in the memory.

[0115] The storage is used to store one or more computer instructions, where the one or more computer instructions are executed by the processor to implement the steps in the foregoing embodiments, and the steps are not described herein again.

[0116] Figure 6 It is a schematic structural diagram of a computer system according to an embodiment of the present invention. As Figure 6 shown, the computer system 600 includes a processor (CPU, GPU, FPGA, etc.) 601, which can execute some or all of the processing in the foregoing embodiments shown in the accompanying drawings according to a program stored in the read-only memory (ROM) 602 or a program loaded from the storage section 608 into the random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the system 600 are also stored. The processor 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. The input / output (I / O) interface 605 is also connected to the bus 604.

[0117] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that a computer program read from it can be installed into the storage section 608 as needed.

[0118] In particular, according to an embodiment of the present application, the method described above with reference to the accompanying drawings can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program tangibly embodied on a machine-readable medium, and the computer program includes program code for performing the method in the accompanying drawings. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 609, and / or installed from a removable medium 611.

[0119] It should be noted that the computer-readable medium in the present invention can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0120] The above computer-readable medium can be included in the above electronic device; or it can exist separately without being assembled into the electronic device.

[0121] The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device is caused to implement all or part of the steps of the multi-modal interaction implementation method of the various embodiments of the present invention described above.

[0122] Alternatively, the above computer-readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to perform all or part of the steps of the multi-modal interaction implementation method according to the foregoing embodiments of the present invention.

[0123] Computer program code for performing the operations of the present invention may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0124] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that, in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0125] The units described in the embodiments of the present invention may be implemented in software or in hardware. Among them, the name of the unit does not constitute a limitation to the unit itself in some cases. For example, the first acquisition unit may also be described as "the unit for acquiring at least two Internet protocol addresses".

[0126] The above description is only a preferred embodiment of the present invention and an explanation of the technical principles applied. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present invention.

Claims

1. A method for implementing the operation of SPEC CPU in the user mode of the simulator, characterized in that, Including: S1, configure the system running environment, install the SPEC CPU test suite, cross-compilation toolchain and simulator; S2, compile the SPEC CPU test suite through the cross-compilation tool to obtain an executable file for a given instruction set architecture; S3, obtain the execution command and verification command of the executable file, and aggregate them to generate an execution script for the simulator in user mode; S4, run the execution script.

2. The method according to claim 1, characterized in that, The simulator is a QEMU simulator.

3. The method according to claim 1, characterized in that The given instruction set architecture is the RISC-V instruction set architecture.

4. The method according to claim 1, wherein The given instruction set architecture is the ARM instruction set architecture.

5. The method according to claim 1, characterized in that The step S2, compiling the SPEC CPU test suite through the cross-compilation tool to obtain an executable file for a given instruction set architecture, includes: S21, modify the configuration file provided by the SPEC CPU test suite to make it suitable for cross-compiling target binary files for a second processor architecture on a first processor architecture, to obtain a modified configuration file; S22, use the obtained modified configuration file to cross-compile the SPEC CPU test suite.

6. The method according to claim 1, characterized in that, The S3, obtaining the execution command and verification command of the executable file, and aggregating them to generate an execution script for the simulator in user mode, includes: S31, obtain the execution command and verification command of the SPEC CPU test suite; S32, write the corresponding execution module for the benchmark program of the SPEC CPU test suite in the user mode of the simulator; S33, write the corresponding result verification module for the benchmark program of the SPEC CPU test suite in the user mode of the simulator; S34, write the corresponding score calculation and report generation module for the benchmark program of the SPEC CPU test suite in the user mode of the simulator; S35, build an execution script for the simulator in user mode based on the above execution module, result verification module and score calculation and report generation module.

7. The method according to claim 6, characterized in that The score calculation and report generation module includes functions for calculating the scores of each benchmark program and overall performance metrics.

8. A device for implementing the operation of SPEC CPU in the user mode of a simulator, characterized in that, Including: A configuration unit for configuring the system running environment, installing the SPEC CPU test suite, cross-compilation toolchain and simulator; A compilation unit for compiling the SPEC CPU test suite through the cross-compilation tool to obtain an executable file for a given instruction set architecture; A script generation unit for obtaining the execution command and verification command of the executable file, and aggregating them to generate an execution script for the simulator in user mode; A script execution unit for running the execution script.

9. An operating system, comprising: The system includes a processor and a memory, and the processor executes computer instructions stored in the memory to implement the running method according to any one of claims 1-7.

10. A computer-readable storage medium for storing non-transitory computer-readable instructions, which when executed by a computer, cause the computer to execute the running method according to any one of claims 1-7.

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