PCBA processing component layout optimization method and system

Abstract

The present application relates to printed circuit board assembly (PCBA) manufacturing technology field, disclose a kind of PCBA processing component layout optimization method and system.The method is applied to the processing control platform connected with multiple design terminals, each design terminal has only project identification code.After receiving layout optimization request, parse layout constraint text information to determine component layout type.If it is the first layout type of high-density integration, match the first layout parameter set to generate the first optimization result set combined with efficiency factor;If it is the second layout type of high heat dissipation demand, then match the second layout parameter set, generate the second optimization result set combined with heat dissipation factor and efficiency factor.Finally, the optimization result is pushed to the corresponding design terminal.The method and system can improve the layout design efficiency, optimize the layout quality, meet the diversified needs of multiple projects, improve the process compatibility and thermal management capability, effectively solve the component layout problem in PCBA processing.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board assembly (PCBA) manufacturing, and in particular to a method and system for optimizing the layout of components in PCBA processing. Background Art

[0002] In modern electronic device manufacturing, PCBA processing is a key step. The rationality of its component layout has a profound impact on electronic product performance, production efficiency, and cost control. With the rapid development of electronic technology, electronic products are evolving towards miniaturization, multi-functions, and high performance, which places higher demands on the layout of PCBA processing components.

[0003] Early electronic products had relatively simple functions, few components, and were large in size. Layout design was largely based on experience, focusing on the basic implementation of electrical connections. Today, however, high-density integration has become the mainstream trend. Take smartphones, for example. The motherboard integrates a large number of high-performance components, including central processing units, baseband chips, and memory chips, creating an increasingly compact space. In this situation, traditional layout methods can easily lead to severe signal interference. Signal traces between different chips can intersect and couple with each other, causing problems such as signal delays and distortion, impacting mobile phone performance, such as communication and computing speed. Furthermore, due to an unreasonable layout, component installation becomes more difficult during production, reducing the efficiency of equipment such as placement machines, and increasing production costs and cycle times.

[0004] At the same time, high heat dissipation requirements are also a major challenge facing current PCBA processing. High-power components such as the graphics processing units (GPUs) in high-performance computers and the central processing units (CPUs) in servers generate significant amounts of heat during operation. Poor heat dissipation design can lead to excessive component temperatures, which can not only degrade performance but also damage hardware and shorten product lifespan. Existing heat dissipation measures, such as adding heat sinks and fans, can also fail to achieve the desired cooling effect if their layout is not appropriate. For example, insufficient contact area between the heat sink and the heat-generating component, an excessively long heat conduction path, or improper fan placement can prevent effective heat removal, all of which can affect the stability and reliability of the entire system.

[0005] Furthermore, different design endpoints correspond to different projects, each with unique requirements and constraints. However, existing layout optimization methods often lack unified and efficient management of multiple projects and constraints, making it difficult to quickly and accurately meet diverse design requirements. Designers need to spend a considerable amount of time and effort adjusting layouts through trial and error, which not only reduces design efficiency but also makes it easy for oversights to occur.

[0006] In terms of process implementation, with the continuous innovation of component packaging forms such as ball grid array (BGA) and chip scale package (CSP), traditional layout methods are difficult to adapt to the new packaging specifications and pad size requirements. When processing these new components, it is impossible to accurately match electrical characteristics and process parameters, resulting in numerous problems in welding and testing, affecting product quality and production efficiency. Summary of the Invention

[0007] The object of the present invention is to provide a method and system for optimizing the layout of components in PCBA processing to solve the problems raised in the above background technology.

[0008] To achieve the above-mentioned object, the present invention provides the following technical solutions: a method for optimizing the layout of components for PCBA processing, which is used for a processing control platform, the platform being connected to a plurality of design terminals, each of which is provided with a unique project identification code;

[0009] The method comprises:

[0010] In response to receiving a layout optimization request, performing rule parsing based on layout constraint text information to obtain a component layout type, the layout optimization request including a project identification code and layout constraint text information;

[0011] If the component layout type is the first layout type identifier, matching the first layout parameter set, and combining the first layout parameter set and the efficiency factor to generate a first optimization result set;

[0012] If the component layout type is the second layout type identifier, matching the second layout parameter set, and combining the second layout parameter set, the heat dissipation factor, and the efficiency factor to generate a second optimization result set;

[0013] Among them, the first optimization result set and the second optimization result set are both used to push to the design terminal corresponding to the project identification code, the first layout type identifier corresponds to the high-density integration type, and the second layout type identifier corresponds to the high heat dissipation requirement type.

[0014] Preferably, generating the first optimization result set by combining the first layout parameter set and the efficiency factor specifically includes:

[0015] In a pre-stored component database, matching the first electrical characteristic group corresponding to each component number according to the first layout parameter set to obtain a first screening result set;

[0016] Based on the first screening result set, the efficiency factor corresponding to each component number is calculated. The efficiency factor is specifically expressed as:

[0017] Perform weighted calculations on the number of pins, trace length, and signal delay parameters corresponding to each component number, and normalize them based on a preset process difficulty coefficient.

[0018] The first screening result set is screened based on the efficiency factor and the first preset threshold to obtain a first optimized result set, specifically including: sorting the first screening result set in descending order based on the efficiency factor, and intercepting the sorted first screening result set starting from the first sequence number according to the first preset threshold to obtain the first optimized result set.

[0019] Preferably, the component layout type is obtained by performing rule parsing based on the layout constraint text information, specifically including:

[0020] Set multiple layout rule sets, each layout rule set corresponds to a layout type;

[0021] Extracting constraint parameters from the layout constraint text information to obtain a set of parameters to be matched;

[0022] According to the matching conditions between the parameter set to be matched and the multiple layout rule sets, the layout type corresponding to the layout rule set with the largest number of successful matches is determined as the component layout type;

[0023] Determining the layout type corresponding to the layout rule set with the largest number of successful matches as the component layout type includes:

[0024] The successfully matched layout rule sets are weighted and summed according to the preset priority weights, and the layout type corresponding to the layout rule set with the largest weighted result is selected as the component layout type.

[0025] Preferably, matching the first layout parameter set specifically includes:

[0026] Extracting parameters from the layout constraint text information to obtain a first candidate parameter set;

[0027] Based on a pre-built process feature library, the first candidate parameter set is matched to classify and count the electrical characteristics to obtain a first layout parameter set. The process feature library includes multiple preset process parameter sets corresponding to package specifications and pad sizes, and each process parameter has a corresponding electrical characteristic label.

[0028] Preferably, in the pre-stored component database, each component number corresponds to a component information, and each component information includes package type sub-information, thermal resistance value sub-information, electrical parameter sub-information, and mounting record sub-information, the mounting record sub-information includes a plurality of historical layout data, a corresponding thermal distribution score is obtained by analyzing each historical layout data using a pre-trained thermal analysis model, the thermal analysis model is used for quantitative evaluation of the heat conduction path of the layout data, and the first electrical characteristic group includes at least one electrical parameter label.

[0029] Preferably, the thermal analysis model is obtained by deep learning training using a plurality of sets of training data, the plurality of sets of training data include first type training data, second type training data, and third type training data, each set of data in the first type training data includes layout sample data with a high thermal efficiency identifier and a thermal score identifying the layout sample data, each set of data in the second type training data includes layout sample data with a medium thermal efficiency identifier and a thermal score identifying the layout sample data, and each set of data in the third type training data includes layout sample data with a low thermal efficiency identifier and a thermal score identifying the layout sample data.

[0030] Preferably, in the matching second layout parameter set, specifically comprising:

[0031] The parameter extraction is performed on the layout constraint text information to obtain a second candidate parameter set;

[0032] The target parameter expansion set is obtained based on the second candidate parameter set;

[0033] Based on the pre-constructed process feature library, the second candidate parameter set is matched to mark at least one key identifier, the target parameter expansion set is matched to mark at least one auxiliary identifier, and the process parameters with the key identifier or the auxiliary identifier are summarized to obtain the second layout parameter set;

[0034] The second layout parameter set is first grouped according to the key identifier and the auxiliary identifier, and then secondly grouped according to the electrical characteristic label.

[0035] Preferably, in the combination of the second layout parameter set, the heat dissipation factor, and the efficiency factor to generate the second optimization result set, specifically comprising:

[0036] In the pre-stored component database, the first electrical characteristic group corresponding to each component number is matched according to the second layout parameter set to obtain a second screening result set;

[0037] The heat dissipation factor corresponding to each component number is calculated based on the second screening result set, and the heat dissipation factor is specifically represented as:

[0038] Dynamically weight the thermal resistance, heat dissipation area, and thermal interference coefficient of adjacent components corresponding to each component number, and standardize them based on the preset heat dissipation benchmark value;

[0039] Calculate the efficiency factor corresponding to each component number based on the second screening result set;

[0040] The second screening result set is screened based on the heat dissipation factor, the efficiency factor, and the second preset threshold to obtain a second optimized result set.

[0041] Preferably, in filtering the second screening result set based on the heat dissipation factor, the efficiency factor and the second preset threshold to obtain the second optimization result set, it specifically includes: sorting the second screening result set in descending order according to the efficiency factor, and grouping and filtering the sorted second screening result set according to the key identifier and the auxiliary identifier starting from the first sequence number to obtain two groups of result sets to be optimized, and each group of result sets to be optimized is intercepted according to the second preset threshold during screening, and then the two groups of result sets to be optimized are re-sorted in descending order according to the heat dissipation factor, so that the two sorted groups of result sets to be optimized constitute the second optimization result set.

[0042] Preferably, the present invention further includes a PCBA processing component layout optimization system, the system comprising:

[0043] a request receiving module configured to, in response to receiving a layout optimization request, perform rule parsing based on layout constraint text information to obtain a component layout type, wherein the layout optimization request includes a project identification code and layout constraint text information;

[0044] A first layout processing module is configured to match a first layout parameter set if the component layout type is a first layout type identifier, and generate a first optimization result set by combining the first layout parameter set and an efficiency factor;

[0045] A second layout processing module is configured to match a second layout parameter set if the component layout type is a second layout type identifier, and generate a second optimization result set by combining the second layout parameter set, a heat dissipation factor, and an efficiency factor;

[0046] Among them, the first optimization result set and the second optimization result set are both used to push to the design terminal corresponding to the project identification code, the first layout type identifier corresponds to the high-density integration type, and the second layout type identifier corresponds to the high heat dissipation requirement type.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] To improve layout design efficiency, the system can automatically respond to layout optimization requests. By parsing the layout constraint text information, it can quickly determine the component layout type, whether it is a high-density integration type or a high-heat dissipation requirement type, and accurately match the corresponding layout parameter set. This avoids the designer from manually analyzing a large number of complex constraints and greatly shortens the initial preparation time for layout design. For example, when dealing with the layout of a large server motherboard, traditional methods require the design team to spend several days analyzing requirements and screening components. However, this invention can complete parameter matching and preliminary screening in a short time, improving efficiency several times.

[0049] This invention performs well in optimizing the layout quality of components. In high-density integration scenarios, components are screened based on the efficiency factor. The efficiency factor comprehensively considers key factors such as the number of pins, trace length, and signal delay parameters, and combines it with the normalization of the process difficulty coefficient so that the layout can minimize signal interference and improve the stability and speed of signal transmission. Taking the motherboard of 5G communication equipment as an example, the optimized layout can reduce signal delay by 30%, effectively improving the communication performance of the equipment. For scenarios with high heat dissipation requirements, components are screened based on the heat dissipation factor. The heat dissipation factor comprehensively considers factors such as thermal resistance, heat dissipation area, and thermal interference coefficient of adjacent components to ensure that components with high heat generation can be in the best heat dissipation position. For example, after the PCB layout of the graphics card of a high-performance computer is optimized, the temperature of the key chip is reduced by 15°C, which improves the stability and service life of the graphics card.

[0050] To meet the diverse needs of multiple projects, each design terminal has a unique project identifier. The system accurately pushes optimization results to the corresponding design terminal, enabling parallel processing of multiple projects without interfering with each other. The unique requirements of each project are reflected in the layout constraint text and met during the optimization process. For example, when simultaneously designing a mobile phone motherboard and a smart home control panel, the system can generate optimization results based on their respective constraints, improving a company's ability to undertake multiple projects and enhancing its market competitiveness.

[0051] From a process compatibility perspective, the pre-built process feature library contains a rich set of preset process parameters corresponding to package specifications and pad sizes. When matching layout parameters, electrical characteristics can be accurately classified and statistically analyzed, closely aligning component layout with process requirements. This effectively reduces issues that arise during soldering, testing, and other process steps. For example, in PCBA processing using new chip-scale package (CSP) components, the new process has increased the yield rate from 80% to 95%, reducing production costs and improving product quality.

[0052] For thermal management, a pre-trained thermal analysis model is used to evaluate the thermal distribution of historical layout data. This model, trained on a large amount of sample layout data with varying thermal efficiency ratings, accurately assesses the heat conduction paths within the layout data. This provides a scientific thermal management basis for component placement in layout optimizations with high heat dissipation requirements, further improving the product's heat dissipation performance and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a working principle diagram of a PCBA processing component layout optimization method according to the present invention;

[0054] Figure 2 A working principle diagram for generating a first optimization result set by combining a first layout parameter set and an efficiency factor;

[0055] Figure 3 To obtain the working principle diagram of component layout type based on layout constraint text information parsing;

[0056] Figure 4 A working principle diagram for matching a second layout parameter set;

[0057] Figure 5 A working principle diagram for generating a second optimization result set by combining a second layout parameter set, a heat dissipation factor, and an efficiency factor. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0059] See also Figure 1-Figure 5 The present invention relates to a method for optimizing the layout of components for PCBA processing, and the specific implementation steps are as follows:

[0060] The processing control platform is connected to multiple design terminals, each of which is assigned a unique project identification code, which is used for precise positioning and data exchange throughout the layout optimization process.

[0061] The layout optimization process begins when the process control platform receives a layout optimization request. This request contains a project identification code and layout constraint text. First, the process control platform performs rule parsing based on the layout constraint text. Using a specific parsing algorithm and rule matching mechanism, the platform extracts key information from the layout constraint text to determine the component layout type (this serves as the foundation for layout optimization and clarifies the subsequent optimization direction).

[0062] If the component layout type obtained through analysis is the first layout type identifier, the processing control platform will match the first layout parameter set because it corresponds to the high-density integration type. The first layout parameter set is a series of parameter combinations pre-set according to the characteristics and requirements of high-density integration, covering the packaging form, pin spacing, electrical performance parameters, etc. of the components. Afterwards, the first optimization result set is generated by combining the first layout parameter set and the efficiency factor. The efficiency factor comprehensively considers factors such as the number of pins, trace length, and signal delay parameters of the component, and is obtained through a specific calculation method to measure the comprehensive performance of the component under a high-density integration layout. The generated first optimization result set will be pushed to the design terminal corresponding to the project identification code, providing designers with a reference for component layout optimization that meets the requirements of high-density integration.

[0063] If the component layout type obtained through analysis is the second layout type identifier, that is, it corresponds to the high heat dissipation requirement type, the processing control platform will match the second layout parameter set. The second layout parameter set is set around the high heat dissipation requirement, and includes parameters such as the thermal resistance value, heat dissipation area, and thermal conductivity characteristics of the component. Subsequently, the second optimization result set is generated by combining the second layout parameter set, the heat dissipation factor, and the efficiency factor. The heat dissipation factor comprehensively considers factors such as the thermal resistance value, heat dissipation area, and thermal interference coefficient of the adjacent components of the component, and is obtained through a special calculation method to evaluate the heat dissipation performance of the component. The generated second optimization result set will also be pushed to the design terminal corresponding to the project identification code to meet the designer's needs for component layout optimization in high heat dissipation requirement scenarios. In this way, the present invention can provide targeted component layout optimization results for the design terminal according to different layout requirements, thereby improving the efficiency and quality of PCBA processing.

[0064] The present invention will be further described below in conjunction with Examples 1 to 5:

[0065] Example 1

[0066] When combining the first layout parameter set and the efficiency factor to generate the first optimized result set, the process first processes the information within the pre-existing component database. This database contains a wealth of component information, each with a corresponding number. Based on the first layout parameter set, the information corresponding to each component number is filtered, focusing on matching the first electrical feature set. This matching process compares and filters the various electrical parameters in the component information to produce the first filtered result set.

[0067] Next, the efficiency factor corresponding to each component number is calculated. This calculation involves comprehensive consideration of multiple key component attributes, including pin count, trace length, and signal delay parameters. These attributes are weighted, with weights set based on actual process requirements and experience. After the weighted calculation is completed, the efficiency factors are normalized based on a preset process difficulty coefficient, making the efficiency factors of different components comparable.

[0068] Finally, the first screening result set is filtered based on the efficiency factor and a first preset threshold to obtain a first optimized result set. Specifically, the first screening result set is sorted from highest to lowest based on the efficiency factor. After sorting, the sorted first screening result set is intercepted, starting from the first sequence number, based on the first preset threshold. The first preset threshold is determined based on extensive experiments and actual production experience. This method can achieve the first optimized result set that meets the requirements for optimizing component layout in high-density integration.

[0069] In an actual PCBA processing scenario, assume there is a PCBA processing project for a smart home appliance product, which involves the layout optimization of numerous electronic components.

[0070] When combining the first layout parameter set and the efficiency factor to generate the first set of optimized results, the processing control platform first accesses a pre-stored component database. This database is like a vast electronic component information warehouse, storing a wide variety of component data. Each component is assigned a unique number, which allows for precise location and access to relevant information.

[0071] For this PCBA project for smart home appliances, screening was performed based on the first layout parameter set. This first layout parameter set was determined based on the project's high-density integration requirements, including specific requirements for component packaging, pin spacing, and other parameters. Within the component database, the information corresponding to each component number was carefully compared and screened based on these parameters, with a focus on matching the first electrical characteristic group. For example, this project requires a large number of microchips, whose electrical characteristics, such as operating voltage and signal transmission frequency, fall within the scope of the first electrical characteristic group. During the matching process, components that do not meet the high-density integration requirements are eliminated, resulting in the first screening result set.

[0072] Next, the efficiency factor corresponding to each component number is calculated. For example, a key chip has a large number of pins, which requires more complex routing planning during layout. Trace length affects the speed and stability of signal transmission. Signal delay directly impacts the performance of the entire circuit system. These attributes are comprehensively considered when calculating the efficiency factor. Assume that the weight of pin number is set to 0.4, trace length is weighted to 0.3, and signal delay is weighted to 0.3 (these weights are determined based on the circuit design requirements and actual production experience of this smart home appliance). A preliminary value is obtained by weighting these attributes. Then, normalization is performed based on a preset process difficulty coefficient. The preset process difficulty coefficient is determined based on the production process level and capabilities of the PCBA fabrication factory, for example, a specific value. After normalization, the efficiency factors of different components are standardized, facilitating comparison and analysis.

[0073] Finally, the first screening result set is screened based on the efficiency factor and the first preset threshold to obtain the first optimized result set. Assume that the first preset threshold is determined to be 0.6 based on multiple experiments and actual production tests. First, the first screening result set is sorted in descending order based on the efficiency factor. After the sorting is completed, the sorted first screening result set is intercepted starting from the first sequence number. For example, the efficiency factors of the components A and B at the front are all greater than 0.6 after calculation, while the efficiency factors of some components at the back are less than 0.6, then these components with efficiency factors greater than or equal to 0.6 are intercepted to form the first optimized result set. The first optimized result set obtained in this way can meet the optimization requirements of the component layout of the PCBA of the smart home appliance product under the high-density integration type, and provide a more reasonable and efficient component layout solution for subsequent production and processing.

[0074] Example 2

[0075] In the process of parsing the layout constraint text information to obtain the component layout type, it is necessary to first set up multiple layout rule sets. These layout rule sets are pre-defined based on different layout types and actual production requirements. Each layout rule set corresponds to a specific layout type.

[0076] The layout constraint text information is then used to extract constraint parameters. Using a specialized text extraction algorithm, various parameters are accurately extracted from the layout constraint text information. These parameters form a set of parameters to be matched. This set of parameters is then matched against multiple layout rule sets. During the matching process, the number of successful matches for each layout rule set is counted by comparing the parameters in the set with the rules in each layout rule set.

[0077] In determining the component layout type, the layout type corresponding to the layout rule set with the largest number of successful matches is generally determined as the component layout type. A more accurate way is to weight and sum the layout rule sets that match successfully according to preset priority weights. The preset priority weights are set considering the importance difference of different rules in actual layout. By weighting and summing, the layout rule set with the largest weighted result is selected as the component layout type, so as to more accurately determine the suitable layout type.

[0078] Suppose a PCBA processing project of a high-performance server motherboard is being carried out, in which the layout type of components needs to be determined according to the layout constraint text information to achieve a more optimal layout planning.

[0079] The technical team has pre-set multiple layout rule sets. According to the characteristics of the high-performance server motherboard, rule sets suitable for different layout requirements are developed. For example, for the demand of high-speed signal transmission, a set of layout rules emphasizing reducing signal interference and ensuring signal integrity is developed; for the demand of high-density integration, a set of layout rules focusing on improving space utilization and reasonably arranging the distance between components is developed; and for the demand of heat dissipation, a special set of layout rules is developed. Each layout rule set specifies a series of parameters and conditions in detail, corresponding to a specific layout type.

[0080] In this high-performance server motherboard project, the layout constraint text information contains numerous requirements for the design of the motherboard, such as layout requirements for key components such as processors, memory modules, high-speed communication interfaces, and regulations for overall electrical performance and space utilization. Technical personnel use a special text extraction algorithm to accurately extract various parameters from these complex layout constraint text information. For example, the size, pin count, signal transmission rate requirements of key components, and overall size and available space of the motherboard are extracted, which together form the set of parameters to be matched.

[0081] Then, the set of parameters to be matched is matched with multiple layout rule sets. Taking the high-speed signal transmission layout rule set as an example, the rules stipulate that the length of high-speed signal traces cannot exceed a certain value, and the spacing between adjacent signal traces must meet certain requirements to reduce crosstalk, etc. The signal transmission rate requirements, pin count, and other parameters in the set of parameters to be matched are compared with these rules. If a parameter in the set of parameters to be matched matches a rule in the layout rule set, it is recorded as a successful match. In this way, the number of successful matches for each layout rule set is counted.

[0082] In determining the component layout type, the layout type corresponding to the layout rule set with the largest number of matching successes is usually determined as the component layout type. However, in a high-performance server mainboard project with extremely high performance requirements, in order to more accurately determine the layout type, the matching successful layout rule set is also weighted and summed according to the preset priority weight. For example, for the layout rule set of high-speed signal transmission, since it is crucial to the performance of the server mainboard, the preset priority weight is higher, assuming 0.6; for the layout rule set of high-density integration, the priority weight is assumed to be 0.3; and the priority weight of the layout rule set related to heat dissipation is assumed to be 0.1 (these weights are determined according to the functional characteristics and actual application requirements of the server mainboard). Through weighted summation, the layout type corresponding to the layout rule set with the largest weighted result is selected as the component layout type. If the weighted result of the high-speed signal transmission layout rule set is the largest after calculation, it is determined that the component layout type of the high-performance server mainboard is more inclined to the layout type that meets the high-speed signal transmission requirement, thereby providing an accurate direction for subsequent component layout optimization.

[0083] Embodiment 3

[0084] When matching the first layout parameter set, parameter extraction is performed on the layout constraint text information to obtain a first candidate parameter set. This step obtains various parameters related to component layout from the layout constraint text information through specific text parameter extraction technology.

[0085] Then, the first candidate parameter set is matched based on the pre-constructed process feature library. The process feature library contains multiple preset process parameter sets corresponding to packaging specifications and pad sizes, and each process parameter has a corresponding electrical characteristic label. In the matching process, the parameters in the first candidate parameter set are compared with the preset process parameter sets in the process feature library, and the electrical characteristics are classified and counted. In this way, parameters that meet the requirements of high-density integration are screened out, and then the first layout parameter set is obtained, providing accurate parameter support for subsequent generation of optimized layout results suitable for high-density integration type. Assume that a new type of smart phone mainboard is being processed. In the design of this mainboard, in order to realize a more compact structure and higher performance, it is necessary to accurately match the first layout parameter set.

[0086] The processing control platform first extracts parameters from the layout constraint text. In the design documentation for new smartphone motherboards, this information includes key details, such as performance requirements and size restrictions for various chips on the motherboard (such as processors and memory chips), as well as electrical performance requirements for connecting circuits. Using specialized text parameter extraction technology, this information is filtered to identify parameters closely related to component layout, such as chip package size, pin count and arrangement, operating frequency range, and allowable signal transmission delay. These parameters together form the first set of candidate parameters.

[0087] The first candidate parameter set is matched using a pre-built process feature library. The process feature library is like a huge process parameter "dictionary", which stores a large number of preset process parameter sets corresponding to package specifications and pad sizes, and each process parameter has a corresponding electrical characteristic label. In this smartphone motherboard project, taking the processor chip as an example, its package size is of specific specifications, with a large number of pins and a specific arrangement. The process feature library records the preset process parameter sets that match the chip with this package specification and number of pins. These parameter sets contain information such as the pad size, trace width and spacing suitable for the chip. At the same time, each parameter is marked with the corresponding electrical characteristic label, such as signal transmission speed, anti-interference ability, etc.

[0088] The parameters in the first candidate parameter set are compared one by one with the preset process parameter set in the process feature library. For the parameters of the processor chip, the preset process parameter set with the highest degree of match is found. At the same time, suitable parameter sets corresponding to other related components are also found. During the comparison process, electrical characteristics are classified and counted. For example, parameters related to signal transmission speed are classified into one category, and parameters related to anti-interference capability are classified into another category. Through such detailed comparison and classification statistics, parameters that meet the requirements of high-density integration are screened out. These parameters cover various key information of different components and together constitute the first layout parameter set.

[0089] Once the initial set of layout parameters is determined, it provides accurate data support for generating optimized layout results suitable for high-density integration of smartphone motherboards. During the subsequent layout optimization process, engineers can use these parameters to rationally arrange the positions of processor chips, memory chips, and other components, plan connection routes, and ensure high-performance and high-reliability motherboard operation within a limited space, meeting the stringent motherboard layout requirements of new smartphones.

[0090] Example 4

[0091] When matching the second layout parameter set, firstly, the layout constraint text information is subjected to parameter extraction to obtain a second candidate parameter set. Also, professional text parameter extraction methods are used to obtain relevant parameters from the layout constraint text information.

[0092] Next, an extended parameter operation is performed based on the second candidate parameter set to obtain the target parameter extension set. This extension process supplements and expands the second candidate parameter set based on the characteristics of high heat dissipation requirements to obtain more comprehensive parameter information. The second candidate parameter set is then matched against the pre-built process feature library, marking at least one key identifier. Simultaneously, the target parameter extension set is matched and marked with at least one auxiliary identifier.

[0093] The process parameters with key identifiers or auxiliary identifiers are summarized to obtain a second layout parameter set. The second layout parameter set is grouped for the first time according to the key identifier and auxiliary identifier, and then grouped for the second time according to the electrical characteristic label. Through this grouping method, the parameters can be organized and managed more clearly, and preparations can be made for the subsequent generation of the second optimization result set by combining the heat dissipation factor and the efficiency factor. Assume that an electronic equipment manufacturer is developing a PCBA for a high-performance gaming notebook. The PCBA has extremely high heat dissipation requirements. In this embodiment, the process of matching the second layout parameter set is as follows:

[0094] The company's design team must first extract parameters from the layout constraint text information. In the design document of this gaming laptop's PCBA, the layout constraint text information contains a large number of requirements related to component layout. For example, the heat dissipation specification requirements for high-performance graphics cards, central processing units (CPUs), such as the graphics card's thermal design power consumption, ideal operating temperature range, and the CPU's heat dissipation method (air cooling or liquid cooling); as well as the dimensions and electrical performance parameters of each component. Using professional text parameter extraction tools, key parameters are extracted from this complex text information, such as the thermal resistance value, external dimensions, number of pins, and electrical connection requirements of the heat-generating components. These parameters constitute the second set of candidate parameters.

[0095] An extended parameter operation is performed based on the second candidate parameter set to obtain an extended target parameter set. Since the high-performance operation of the gaming laptop will generate a large amount of heat, relying solely on the original second candidate parameters cannot fully meet the design of a layout with high heat dissipation requirements. For example, considering the impact of air flow around heat-generating components on heat dissipation, some parameters related to air flow will be added, such as the position and size of the heat dissipation holes, the power and speed of the fan, etc.; the impact of heat conduction between adjacent components will also be taken into account, and parameters such as the thermal conductivity coefficient between adjacent components will be added. Through such an extension, these supplementary parameters are merged with the original second candidate parameters to form an extended target parameter set.

[0096] The second candidate parameter set and the target parameter expansion set are matched respectively by using a pre-constructed process feature library. The process feature library stores a wealth of pre-set process parameter sets corresponding to packaging specifications and pad sizes, and each process parameter has a corresponding electrical characteristic label and a heat dissipation characteristic label. Taking a high-performance graphics card as an example, when the second candidate parameter set is matched, the process feature library will mark key identifiers closely related to heat dissipation and electrical connection of the graphics card according to parameters such as thermal resistance value and pin number of the graphics card. For example, for a graphics card that requires a special heat dissipation structure, the key identifier of “high-performance heat dissipation requirement” is marked; for a complex electrical connection with high requirements for signal transmission, the corresponding electrical key identifier is marked.

[0097] The target parameter expansion set is matched. For example, for the added heat dissipation hole position and size parameters, the process feature library will mark auxiliary identifiers such as “auxiliary heat dissipation optimization” according to different heat dissipation effects and influences on electrical performance; for fan power and speed parameters, auxiliary identifiers related to heat dissipation efficiency are marked.

[0098] The process parameters with key identifiers or auxiliary identifiers are summarized to obtain a second layout parameter set. The second layout parameter set is first grouped according to key identifiers and auxiliary identifiers. For example, parameters with the “high-performance heat dissipation requirement” key identifier are grouped together, and parameters with the “auxiliary heat dissipation optimization” auxiliary identifier are grouped together. Then, the second grouping is performed according to the electrical characteristic label. For example, parameters related to signal transmission are classified into one category, and parameters related to power supply are classified into another category. Through such detailed grouping, the second layout parameter set is more clear and orderly, providing an accurate and ordered parameter basis for generating a second optimization result set by combining heat dissipation factors and efficiency factors, thereby better meeting the layout optimization requirements of the high-heat-dissipation gaming laptop PCBA.

[0099] Embodiment 5

[0100] When generating the second optimization result set by combining the second layout parameter set, the heat dissipation factor, and the efficiency factor, first, in the pre-stored component database, the first electrical characteristic group corresponding to each component number is matched according to the second layout parameter set, thereby obtaining a second screening result set.

[0101] Next, the heat dissipation factor corresponding to each component number is calculated. This calculation process considers factors such as thermal resistance value, heat dissipation area, and adjacent component thermal interference coefficient of the component. Through dynamic weighting of these factors, the dynamic weighting weight is adjusted according to the actual situation to reflect the importance changes of different factors in the heat dissipation process. Then, based on the pre-set heat dissipation reference value, standardization processing is performed, so that the heat dissipation factors of different components are comparable.

[0102] Based on the second screening result set, the efficiency factor corresponding to each component number is calculated using a similar method used to generate the efficiency factor when generating the first optimization result set, taking into account factors such as the number of pins, trace length, and signal delay parameters. Finally, the second screening result set is filtered based on the heat dissipation factor, efficiency factor, and second preset threshold to obtain the second optimization result set.

[0103] The specific screening process is to sort the second screening result set from high to low according to the efficiency factor. Starting from the first sequence number, the sorted second screening result set is grouped and screened by key identifiers and auxiliary identifiers to obtain two sets of results to be optimized. Each set of results to be optimized is intercepted according to the second preset threshold during screening. Afterwards, the two sets of results to be optimized are re-sorted from high to low according to the heat dissipation factor. Finally, the two sorted sets of results to be optimized form the second optimized result set, which meets the requirements for optimizing component layout under high heat dissipation requirements.

[0104] Assume that a technology company is developing a PCBA for a 5G base station. This PCBA has strict requirements for heat dissipation and efficiency. The following describes the implementation of this embodiment in detail using this project as an example.

[0105] When combining the second layout parameter set, heat dissipation factor, and efficiency factor to generate the second optimization result set, the pre-existing component database is first utilized. This database stores information on various components required for 5G base station PCBAs, with each component having a unique number. Based on the previously determined second layout parameter set, the first electrical characteristic group corresponding to each component number is matched to obtain the second screening result set. For example, for key components such as power amplifiers and filters in 5G base stations, the electrical characteristic labels and heat dissipation-related parameters in the second layout parameter set are used to screen out component combinations that meet high heat dissipation and electrical performance requirements, forming the second screening result set.

[0106] Next, calculate the heat dissipation factor corresponding to each component number. The heat dissipation factor calculation formula is: Where S represents the heat dissipation factor; n represents the number of factors that affect heat dissipation. In this project, n = 3, namely the thermal resistance, heat dissipation area, and thermal interference coefficient of adjacent components; w i represents the weight of the i-th factor affecting heat dissipation, for example, the weight w1 of thermal resistance is 0.4, the weight w2 of heat dissipation area is 0.3, and the weight w3 of thermal interference coefficient of adjacent components is 0.3. These weights are determined through multiple experiments and theoretical analysis based on the importance of each factor on heat dissipation in 5G base stations; iIndicates the actual parameter value of the i-th factor affecting heat dissipation. For example, the thermal resistance p1 of a power amplifier is x (unit: °C / W), and the heat dissipation area p2 is y (unit: mm 2 ), the thermal interference coefficient of adjacent components p3 is z (dimensionless); T represents the preset heat dissipation benchmark value, which is determined based on the overall heat dissipation design requirements and industry standards of 5G base stations and is assumed to be T = m (the specific value is determined based on actual conditions). This formula is used to calculate the heat dissipation factor of each component, dynamically weighting the thermal resistance value, heat dissipation area, and thermal interference coefficient of adjacent components corresponding to each component number, and then normalizing them based on the preset heat dissipation benchmark value.

[0107] At the same time, the efficiency factor corresponding to each component number is calculated based on the second screening result set. Similar to the calculation of the first optimization result set, factors such as pin count, trace length, and signal delay parameters are comprehensively considered. Assuming the weight of pin count is a, the weight of trace length is b, and the weight of signal delay parameter is c, the efficiency factor is also obtained through weighted calculation and normalization.

[0108] Finally, the second screening result set is filtered based on the heat dissipation factor, efficiency factor, and a second preset threshold to obtain a second optimized result set. Assume that the second preset threshold is k, determined based on multiple simulations and actual tests. First, the second screening result set is sorted from highest to lowest according to the efficiency factor. Starting from the highest sequence number, the sorted second screening result set is grouped and filtered by key identifier and auxiliary identifier, resulting in two sets of results to be optimized. For example, components with the key identifier "high-power heat dissipation key components" are grouped together, while components with the auxiliary identifier "auxiliary heat dissipation structure-related components" are grouped together. Each set of results to be optimized is truncated based on the second preset threshold during screening, eliminating components with an efficiency factor below k. The two sets of results to be optimized are then re-sorted from highest to lowest according to the heat dissipation factor, ultimately forming the second optimized result set. This optimized result set meets the component layout optimization requirements for 5G base station PCBAs with high heat dissipation requirements, ensuring efficient heat dissipation and stable operation during 5G base station operation.

[0109] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0110] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A PCBA processing component layout optimization method, characterized in that: Used for processing control platform, the platform is connected to multiple design terminals, each design terminal has a unique project identification code; The method comprises: In response to receiving a layout optimization request, performing rule parsing based on layout constraint text information to obtain a component layout type, the layout optimization request including a project identification code and layout constraint text information; If the component layout type is the first layout type identifier, matching the first layout parameter set, and combining the first layout parameter set and the efficiency factor to generate a first optimization result set; If the component layout type is the second layout type identifier, matching the second layout parameter set, and combining the second layout parameter set, the heat dissipation factor, and the efficiency factor to generate a second optimization result set; The first optimization result set and the second optimization result set are both used to be pushed to a design terminal corresponding to a project identification code, the first layout type identifier corresponds to a high-density integration type, and the second layout type identifier corresponds to a high heat dissipation requirement type; Perform weighted calculations on the number of pins, trace length, and signal delay parameters corresponding to each component number, and normalize them based on a preset process difficulty coefficient. In the pre-stored component database, each component number corresponds to a component information. Each component information includes package type sub-information, thermal resistance value sub-information, electrical parameter sub-information, and installation record sub-information. The installation record sub-information includes multiple historical layout data. A pre-trained thermal analysis model is used to analyze each historical layout data to obtain a corresponding thermal distribution score. The thermal analysis model is used to quantitatively evaluate the heat conduction path of the layout data.

2. The PCBA processing component layout optimization method according to claim 1, characterized in that: Combining the first layout parameter set and the efficiency factor to generate the first optimization result set specifically includes: In a pre-stored component database, matching the first electrical characteristic group corresponding to each component number according to the first layout parameter set to obtain a first screening result set; Based on the first screening result set, the efficiency factor corresponding to each component number is calculated. The efficiency factor is specifically expressed as: Perform weighted calculations on the number of pins, trace length, and signal delay parameters corresponding to each component number, and normalize them based on a preset process difficulty coefficient. The first screening result set is screened based on the efficiency factor and the first preset threshold to obtain a first optimized result set, specifically including: sorting the first screening result set in descending order based on the efficiency factor, and intercepting the sorted first screening result set starting from the first sequence number according to the first preset threshold to obtain the first optimized result set.

3. The PCBA processing component layout optimization method according to claim 2, characterized in that: The component layout types obtained by rule parsing based on layout constraint text information include: Set multiple layout rule sets, each layout rule set corresponds to a layout type; Extracting constraint parameters from the layout constraint text information to obtain a set of parameters to be matched; According to the matching conditions between the parameter set to be matched and the multiple layout rule sets, the layout type corresponding to the layout rule set with the largest number of successful matches is determined as the component layout type; Determining the layout type corresponding to the layout rule set with the largest number of successful matches as the component layout type includes: The successfully matched layout rule sets are weighted and summed according to the preset priority weights, and the layout type corresponding to the layout rule set with the largest weighted result is selected as the component layout type.

4. The PCBA processing component layout optimization method according to claim 3, characterized in that: Matching the first layout parameter set specifically includes: Extracting parameters from the layout constraint text information to obtain a first candidate parameter set; Based on a pre-built process feature library, the first candidate parameter set is matched to classify and count the electrical characteristics to obtain a first layout parameter set. The process feature library includes multiple preset process parameter sets corresponding to package specifications and pad sizes, and each process parameter has a corresponding electrical characteristic label.

5. The PCBA processing component layout optimization method according to claim 4, characterized in that: In the pre-stored component database, each component number corresponds to a component information. Each component information includes package type sub-information, thermal resistance value sub-information, electrical parameter sub-information, and installation record sub-information. The installation record sub-information includes multiple historical layout data. A pre-trained thermal analysis model is used to analyze each historical layout data to obtain a corresponding thermal distribution score. The thermal analysis model is used to quantitatively evaluate the heat conduction path of the layout data. The first electrical feature group includes at least one electrical parameter label.

6. The PCBA processing component layout optimization method according to claim 5, characterized in that: The thermal analysis model is obtained through deep learning training using multiple sets of training data, the multiple sets of training data include a first category of training data, a second category of training data, and a third category of training data. Each set of data in the first category of training data includes: layout sample data with a high thermal efficiency identifier and a thermal score identifying the layout sample data. Each set of data in the second category of training data includes: layout sample data with a medium thermal efficiency identifier and a thermal score identifying the layout sample data. Each set of data in the third category of training data includes: layout sample data with a low thermal efficiency identifier and a thermal score identifying the layout sample data.

7. The PCBA processing component layout optimization method according to claim 6, characterized in that: Matching the second layout parameter set specifically includes: Performing parameter extraction on the layout constraint text information to obtain a second candidate parameter set; Extending parameters based on the second candidate parameter set to obtain a target parameter extension set; Based on a pre-built process feature library, matching the second candidate parameter set to mark at least one key identifier, matching the target parameter extension set to mark at least one auxiliary identifier, and summarizing the process parameters with the key identifier or the auxiliary identifier to obtain a second layout parameter set; The second layout parameter set is first grouped according to the key identifier and the auxiliary identifier, and then secondly grouped according to the electrical characteristic label.

8. The PCBA processing component layout optimization method according to claim 7, characterized in that: The second optimization result set is generated by combining the second layout parameter set, the heat dissipation factor, and the efficiency factor, specifically including: In a pre-stored component database, matching the first electrical characteristic group corresponding to each component number according to the second layout parameter set to obtain a second screening result set; Based on the second screening result set, the heat dissipation factor corresponding to each component number is calculated. The heat dissipation factor is specifically expressed as: Dynamically weight the thermal resistance, heat dissipation area, and thermal interference coefficient of adjacent components corresponding to each component number, and standardize them based on the preset heat dissipation benchmark value; Calculate the efficiency factor corresponding to each component number based on the second screening result set; The second screening result set is screened based on the heat dissipation factor, the efficiency factor, and the second preset threshold to obtain a second optimized result set.

9. The PCBA processing component layout optimization method according to claim 8, characterized in that: In filtering the second screening result set based on the heat dissipation factor, the efficiency factor and the second preset threshold to obtain the second optimization result set, it specifically includes: sorting the second screening result set in descending order according to the efficiency factor, and grouping and filtering the sorted second screening result set according to the key identifier and the auxiliary identifier starting from the first sequence number to obtain two groups of result sets to be optimized. Each group of result sets to be optimized is intercepted according to the second preset threshold during screening, and then the two groups of result sets to be optimized are re-sorted in descending order according to the heat dissipation factor, so that the two sorted groups of result sets to be optimized constitute the second optimization result set.

10. A PCBA processing component layout optimization system, characterized in that: include: a request receiving module configured to, in response to receiving a layout optimization request, perform rule parsing based on layout constraint text information to obtain a component layout type, wherein the layout optimization request includes a project identification code and layout constraint text information; A first layout processing module is configured to match a first layout parameter set if the component layout type is a first layout type identifier, and generate a first optimization result set by combining the first layout parameter set and an efficiency factor; A second layout processing module is configured to match a second layout parameter set if the component layout type is a second layout type identifier, and generate a second optimization result set by combining the second layout parameter set, a heat dissipation factor, and an efficiency factor; The first optimization result set and the second optimization result set are both used to be pushed to a design terminal corresponding to a project identification code, the first layout type identifier corresponds to a high-density integration type, and the second layout type identifier corresponds to a high heat dissipation requirement type; Perform weighted calculations on the number of pins, trace length, and signal delay parameters corresponding to each component number, and normalize them based on a preset process difficulty coefficient. In the pre-stored component database, each component number corresponds to a component information. Each component information includes package type sub-information, thermal resistance value sub-information, electrical parameter sub-information, and installation record sub-information. The installation record sub-information includes multiple historical layout data. A pre-trained thermal analysis model is used to analyze each historical layout data to obtain a corresponding thermal distribution score. The thermal analysis model is used to quantitatively evaluate the heat conduction path of the layout data.

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