High-speed signal wiring structure and method for chip

Abstract

The present application provides a high-speed signal wiring structure and method for a chip, relating to the field of chip design. The structure includes: arranging a first flat plate capacitor on either side of a target dielectric layer in a target internal routing layer where a first high-speed signal line and a second high-speed signal line are located, so as to form a target capacitance value that meets the requirements; wherein the first flat plate capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate, thereby realizing an AC capacitive coupling design of high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line through the first flat plate capacitor, avoiding the placement of layer-changing vias, surface routing, and capacitors, increasing the impedance consistency of the high-speed signal link, improving the utilization rate of the PCB layout space, and providing effective protection for high-speed and high-density PCB design.

Description

Technical Field

[0001] The present application relates to the field of chip design, and in particular to a high-speed signal wiring structure and method for a chip. Background Art

[0002] High-speed signals refer to signals transmitted at extremely high speeds in electronic communications, data transmission, and digital systems. When routing signal lines that carry high-speed signals, internal routing is typically used to avoid surface greening and production processing uncertainties. High-speed signal transmission often takes a point-to-point approach. Depending on the chip's characteristics, high-speed signal transmission can be divided into two methods: DC coupling and AC coupling. AC coupling requires a capacitor of a certain value to be placed between the two interconnected points to ensure proper signal transmission.

[0003] In the prior art, if high-speed signals interconnecting chips are coupled using AC capacitors, the signals need to be routed from the inner layer of the stacked structure to the surface layer through layer-changing vias for capacitor placement, and then returned to the inner layer through layer-changing vias.

[0004] It can be seen that the existing AC capacitor coupling method has a complex structure. Therefore, designers mainly focus more on optimizing layer-changing vias and coupling capacitors. However, the optimized AC capacitor coupling method still has problems such as impedance discontinuity and large space occupation. Summary of the Invention

[0005] The purpose of this application is to address the deficiencies in the above-mentioned prior art and provide a high-speed signal wiring structure and method for a chip. The layout of the first flat capacitor can avoid the placement of layer-changing vias, surface routing and capacitors, increase the impedance consistency of the high-speed signal link, improve the utilization rate of the PCB layout space, and provide effective protection for high-speed and high-density PCB design.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, the present invention provides a high-speed signal wiring structure for a chip, comprising:

[0008] Arrange a first flat plate capacitor on either side of a target dielectric layer in a target internal wiring layer where the first high-speed signal line and the second high-speed signal line are located, so as to form a target capacitance value that meets the requirements;

[0009] The first flat plate capacitor includes a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

[0010] In an optional embodiment, the first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate, the first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line.

[0011] In an optional embodiment, a first distance between the first sub-metal conductor plate and the first signal lines on two adjacent sides meets a first preset distance requirement;

[0012] A second distance between the second sub-metal conductor plate and the second signal lines on two adjacent sides meets a first preset distance requirement.

[0013] In an optional embodiment, the second projection area of ​​the second metal conductor plate includes: the first sub-projection area of ​​the first sub-metal conductor plate and the second sub-projection area of ​​the second sub-metal conductor plate, and the area of ​​the second projection area is greater than the sum of the areas of the first sub-projection area and the second sub-projection area.

[0014] In an optional embodiment, the second metal conductor plate is obtained by etching a second metal conductor layer disposed on either side of a target dielectric layer in a target internal wiring layer.

[0015] In an optional embodiment, a third distance between the second metal conductor plate and the third signal lines on two adjacent sides meets a third preset distance requirement.

[0016] In an optional embodiment, the thickness and dielectric constant of the first dielectric layer are determined according to the target capacitance value.

[0017] In an optional embodiment, the target internal routing layer further includes: a third high-speed signal line and a fourth high-speed signal line, the third high-speed signal line is adjacent to the first high-speed signal line, and the fourth high-speed signal line is adjacent to the second high-speed signal line;

[0018] Arrange a second flat plate capacitor on either side of a target dielectric layer in a target internal wiring layer where the third high-speed signal line and the fourth high-speed signal line are located;

[0019] The second flat plate capacitor is staggered with the first flat plate capacitor, and comprises a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

[0020] In an optional embodiment, the first flat plate capacitor is arranged on the upper side of the target dielectric layer, and the second flat plate capacitor is arranged on the lower side of the target dielectric layer; or, the first flat plate capacitor is arranged on the lower side of the target dielectric layer, and the second flat plate capacitor is arranged on the upper side of the target dielectric layer.

[0021] In an optional embodiment, the first sub-metal conductor plate and the second sub-metal conductor plate have the same size.

[0022] In a second aspect, the present invention provides a high-speed signal routing method for a chip, the method comprising:

[0023] Determining, based on an initial stacking structure corresponding to the target circuit, a target internal routing layer where a first high-speed signal line and a second high-speed signal line of a first flat-plate capacitor are to be arranged in the target circuit;

[0024] Arranging a first flat plate capacitor on either side of a target dielectric layer in a target internal routing layer where the first high-speed signal line and the second high-speed signal line are located, so as to form a target capacitance value that meets requirements;

[0025] The first flat plate capacitor includes a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

[0026] The beneficial effects of this application are:

[0027] In the high-speed signal wiring structure and method for a chip provided in an embodiment of the present application, the high-speed signal wiring structure includes: arranging a first flat plate capacitor on either side of a target dielectric layer in a target internal routing layer where a first high-speed signal line and a second high-speed signal line are located to form a target capacitance value that meets requirements; wherein the first flat plate capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate, thereby implementing an AC capacitive coupling design for high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line through the first flat plate capacitor, avoiding the placement of layer-changing vias, surface routing, and capacitors, increasing the impedance consistency of the high-speed signal link, improving the utilization of PCB layout space, and providing effective guarantees for high-speed and high-density PCB design. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic diagram of an existing AC capacitive coupling provided in an embodiment of the present application;

[0030] Figure 2 This is one of the schematic diagrams of the high-speed signal wiring structure of a chip provided in an embodiment of the present application;

[0031] Figure 3 This is a second schematic diagram of a high-speed signal wiring structure of a chip provided in an embodiment of the present application;

[0032] Figure 4 The third schematic diagram of a high-speed signal wiring structure of a chip provided in an embodiment of the present application;

[0033] Figure 5 A fourth schematic diagram of a high-speed signal wiring structure of a chip provided in an embodiment of the present application;

[0034] Figure 6 A fifth schematic diagram of a high-speed signal wiring structure of a chip provided in an embodiment of the present application;

[0035] Figure 7 A high-speed signal routing method for a chip is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0039] High-speed signal routing typically uses internal layer routing to avoid surface green oil and production processing uncertainties, and high-speed signal transmission is often point-to-point. Based on the requirements of chip characteristics, high-speed signal transmission can be divided into two methods: DC coupling and AC coupling. DC coupling uses a direct connection between signals, without the need for other devices between the two interconnected points. AC coupling, on the other hand, requires the placement of a capacitor of a certain capacitance (for example, 220nf) between the two interconnected points to ensure normal signal transmission. Many high-speed signal designs require AC coupling capacitors. For example, PCIe signals require the placement of a 220nf capacitor at the transmitting end. If AC capacitor coupling is used for high-speed signals connecting chips, the signal routing must be carried out from the internal layers of the stacked structure through layer-change vias to the surface layer for capacitor placement, and then returned to the internal layers through layer-change vias.

[0040] It can be seen that in the related technology, if the high-speed signals interconnecting the chips adopt the AC capacitor coupling method, then when routing the signals, it is necessary to lead the signals from the internal layer of the stacked structure to the surface layer through the layer-changing via for capacitor placement, and then return to the internal layer through the layer-changing via.

[0041] Figure 1 This is a schematic diagram of an existing AC capacitive coupling provided in an embodiment of the present application. Figure 1 As shown, in the prior art, if it is necessary to establish an AC coupling capacitor C0 between the first inner layer routing L_1 and the second inner layer routing L_2, it is necessary to set a first layer-changing via Q1 at the position of the first inner layer routing L_1, and set a first surface routing S_1 at the other end of the first layer-changing via Q1; set a second layer-changing via Q2 at the position of the second inner layer routing L_2, and set a second surface routing S_2 at the other end of the second layer-changing via Q2, and then set an AC coupling capacitor C0 between the first surface routing S_1 and the second surface routing S_2.

[0042] It can be seen that the existing AC capacitor coupling method has the following disadvantages: First, the transmission method is complex, and the signal needs to be brought out to the surface layer through two levels of vias, which increases the number of vias and leads to more discontinuous points in signal transmission; second, the introduction of layer-change vias will interfere with the utilization of other signal layers, and the signal wiring on other signal layers must bypass the layer-change via area; third, the layer-change vias require a larger PCB space to avoid interference from the vertical area of ​​the vias; fourth, the placement of capacitors on the surface increases the PCB layout space, wastes PCB board space, and cannot achieve high-density wiring.

[0043] To address the increased impedance discontinuity and design risks associated with existing AC capacitor coupling, PCB designers have focused on optimizing layer-switching vias and coupling capacitors. However, even after optimization, the AC capacitor coupling method still suffers from impedance discontinuity and large space requirements.

[0044] In view of this, an embodiment of the present application provides a high-speed signal wiring structure of a chip, in which a first flat plate capacitor is arranged on the target internal layer where the first high-speed signal line and the second high-speed signal line are located. Through the first flat plate capacitor, an AC capacitor coupling design of the high-speed signal transmitted by the first high-speed signal line and the second high-speed signal line can be realized, thereby avoiding the placement of layer-changing vias, surface routing and capacitors, increasing the impedance consistency of the high-speed signal link, improving the utilization rate of the PCB layout space, and providing effective protection for high-speed and high-density PCB design.

[0045] Figure 2 This is one of the schematic diagrams of the high-speed signal wiring structure of a chip provided in an embodiment of the present application. Figure 3 This is a second schematic diagram of a high-speed signal wiring structure of a chip provided in an embodiment of the present application. Figure 2 and Figure 3 As shown, the high-speed signal wiring structure may include:

[0046] A first flat plate capacitor is arranged on either side of a target dielectric layer in a target internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located to form a target capacitance value that meets the requirements; wherein the first flat plate capacitor includes: a first metal conductor plate A, a second metal conductor plate B, and a first dielectric layer D located between the first metal conductor plate A and the second metal conductor plate B.

[0047] The first high-speed signal line L1 and the second high-speed signal line L2 may be high-speed signal lines in a target circuit, and the target circuit may be a partial circuit in an integrated circuit corresponding to the chip.

[0048] Optionally, the first high-speed signal line L1 and the second high-speed signal line L2 may be signal lines requiring AC capacitor coupling design, such as high-speed serial signals, high-speed parallel signals, high-speed network signals, and differential signal lines in the target circuit. Of course, it should be noted that if there are two signal lines requiring AC capacitor coupling design, for example, a first differential signal line and a second differential signal line, a corresponding first parallel capacitor may be provided for each differential signal line.

[0049] The target internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located is also the internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located in the stacked structure corresponding to the target circuit. In order to better understand this application, the following description is combined with part of the initial stacked structure of the chip.

[0050] Table 1 is a schematic diagram of a portion of the stacked structure of a chip provided in an embodiment of the present application before adjustment. Table 2 is a schematic diagram of a portion of the stacked structure of a chip provided in an embodiment of the present application after adjustment. Referring to Table 1, the stacked structure comprises five layers, from top to bottom: TOP (surface layer), GND02 (inner ground plane), ART03 (signal layer), GND04, and ART05. It should be noted that the stacked structure is not limited to this; more PCB layers can be arranged depending on the complex functions required.

[0051] The TOP layer has a base copper thickness of 0.3 oz (approximately 10 μm), which can ultimately reach 1 oz through electroplating (e.g., copper plating). A 2.632-mil thick PP (model 1080) prepreg material is placed between the TOP layer and the GND02 layer. For the ART03 layer, a 4.688-mil thick PP dielectric is placed above the ART03 layer. The ART03 layer includes a 1 oz copper foil and a 3-mil thick target dielectric layer, CoreA, beneath it. For descriptions of the other layers, refer to that section and are omitted here. PP (1035*2) represents two 1035 prepreg materials.

[0052] Optionally, the target internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located may be the ART03 layer shown in Table 1, but is not limited thereto.

[0053] Of course, it should be noted that the present application does not limit the specific arrangement of the initial stacked structure corresponding to the chip, and it can be flexibly set according to the actual application scenario.

[0054] Table 1

[0055]

[0056] Table 2

[0057]

[0058] Based on the above, it should be noted that the specific layout of the first planar capacitor can be arranged on the upper side of the target dielectric layer in the target internal routing layer, or it can be arranged on the lower side of the target dielectric layer in the target internal routing layer. This is not limited here and can be flexibly arranged according to the actual application scenario. Among them, the target dielectric layer in the target internal routing layer, that is, the existing core material in the target internal routing layer, as shown in Table 2, the target dielectric layer can be CoreA in the ART03 layer.

[0059] In some embodiments, if the target internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located is the ART03 layer shown in Table 1, optionally, a 0.5 oz copper foil and a first dielectric layer CoreB with a thickness of 1 mil located on the copper foil can be added on the upper side of the core material CoreA in the ART03 layer to obtain the adjusted partial laminate structure shown in Table 2.

[0060] Of course, in some embodiments, a 0.5oz copper foil and a first dielectric layer CoreB with a thickness of 1 mil located on the copper foil may be added to the lower side of the CoreA core material. This is not limited here and can be flexibly set according to the actual layout space.

[0061] In addition, it should be noted that when specifically arranging the first flat-plate capacitor with a target capacitance value, it should be arranged at the target coupling area of ​​the first high-speed signal line L1 and the second high-speed signal line L2 (where electrical connection between the first high-speed signal line L1 and the second high-speed signal line L2 is required to couple with the first dielectric layer D and the second metal conductor plate B to form the first flat-plate capacitor), so that the DC component transmitted between the first high-speed signal line L1 and the second high-speed signal line L2 can be blocked by the first flat-plate capacitor, and only the AC signal can be transmitted. It can be seen that the design method of the first flat-plate capacitor provided in the embodiment of the present application can not only realize the AC capacitive coupling design of the high-speed signal transmitted by the first high-speed signal line L1 and the second high-speed signal line L2, but also avoid the placement of layer-changing vias, surface routing and capacitors, increase the impedance consistency of the high-speed signal link, and improve the utilization of the PCB layout space, providing an effective guarantee for high-speed and high-density PCB design.

[0062] In summary, the embodiments of the present application provide a high-speed signal wiring structure for a chip, which includes: arranging a first flat plate capacitor on either side of a target dielectric layer in a target internal routing layer where a first high-speed signal line and a second high-speed signal line are located to form a target capacitance value that meets the requirements; wherein the first flat plate capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate, thereby realizing an AC capacitive coupling design of high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line through the first flat plate capacitor, avoiding the placement of layer-changing vias, surface routing, and capacitors, increasing the impedance consistency of the high-speed signal link, improving the utilization rate of the PCB layout space, and providing effective protection for high-speed and high-density PCB design.

[0063] Figure 4 This is a third schematic diagram of a high-speed signal wiring structure for a chip provided in an embodiment of the present application. In an optional embodiment, the first metal conductor plate includes a first sub-metal conductor plate and a second sub-metal conductor plate, the first sub-metal conductor plate being electrically connected to the first high-speed signal line, and the second sub-metal conductor plate being electrically connected to the second high-speed signal line.

[0064] Optionally, the target coupling region of the first high-speed signal line L1 and the second high-speed signal line L2 is used to couple with the first dielectric layer D and the second metal conductor plate B to form a first parallel plate capacitor. In some embodiments, the target coupling region may include a first sub-coupling region and a second sub-coupling region.

[0065] Accordingly, if Figures 2 to 4 As shown, the first metal conductor plate A may include two independent first sub-metal conductor plates A1 and second sub-metal conductor plates A2, wherein the first sub-metal conductor plate A1 may be electrically connected to the first high-speed signal line L1 to form a first sub-coupling region, and the second sub-metal conductor plate A2 may be electrically connected to the second high-speed signal line L2 to form a second sub-coupling region.

[0066] Optionally, the signal lines on two adjacent sides of the first sub-metal conductor plate A1 may be recorded as first signal lines LA1, and the signal lines on two adjacent sides of the second sub-metal conductor plate A2 may be recorded as second signal lines LA2.

[0067] In an optional embodiment, the first distance between the first sub-metal conductor plate A1 and the first signal lines LA1 on both adjacent sides meets the first preset distance requirement; the second distance between the second sub-metal conductor plate A2 and the second signal lines LA2 on both adjacent sides meets the first preset distance requirement.

[0068] It is understandable that the larger size of the first metal conductor plate A increases the coupling area with the second metal conductor plate B. However, due to the relatively dense layout of high-speed signal lines, a larger size of the first metal conductor plate A may affect the layout of other adjacent signals on the same layer. Optionally, to prevent the configuration of the first sub-metal conductor plate A1 and the second sub-metal conductor plate A2 from affecting adjacent signal lines in the target internal routing layer (for example, to avoid crosstalk), the first spacing between the first sub-metal conductor plate A1 and the first signal lines LA1 on both sides can be configured to meet a first preset spacing requirement, and the second spacing between the second sub-metal conductor plate A2 and the second signal lines LA2 on both sides can be configured to meet the first preset spacing requirement.

[0069] Optionally, the first preset spacing requirement can be determined based on a preset line width of the signal line. For example, in a certain implementation scenario, the preset line width is required to be W, and the first preset spacing requirement can be less than N times the preset line width W. In some embodiments, the value of N can be 3, that is, the first preset spacing requirement is greater than 3W. Of course, it should be noted that the specific setting method is not limited to this. The value of N can be determined based on the signal rate, where the higher the signal rate, the larger the value of N.

[0070] Reference Figure 4 As shown, the first high-speed signal line L1 and the second high-speed signal line L2 are used as single signal lines for illustration. The first spacing is S1, the second spacing is S2, the first signal line on the two adjacent sides of the first sub-metallic conductor plate A1 is LA1, and the second signal line on the two adjacent sides of the second sub-metallic conductor plate A2 is LA2. The first preset spacing requirement is to be greater than 3W. Specifically, the first sub-metallic conductor plate A1 and the second sub-metallic conductor plate A2 should be arranged such that S1>3W and S2>3W. Of course, it should be noted that the specific arrangement is not limited to this.

[0071] It should be noted that, in some embodiments, the first signal line LA1 and the second signal line LA2 located on the same side of the first high-speed signal line L1 may be the same signal line. If they are the same signal line, they should also meet the above layout rules.

[0072] In an optional embodiment, the second projection area SD of the second metal conductor pad B includes: a first sub-projection area SA1 of the first sub-metal conductor pad A1 and a second sub-projection area SA2 of the second sub-metal conductor pad A2, and the area of ​​the second projection area SD is greater than the sum of the areas of the first sub-projection area SA1 and the second sub-projection area SA2.

[0073] In order to better understand the present application, the relationship among the second metal conductor plate B, the first sub-metal conductor plate A1 and the second sub-metal conductor plate A2 is described from the perspective of the projection area.

[0074] Continue to refer to Figure 4 As shown, it can be seen that the first sub-metal conductor plate A1 and the first sub-metal conductor plate A1 are set to the same size, and the overlapping area of ​​the second projection area SD and the first sub-projection area SA1 is the first sub-projection area SA1, the overlapping area of ​​the second projection area SD and the second sub-projection area SA2 is the second sub-projection area SA2, and the area of ​​the second projection area SD is larger than the sum of the areas of the first sub-projection area SA1 and the second sub-projection area SA2, so that a first flat plate capacitor M1 with a target capacitance value can be formed between the first high-speed signal line L1 and the second high-speed signal line L2, and the first flat plate capacitor M1 can block the DC component transmitted between the first high-speed signal line L1 and the second high-speed signal line L2, and only transmit AC signals.

[0075] In addition, it should be noted that although the effective coupling area of ​​the coupling capacitor formed by the first metal conductor plate A and the second metal conductor plate B is the area of ​​the projection area corresponding to the first metal conductor plate A, in some embodiments, the second projection area of ​​the second projection area SD can still be set to be larger than the first projection area of ​​the first metal conductor plate A, so that the parasitic capacitive effect at high frequency can be better utilized, making the target capacitance value of the coupling easier to achieve.

[0076] In order to better understand the size relationship between the second projection area SD of the second metal conductor plate B and the first projection area of ​​the first metal conductor plate A, the sizes of the first sub-metal conductor plate A1 and the second sub-metal conductor plate A2 can be 0.25mm*0.25mm respectively, and the size of the second metal conductor plate B can be 0.3mm*0.8mm. Of course, the specific setting method is not limited to this.

[0077] In an optional embodiment, the second metal conductor plate B is obtained by etching a second metal conductor layer disposed on either side of a target dielectric layer in a target internal wiring layer.

[0078] Optionally, the second metal conductor plate B can be generated through an etching operation. For example, a second metal conductor layer can be laid below the first metal conductor plate A (i.e., above the target dielectric layer) and etched to form a region of a specific shape. This region of a specific shape can be considered the second metal conductor plate B. In other words, the second metal conductor layer can be made to retain only the size of the second metal conductor plate B, and the remaining copper foil can be etched away to avoid affecting the impedance consistency of the signal line. The specific shape can be a rectangle. Of course, the present application does not limit the size of this region, and it can be flexibly set according to the actual application scenario.

[0079] In some embodiments, the second metal conductor layer may be copper, or other conductive materials, and may be flexibly configured according to the actual application scenario. Optionally, the thickness of the copper may be 0.5 oz or 1 / 3 oz, which is not limited here.

[0080] Figure 5 This is a fourth schematic diagram of a high-speed signal wiring structure of a chip provided by an embodiment of the present application. In an optional embodiment, the third spacing between the second metal conductor plate B and the third signal lines on two adjacent sides meets the third preset spacing requirement.

[0081] Among them, referring to the above, it can be seen that the size of the second metal conductor plate should be larger than the sum of the sizes of the first sub-metal conductor plate and the second sub-metal conductor plate. In some embodiments, the third spacing between the second metal conductor plate B and the third signal lines on the adjacent two sides should be larger than half of the preset routing spacing to avoid affecting other adjacent signals. Among them, the preset routing spacing can be set according to the preset line width. For example, W is the preset line width of the signal line, and the preset routing spacing can be 3W.

[0082] Reference Figure 5 In the figure, a first high-speed signal line L1 and a second high-speed signal line L2 are used as two signal lines (e.g., differential signal lines) for illustration. The first high-speed signal line L1 includes a first high-speed sub-signal line L1_1 and a second high-speed sub-signal line L1_2, and the second high-speed signal line L2 includes a third high-speed sub-signal line L2_1 and a fourth high-speed sub-signal line L2_2. A first sub-coupling region exists between the first high-speed sub-signal line L1_1 and the third high-speed sub-signal line L2_1, and a second sub-coupling region exists between the second high-speed sub-signal line L1_2 and the fourth high-speed sub-signal line L2_2. Referring to the above embodiment, a first sub-plate capacitor H1 is provided in the first sub-coupling region, and a second sub-plate capacitor H2 is provided in the second sub-coupling region. In each sub-plate capacitor, a first spacing between the first sub-metal conductor plate and the adjacent first signal line LA1 meets a first predetermined spacing requirement, and a second spacing between the second sub-metal conductor plate and the adjacent second signal line LA2 meets the first predetermined spacing requirement.

[0083] Optionally, the signal lines on the two adjacent sides of the second metal conductor plate B can be recorded as third signal lines. In some embodiments, such as Figure 5 As shown, taking the first sub-panel capacitor H1 as an example, the third spacing S3 between the second metal conductor plate and the third signal line LC1 in the first sub-panel capacitor H1 should be greater than half of the preset routing spacing (for example, 3W / 2). For the description of other third signal lines (LC2, LC3, LC4), please refer to the description of the third signal line LC1, which will not be repeated here.

[0084] In addition, it should be noted that Figure 5 In the embodiment shown, if the first high-speed signal line L1 and the second high-speed signal line L2 are differential signal lines, the fourth spacing S4 between the second metal conductor plate in the first sub-panel capacitor H1 and the second metal conductor plate in the second sub-panel capacitor H2 needs to be consistent with the differential signal line spacing (for example, the spacing between the first high-speed sub-signal line and the second high-speed sub-signal line).

[0085] In an optional embodiment, the thickness and dielectric constant of the first dielectric layer D are determined according to a target capacitance value.

[0086] It should be noted that when laying the first dielectric layer, the thickness should be small, so that a large equivalent capacitance is formed in the coupling area, while not affecting the impedance consistency of the signal line outside the coupling area. For example, in some scenarios, although the dielectric constant of the first dielectric layer is large, its thin thickness will have little impact on the impedance of the signal line.

[0087] Among them, the target capacitance value of the first flat plate capacitor M1 can be determined according to the thickness and dielectric constant of the first dielectric layer D. The purpose of adding the first dielectric layer D is to produce an insulating cavity of the capacitor, that is, the first metal conductor plate A, the second metal conductor plate B and the first dielectric layer D together form a capacitor cavity, forming a target capacitance value that meets the requirements, thereby realizing a coupling design.

[0088] It should be noted that, the smaller the thickness of the first dielectric layer D and the larger the dielectric constant, the larger the target capacitance value generated.

[0089] For example, to generate a target capacitance of 220 nF, the thickness of the added first dielectric layer D may be less than 1 mil, and the dielectric constant of the first dielectric layer D may be approximately 30. Of course, the specific configuration is not limited thereto.

[0090] Figure 6This is a fifth schematic diagram of a high-speed signal wiring structure for a chip provided in an embodiment of the present application. In an optional embodiment, the target internal routing layer further includes: a third high-speed signal line L3 and a fourth high-speed signal line L4, wherein the third high-speed signal line L3 is adjacent to the first high-speed signal line L1, and the fourth high-speed signal line L4 is adjacent to the second high-speed signal line L2; and a second flat-plate capacitor M2 is arranged on either side of the target dielectric layer in the target internal routing layer where the third high-speed signal line L3 and the fourth high-speed signal line L4 are located.

[0091] The second flat plate capacitor M2 is staggered with the first flat plate capacitor M1 , and includes a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

[0092] The specific composition of the second flat plate capacitor M2 can be found in the related content of the first flat plate capacitor W1 , which will not be described in detail here.

[0093] It should be noted that the position of the second flat capacitor M2 in the target internal routing layer can be flexibly set. In some embodiments, the second flat capacitor M2 can be arranged on the upper side of the target dielectric layer in the target internal routing layer, or on the lower side of the target dielectric layer in the target internal routing layer. This is not limited here and can be flexibly set according to the actual application scenario.

[0094] In some embodiments, the first flat plate capacitor M1 and the second flat plate capacitor M2 may be arranged on the same side or on different sides of the target dielectric layer in the target internal wiring layer, which is not limited here and can be flexibly described according to actual application scenarios.

[0095] Furthermore, if Figure 6 As shown, in some embodiments, if the first flat plate capacitor M1 and the second flat plate capacitor M2 are arranged on the same side of the target dielectric layer in the target internal routing layer, the second flat plate capacitor and the first flat plate capacitor M1 can be staggered, that is, adjacent signal coupling areas are staggered, thereby increasing space utilization.

[0096] In an optional embodiment, the first flat plate capacitor M1 and the second flat plate capacitor M2 can be arranged on opposite sides of the target dielectric layer in the target internal routing layer, with the first flat plate capacitor M1 arranged on the upper side of the target dielectric layer and the second flat plate capacitor M2 arranged on the lower side of the target dielectric layer; or, the first flat plate capacitor M1 is arranged on the lower side of the target dielectric layer and the second flat plate capacitor M2 is arranged on the upper side of the target dielectric layer.

[0097] It can be understood that by setting it on different sides, the applicability and flexibility of the method of the present application can be increased, providing more options for the design of high-speed and high-density PCBs.

[0098] Of course, it should be noted that this application does not limit the specific layout method, and it can be flexibly set according to the actual application scenario.

[0099] In an optional embodiment, the first sub-metal conductor plate and the second sub-metal conductor plate have the same size.

[0100] Optionally, in some embodiments, the coupling area S in the first parallel plate capacitor, the dielectric constant E, and the thickness F of the first dielectric layer D may be determined referring to the following method.

[0101] First, based on the application scenarios of the first high-speed signal line L1 and the second high-speed signal line L2, a target capacitance C of the first flat plate capacitor is determined. The coupling area formed by the first metal conductor plate A and the second metal conductor plate B is denoted as S, and the dielectric constant and thickness of the first dielectric layer D are denoted as E and D. During the optimization process, the thickness F is kept constant, the coupling area D and the dielectric constant E are adjusted, and the capacitance C0 of the first flat plate capacitor is calculated. A comparison is made to determine whether C0 equals the target capacitance C. If not, the effective coupling area D and the dielectric constant E are readjusted, and the capacitance C0 of the first flat plate capacitor is calculated until C0 equals the target capacitance C. At this point, a first flat plate capacitor structure that meets the target capacitance is obtained. Furthermore, the type of the first dielectric layer D and the coupling area requirement are determined based on the adjusted dielectric constant E. Subsequently, based on the determined coupling area S, the dielectric constant E, and the thickness F of the first dielectric layer D, the corresponding first flat plate capacitors are arranged on either side of the target dielectric layer in the target internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located.

[0102] It can be understood that after determining the coupling area of ​​the first flat plate capacitor, the sizes of the first sub-metal conductor plate and the second sub-metal conductor plate can be set accordingly. For example, the sizes of the first sub-metal conductor plate and the second sub-metal conductor plate can be set to half of the coupling area, thereby achieving rapid setting. Of course, the specific setting method is not limited to this.

[0103] Figure 7 The embodiment of the present application provides a high-speed signal wiring method for a chip. The execution subject of the method can be a high-speed signal wiring device. The basic principle and technical effects of the method are the same as those of the corresponding structural embodiment described above. For the sake of brief description, the parts not mentioned in this embodiment can be referred to the corresponding content in the method embodiment. Figure 7 As shown, the method includes:

[0104] Step 101: Determine a target internal routing layer where a first high-speed signal line and a second high-speed signal line of a target circuit are located and where a first parallel-plate capacitor is required to be arranged, according to an initial stacking structure corresponding to the target circuit.

[0105] Among them, the target circuit can be a part of the circuit in the integrated circuit corresponding to the chip. Optionally, the target internal routing layer can be any routing layer in the initial stacking structure corresponding to the target circuit, which has high-speed signal lines and requires AC coupling capacitors between the high-speed signal lines. This is not limited here.

[0106] Step 102 : Arrange a first flat plate capacitor on either side of a target dielectric layer in a target internal wiring layer where the first high-speed signal line and the second high-speed signal line are located, so as to form a target capacitance value that meets requirements.

[0107] The first flat plate capacitor includes a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

[0108] The specific configuration of the first flat plate capacitor can be found in the related contents of the aforementioned embodiment and will not be described again here.

[0109] In an optional embodiment, the first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate, the first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line.

[0110] In an optional embodiment, a first distance between the first sub-metal conductor plate and the first signal lines on two adjacent sides meets a first preset distance requirement;

[0111] A second distance between the second sub-metal conductor plate and the second signal lines on two adjacent sides meets a first preset distance requirement.

[0112] In an optional embodiment, the second projection area of ​​the second metal conductor plate includes: the first sub-projection area of ​​the first sub-metal conductor plate and the second sub-projection area of ​​the second sub-metal conductor plate, and the area of ​​the second projection area is greater than the sum of the areas of the first sub-projection area and the second sub-projection area.

[0113] In an optional embodiment, the second metal conductor plate is obtained by etching a second metal conductor layer disposed on either side of a target dielectric layer in a target internal wiring layer.

[0114] In an optional embodiment, a third distance between the second metal conductor plate and the third signal lines on two adjacent sides meets a third preset distance requirement.

[0115] In an optional embodiment, the thickness and dielectric constant of the first dielectric layer are determined according to the target capacitance value.

[0116] In an optional embodiment, the target internal routing layer further includes: a third high-speed signal line and a fourth high-speed signal line, the third high-speed signal line is adjacent to the first high-speed signal line, and the fourth high-speed signal line is adjacent to the second high-speed signal line;

[0117] Arrange a second flat plate capacitor on either side of a target dielectric layer in a target internal wiring layer where the third high-speed signal line and the fourth high-speed signal line are located;

[0118] The second flat plate capacitor is staggered with the first flat plate capacitor, and comprises a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

[0119] In an optional embodiment, the first flat plate capacitor is arranged on the upper side of the target dielectric layer, and the second flat plate capacitor is arranged on the lower side of the target dielectric layer; or, the first flat plate capacitor is arranged on the lower side of the target dielectric layer, and the second flat plate capacitor is arranged on the upper side of the target dielectric layer.

[0120] In an optional embodiment, the first sub-metal conductor plate and the second sub-metal conductor plate have the same size.

[0121] By applying the embodiments of the present application, an AC capacitor coupling design of high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line can be realized through the first flat capacitor, thereby avoiding the placement of layer-changing vias, surface routing and capacitors, increasing the impedance consistency of the high-speed signal link, improving the utilization of the PCB layout space, and providing effective protection for high-speed and high-density PCB design.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0123] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0124] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0125] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor (English: processor) to perform some steps of the methods of each embodiment of the present application. The aforementioned storage medium includes: USB flash drives, mobile hard drives, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: Random Access Memory, abbreviated: RAM), magnetic disks or optical disks, and other media that can store program code.

[0126] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0127] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A high-speed signal wiring structure for a chip, characterized in that: include: Arrange a first flat plate capacitor on either side of a target dielectric layer in a target internal wiring layer where the first high-speed signal line and the second high-speed signal line are located, so as to form a target capacitance value that meets the requirements; The first flat plate capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate; The first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate. The first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line, so as to realize AC capacitive coupling design of high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line through the first flat plate capacitor.

2. The high-speed signal wiring structure according to claim 1, wherein: A first distance between the first sub-metal conductor plate and the first signal lines on two adjacent sides meets a first preset distance requirement; A second distance between the second sub-metal conductor plate and the second signal lines on two adjacent sides meets a first preset distance requirement.

3. The high-speed signal wiring structure according to claim 1, wherein: The second projection area of ​​the second metal conductor plate includes: the first sub-projection area of ​​the first sub-metal conductor plate and the second sub-projection area of ​​the second sub-metal conductor plate, and the area of ​​the second projection area is greater than the sum of the areas of the first sub-projection area and the second sub-projection area.

4. The high-speed signal wiring structure according to claim 1, wherein: The second metal conductor plate is obtained by etching a second metal conductor layer disposed on either side of a target dielectric layer in a target internal wiring layer.

5. The high-speed signal wiring structure according to claim 1, wherein: A third distance between the second metal conductor plate and the third signal lines on two adjacent sides meets a third preset distance requirement.

6. The high-speed signal wiring structure according to claim 1, wherein: The thickness and dielectric constant of the first dielectric layer are determined according to the target capacitance value.

7. The high-speed signal wiring structure according to claim 1, wherein: The first sub-metal conductor plate and the second sub-metal conductor plate have the same size.

8. The high-speed signal wiring structure according to any one of claims 1 to 7, wherein: The target internal routing layer further includes: a third high-speed signal line and a fourth high-speed signal line, the third high-speed signal line is adjacent to the first high-speed signal line, and the fourth high-speed signal line is adjacent to the second high-speed signal line; Arrange a second flat plate capacitor on either side of a target dielectric layer in a target internal wiring layer where the third high-speed signal line and the fourth high-speed signal line are located; The second flat plate capacitor is staggered with the first flat plate capacitor, and comprises a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

9. The high-speed signal wiring structure according to claim 8, wherein: The first flat plate capacitor is arranged on the upper side of the target dielectric layer, and the second flat plate capacitor is arranged on the lower side of the target dielectric layer; or The first flat plate capacitor is arranged at the lower side of the target dielectric layer, and the second flat plate capacitor is arranged at the upper side of the target dielectric layer.

10. A high-speed signal wiring method for a chip, characterized in that: The method comprises: Determining, based on an initial stacking structure corresponding to the target circuit, a target internal routing layer where a first high-speed signal line and a second high-speed signal line of a first flat-plate capacitor are to be arranged in the target circuit; Arranging a first flat plate capacitor on either side of a target dielectric layer in a target internal routing layer where the first high-speed signal line and the second high-speed signal line are located, so as to form a target capacitance value that meets requirements; The first flat plate capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first and second metal conductor plates; the first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate, the first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line, so as to implement an AC capacitive coupling design of the high-speed signals transmitted by the first and second high-speed signal lines through the first flat plate capacitor.

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