Memristor synapse array supporting online learning of spiking neural network

Abstract

The invention relates to a memristor synapse array supporting online learning of a pulse neural network, the memristor synapse array comprises n * k * i 2T2R units, the memristor synapse array is composed of k sub-arrays, each sub-array comprises n 2T2R unit blocks Block, and each 2T2R unit block Block comprises i 2T2R units; each subarray and a peripheral circuit of the 2T2R unit block form i word line signal ends WL, i / 2 bias signal ends SL, a pair of reverse reasoning signal ends INB and INF, n pairs of enabling signal ends RWP and RWN, n pairs of weight output ends IBLP and IBLN, and n pairs of bit line signal ends ABLP and bit line signal ends ABLN; and the peripheral circuit of the 2T2R unit block Block comprises two pairs of NMOS (N-channel Metal Oxide Semiconductor) tubes mpi0 and mni0 as well as mpa0 and mna0 on the outer side of the 2T2R unit block Block. Compared with the prior art, the method has the advantages of reducing related power consumption overhead and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of memristor synaptic arrays, and in particular to a memristor synaptic array supporting online learning of a pulse neural network. Background Art

[0002] Driven by large computing power models, traditional silicon-based semiconductors cannot meet the needs of high computing density and high storage density due to physical limitations. In recent years, with the development of related technologies, the number of parameters required for large model calculations has reached hundreds of billions, and the gap between model iteration and computing power expansion has become increasingly larger: even with the most advanced hardware facilities, training ultra-large-scale models faces huge computing pressure. At the same time, as the scale of the model increases, the computing power of a single chip can no longer meet the demand under the constraints of the limits of traditional semiconductor processes, and the industry has to adopt distributed training and multi-chip interconnection strategies to complete the calculation of large models. This also leads to a large amount of energy consumption on the hardware side during training, especially high-performance computing devices such as GPUs and TPUs, which will generate high power consumption and carbon emissions. Therefore, in order to ensure the computing capacity of the chip while reducing its computing load and computing power consumption, the industry has proposed network models with lower computing overhead, such as pulse neural networks that are more suitable for biological behavior mechanisms and more hardware-friendly; on the other hand, it has proposed the concept of designing dedicated computing chips to alleviate the problems of "storage wall" and "power consumption wall". Among them, a research team has opened up a path to combine multi-valued new memristor memory with in-memory computing.

[0003] If the spiking neural network is integrated with the memristor memory chip, it may be able to alleviate the computing bottleneck in terminal applications to a certain extent, but in actual deployment, there are still many problems to be solved in this field. In spiking neural networks, memristors are usually used as carriers of network weights to characterize the connection strength between different neurons. However, when the network is trained on-chip, the industry generally uses traditional static random access memory SRAM, which requires charging and discharging operations on long parasitic capacitances, adding additional hardware overhead and data transmission power consumption, limiting the bandwidth and latency of the system. Summary of the invention

[0004] The purpose of the present invention is to provide a memristor synaptic array that supports online learning of pulse neural networks in order to reduce related power consumption.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] A memristor synaptic array supporting online learning of spiking neural networks, comprising n*k*i 2T2R units. The memristor synaptic array is composed of k sub-arrays SubArray. Each sub-array SubArray includes n 2T2R unit blocks Block, and each 2T2R unit block Block includes i 2T2R units;

[0007] Each sub-array SubArray and the peripheral circuits of the 2T2R unit blocks Block therein form i word line signal terminals WL, i / 2 bias signal terminals SL, 1 pair of reverse inference signal terminals INB and inference signal terminal INF, n pairs of enable signal terminals RWP and enable signal terminal RWN, n pairs of weight output terminals IBLP and weight output terminal IBLN, and n pairs of bit line signal terminals ABLP and bit line signal terminal ABLN;

[0008] The peripheral circuit of the 2T2R unit block Block includes two pairs of NMOS transistors mpi0 and mni0 and mpa0 and mna0 outside the 2T2R unit block Block.

[0009] Further, in the peripheral circuit of the a-th 2T2R unit block Block, one end of the NMOS transistor mpi0 is connected to the bit line signal terminal ABLP[a], one end of the NMOS transistor mpa0 and the other end of the NMOS transistor mpi0 are connected to the bit line terminal BL1 of the 2T2R unit, the gate of the NMOS transistor mpi0 is connected to the first CMOS transmission gate tgp0, and the other end of the NMOS transistor mpa0 is connected to the a-th weight output terminal IBLP[a].

[0010] Further, in the peripheral circuit of the a-th 2T2R unit block Block, one end of the NMOS transistor mni0 is connected to the bit line signal terminal ABLN[a], one end of the NMOS transistor mna0 and the other end of the NMOS transistor mni0 are connected to the bit line terminal BL2 of the 2T2R unit, the gate of the NMOS transistor mni0 is connected to the second CMOS transmission gate tgn0, and the other end of the NMOS transistor mna0 is connected to the a-th weight output terminal IBLN[a].

[0011] Further, in the a-th 2T2R unit block Block, the gates of the NMOS transistors mpa0 and mna0 are connected together and are connected to the inference signal terminal INF.

[0012] Further, the 2T2R unit includes two upper and lower 2T2R structures. The source line terminals of the two 2T2R structures are connected to each other, the bit line terminals BL1 on the same side of the two 2T2R structures are connected to each other, and the bit line terminals BL2 on the same side are connected to each other. At the same time, the bit line terminals BL1 on the same side of each 2T2R unit are connected to each other, and the bit line terminals BL2 on the same side are connected to each other. The 2T2R structure includes a positive unit memristor and a supporting unit memristor.

[0013] Further, one word line terminal of a 2T2R in the b-th 2T2R unit in a 2T2R unit block Block is connected to the word line signal terminal WL[2b - 2], and the other word line terminal of the 2T2R is connected to the word line signal terminal WL[2b - 1]. The source line terminals of the b-th 2T2R unit are collectively connected to the bias signal terminal SL[b - 1], where b = 1, 2,..., i / 2.

[0014] Further, the first CMOS transmission gate tgp0 of the a-th 2T2R unit block Block is connected to the a-th enable signal terminal RWP[a - 1], the second CMOS transmission gate tgn0 of the a-th 2T2R unit block Block is connected to the a-th enable signal terminal RWN[a - 1], and the first CMOS transmission gate tgp0 and the second CMOS transmission gate tgn0 are collectively connected to the reverse inference signal terminal INB.

[0015] The present invention also proposes a control method for a memristor synaptic array supporting online learning of a spiking neural network, characterized in that the above-mentioned memristor synaptic array is adopted, and the method includes a training part and an inference part of the memristor synaptic array;

[0016] The inference part includes:

[0017] When receiving the network inference current, control the NMOS transistors mpi0 and mni0 in all sub-arrays to be in the off state; the NMOS transistors mpa0 and mna0 are in the on state, and the current flows from the bias signal terminal SL through each 2T2R unit, and is aggregated to the weight output terminal IBLP and the weight output terminal IBLN, and the currents of the weight output terminal IBLP and the weight output terminal IBLN are subjected to addition and subtraction operations to complete the reading of the positive and negative weights of the network;

[0018] The training part includes:

[0019] Control the inference signal terminal INF in the 2T2R unit block Block to be trained to be turned off. For the training of the positive unit memristor of the upper 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by turning on the word line signal terminal WL[2b - 2] and the enable signal terminal RWP[a - 1], the training operation of the positive unit memristor is determined based on the relative potentials of the bit line signal terminal ABLP[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block;

[0020] For the training of the negative unit memristor of the upper 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in SubArray, by enabling the word line signal terminal WL[2b - 2] and the enable signal terminal RWN[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLN[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block;

[0021] For the training of the positive unit memristor of the lower 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in SubArray, by enabling the word line signal terminal WL[2b - 1] and the enable signal terminal RWP[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block;

[0022] For the training of the negative unit memristor of the lower 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in SubArray, by enabling the word line signal terminal WL[2b - 1] and the enable signal terminal RWN[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLN[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block.

[0023] Furthermore, determining the training operation of the memristor according to the relative potential includes: performing a set operation when applying a positive voltage at the top electrode terminal of the memristor, that is, the end where the memristor is not directly connected to the corresponding 2T2R internal transistor, and writing the device as a low resistance state; performing a reset operation when applying a positive voltage at the bottom electrode terminal of the memristor, that is, the end where the memristor is directly connected to the corresponding 2T2R internal transistor, and writing the device as a high resistance state.

[0024] Furthermore, in the inference part, in the resting state before receiving the network inference current, all inference signal terminals INF are in the enabled state, and all bias signals SL also maintain their inference voltages.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The synaptic array structure of the present invention that adopts array partitioning and transmission path separation can meet the requirements of low-power online learning of spiking neural networks. While enabling access to any unit, it reduces the power consumption of weight operations. The word line signals WL and bias signals SL arranged in the row direction ensure the parallel computing of the synaptic array. The additional computing transistors in each unit block, namely two pairs of NMOS transistors mpi0 and mni0, and mpa0 and mna0, under flexible switching control, avoid the charge and discharge operations of the parasitic capacitance of the long transmission line, reduce the related power consumption overhead, and while being conducive to the dedicated optimization of the peripheral circuit for weight inference and weight update, it can also achieve access and programming of each unit in the column direction, thus providing a complete hardware foundation for the online learning of neural networks. Brief Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of the present invention;

[0028] Figure 2 is the waveform of the relevant node voltage of a single memristor representing a negative weight during the weight reading and weight update states in the network operation process. Detailed Embodiment

[0029] The present invention will be described in detail below with reference to the drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and the detailed implementation manners and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.

[0030] The present invention proposes a memristor synaptic array supporting online learning of spiking neural networks, and the structural diagram is as Figure 1 shown. It includes n*k*i 2T2R units. The memristor synaptic array is composed of k sub-arrays SubArray. Each sub-array SubArray includes n 2T2R unit blocks Block, and each 2T2R unit block Block includes i 2T2R units;

[0031] Each sub-array SubArray and the peripheral circuit of the 2T2R unit block Block form i word line signal terminals WL, i / 2 bias signal terminals SL, 1 pair of reverse inference signal terminals INB and inference signal terminals INF, n pairs of enable signal terminals RWP and enable signal terminals RWN, n pairs of weight output terminals IBLP and weight output terminals IBLN, and n pairs of bit line signal terminals ABLP and bit line signal terminals ABLN;

[0032] The peripheral circuit of the 2T2R unit block Block includes two pairs of NMOS transistors mpi0 and mni0, and mpa0 and mna0 outside the 2T2R unit block Block.

[0033] In the peripheral circuit of the a-th 2T2R unit block Block, one end of the NMOS transistor mpi0 is connected to the bit line signal terminal ABLP[a], one end of the NMOS transistor mpa0 and the other end of the NMOS transistor mpi0 are connected to the bit line terminal BL1 of the 2T2R unit, the gate of the NMOS transistor mpi0 is connected to the first CMOS transmission gate tgp0, and the other end of the NMOS transistor mpa0 is connected to the a-th weight output terminal IBLP[a].

[0034] In the peripheral circuit of the a-th 2T2R unit block Block, one end of the NMOS transistor mni0 is connected to the bit line signal terminal ABLN[a], one end of the NMOS transistor mna0 and the other end of the NMOS transistor mni0 are connected to the bit line terminal BL2 of the 2T2R unit, the gate of the NMOS transistor mni0 is connected to the second CMOS transmission gate tgn0, and the other end of the NMOS transistor mna0 is connected to the a-th weight output terminal IBLN[a].

[0035] In the a-th 2T2R unit block Block, the gates of the NMOS transistors mpa0 and mna0 are connected together and are connected to the inference signal terminal INF.

[0036] The 2T2R unit includes two upper and lower 2T2R structures. The source line terminals of the two 2T2R structures are connected to each other. The bit line terminals BL1 on the same side of the two 2T2R structures are connected to each other, and the bit line terminals BL2 on the same side are connected to each other. At the same time, the bit line terminals BL1 on the same side of each 2T2R unit are connected to each other, and the bit line terminals BL2 on the same side are connected to each other. The 2T2R structure includes a positive unit memristor and a supporting unit memristor.

[0037] In the b-th 2T2R unit of a 2T2R unit block Block, one word line terminal of one 2T2R is connected to the word line signal terminal WL[2b - 2], and the other word line terminal of the other 2T2R is connected to the word line signal terminal WL[2b - 1]. The source line terminals of the b-th 2T2R unit are connected together to the bias signal terminal SL[b - 1], where b = 1, 2,... i / 2.

[0038] The first CMOS transmission gate tgp0 of the a-th 2T2R unit block Block is connected to the a-th enable signal terminal RWP[a - 1], the second CMOS transmission gate tgn0 of the a-th 2T2R unit block Block is connected to the a-th enable signal terminal RWN[a - 1], and the first CMOS transmission gate tgp0 and the second CMOS transmission gate tgn0 are connected together to the reverse inference signal terminal INB.

[0039] The present invention also proposes a control method for a memristor synaptic array supporting online learning of a spiking neural network. Using the above-mentioned memristor synaptic array, the method includes a training part and an inference part of the memristor synaptic array;

[0040] The inference part includes:

[0041] When receiving the network inference current, control the NMOS transistors mpi0 and mni0 in all sub-arrays to be in the off state; the NMOS transistors mpa0 and mna0 are in the on state, and the current flows from the bias signal terminal SL through each 2T2R unit and is aggregated to the weight output terminal IBLP and the weight output terminal IBLN. Perform addition and subtraction operations on the currents of the weight output terminal IBLP and the weight output terminal IBLN to complete the reading of the positive and negative weights of the network;

[0042] The training part includes:

[0043] Control the inference signal terminal INF in the 2T2R unit block Block to be trained to be turned off. For the training of the positive unit memristor of the upper 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by enabling the word line signal terminal WL[2b - 2] and the enable signal terminal RWP[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block;

[0044] For the training of the negative unit memristor of the upper 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by enabling the word line signal terminal WL[2b - 2] and the enable signal terminal RWN[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLN[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block;

[0045] For the training of the positive unit memristor of the lower 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by enabling the word line signal terminal WL[2b - 1] and the enable signal terminal RWP[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block;;

[0046] For the training of the negative unit memristor in the lower 2T2R structure of the b-th 2T2R unit in the a-th 2T2R unit block Block that needs to be trained in the SubArray, by enabling the word line signal terminal WL[2b - 1] and the enable signal terminal RWN[a - 1], the training operation of the positive unit memristor is determined based on the relative potential of the bit line signal terminal ABLN[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit in the a-th 2T2R unit block Block.

[0047] The present invention proposes a multi-valued memristor synaptic array that supports online learning of spiking neural networks. By enabling different select tubes, the array can perform inference and training of on-chip spiking neural networks, and can also optimize the respective transmission paths for network inference and weight update operations; in addition, the introduced macro cell block scheme helps to reduce parasitic parameters during the operation of memristors, thereby reducing the energy consumption of neural network inference.

[0048] The memristor synaptic array consists of n*k*i 2T2R units. Every i rows of 2T2R form a sub-array SubArray, and each sub-array contains n columns of 2T2R unit blocks Block. To reduce the performance overhead of on-chip training and the impact on network inference, a set of computing tubes is designed for each unit block Block to assist in the on-chip training and inference of spiking neural networks. Finally, each sub-array and the peripheral circuit form i WLs, i / 2 SLs, 1 pair of INB and INF, n pairs of RWP and RWN, n pairs of IBLP and IBLN, and n pairs of ABLP and ABLN interface signals. The reading and writing of the corresponding memristors are controlled by their respective word line signals WL (the memristors rp0 and rn0 are enabled by WL[0]; the memristors rp1 and rn1 are enabled by WL[1]). The reading and writing currents of the memristor units are transmitted through the outer two pairs of NMOS tubes (mpi0 and mni0; mpa0 and mna0).

[0049] During the process of neural network inference, the select tubes mpi0 and mni0 in all sub-arrays are in the off state; the select tubes mpa0 and mna0 are in the on state, and the current flows from the bias signal SL terminal, through the memristor, and converges to the IBLP and IBLN terminals. Combining with the operation circuit module, the currents at the IBLP and IBLN terminals are added and subtracted to complete the reading of the positive and negative weights of the network; during the process of neural network weight update, the transistors mpa0 and mna0 in the selected sub-array are in the off state, and the mpa0 and mna0 in the unselected sub-arrays are still in the on state. The RWP and RWN signals in the column direction cooperate with the word line signal WL to achieve access and write operations on the resistance state of a single device, and the multi-valued switching of the resistance state is controlled by the bias signal SL, the bit line signals ABLP and ABLN, and the gate voltage WL.

[0050] Control method: Since the weight reading operation occupies the main part of the neural network operation cycle, all inference signals INF are in the enabled state and all bias signals SL maintain their respective inference voltages when the synaptic array is in the resting state. Whenever an input pulse related to network inference arrives, only enabling the word line signal WL can immediately put the synaptic array into the weight reading state.

[0051] During network training when the memristor weights need to be updated, the select tubes mpi0 and mni0; mpa0 and mna0 inside the unselected sub-arrays maintain the state during weight reading, and their INF signals are also in the enabled state to reduce the power consumption of signal switching. The INF signal inside the selected sub-array is turned off, and each memristor unit inside this sub-array is jointly controlled by the word line signal WL and the read / write enable signals RWP and RWN: when WL[0] and RWP[0] are turned on, the relative potential between SL[0] and ABLP[0] determines whether to perform a Reset operation or a Set operation on the memristor rp0; when WL[0] and RWN[0] are turned on, the relative potential between SL[0] and ABLN[0] determines whether to perform a Reset operation or a Set operation on the memristor rn0. After each write operation, the bias signal SL switches to a lower read voltage, and ABLP or ABLN collects the current of the corresponding device and determines whether to write to the same unit again to ensure accurate update of the resistance state.

[0052] The synaptic array structure adopting array partitioning and transmission path separation can meet the requirements of low-power online learning of spiking neural networks. The word line signal WL and the bias signal SL arranged in the row direction ensure the parallel computing of the synaptic array. The additional computing tubes in each unit block, under flexible switching control, avoid the charge and discharge operations on the parasitic capacitance of the long wire, reduce the related power consumption overhead, and while being beneficial for the peripheral circuit to specifically optimize weight inference and weight update, can also achieve the access and programming of each unit in the column direction, thus providing a complete hardware foundation for the online learning of neural networks.

[0053] Due to the added transmission path, some signals inside the array can remain in a fixed state for a long time after power-on, reducing the energy consumption introduced by parasitic parameters after each input pulse arrives, and effectively improving the network inference energy efficiency.

[0054] Figure 1 The structure diagram of the multi-valued memristor synaptic array based on the online learning of spiking neural networks is given; Figure 2 The relevant node voltage waveforms of a single memristor representing negative weights in the weight reading and weight update states during the network operation are given.

[0055] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations based on the concept of the present invention without creative work. Therefore, all technical solutions that can be obtained by those skilled in the art in this technical field based on the concept of the present invention through logical analysis, reasoning, or limited experiments on the basis of the prior art should fall within the protection scope determined by the claims.

Claims

1. A memristor synaptic array supporting online learning of spiking neural networks, characterized in that, It includes n*k*i 2T2R units. The memristor synaptic array consists of k sub-arrays SubArray. Each sub-array SubArray includes n 2T2R unit blocks Block, and each 2T2R unit block Block includes i 2T2R units; For each sub-array SubArray, i word line signal terminals WL, i / 2 bias signal terminals SL, 1 pair of reverse inference signal terminals INB and inference signal terminal INF, n pairs of enable signal terminals RWP and enable signal terminal RWN, n pairs of weight output terminals IBLP and weight output terminal IBLN, and n pairs of bit line signal terminals ABLP and bit line signal terminal ABLN are formed with the peripheral circuits of the 2T2R unit blocks Block therein; The peripheral circuit of the 2T2R unit block Block includes two pairs of NMOS transistors mpi0 and mni0 and mpa0 and mna0 outside the 2T2R unit block Block.

2. The memristor synaptic array for supporting online learning of spiking neural networks according to claim 1, wherein In the peripheral circuit of the a-th 2T2R unit block Block, one end of the NMOS transistor mpi0 is connected to the bit line signal terminal ABLP[a], one end of the NMOS transistor mpa0 and the other end of the NMOS transistor mpi0 are connected to the bit line terminal BL1 of the 2T2R unit, the gate of the NMOS transistor mpi0 is connected to the first CMOS transmission gate tgp0, and the other end of the NMOS transistor mpa0 is connected to the a-th weight output terminal IBLP[a].

3. The memristor synaptic array for supporting online learning of spiking neural networks according to claim 2, wherein, In the peripheral circuit of the a-th 2T2R unit block Block, one end of the NMOS transistor mni0 is connected to the bit line signal terminal ABLN[a], one end of the NMOS transistor mna0 and the other end of the NMOS transistor mni0 are connected to the bit line terminal BL2 of the 2T2R unit, the gate of the NMOS transistor mni0 is connected to the second CMOS transmission gate tgn0, and the other end of the NMOS transistor mna0 is connected to the a-th weight output terminal IBLN[a].

4. The memristor synaptic array for supporting online learning of spiking neural networks according to claim 3, wherein In the a-th 2T2R unit block Block, the gates of the NMOS transistors mpa0 and mna0 are connected together and are connected to the inference signal terminal INF.

5. The memristor synaptic array for supporting online learning of spiking neural networks according to claim 4, characterized in that, The 2T2R unit includes two 2T2R structures up and down. The source line terminals of the two 2T2R structures are connected to each other, the bit line terminals BL1 on the same side of the two 2T2R structures are connected to each other, and the bit line terminals BL2 on the same side are connected to each other. At the same time, the bit line terminals BL1 on the same side of each 2T2R unit are connected to each other, and the bit line terminals BL2 on the same side are connected to each other. The 2T2R structure includes a positive unit memristor and a supporting unit memristor.

6. The 2T2R memristor synaptic array for supporting online learning of spiking neural networks according to claim 5, wherein For the b-th 2T2R unit in a 2T2R unit block Block, one word line terminal of one 2T2R is connected to the word line signal terminal WL[2b - 2], and the other word line terminal of the other 2T2R is connected to the word line signal terminal WL[2b - 1]. The source line terminals of the b-th 2T2R unit are connected together to the bias signal terminal SL[b - 1], where b = 1, 2,..., i / 2.

7. The memristor synaptic array for supporting online learning of spiking neural networks according to claim 6, wherein The first CMOS transmission gate tgp0 of the a-th 2T2R unit block Block is connected to the a-th enable signal terminal RWP[a - 1], and the second CMOS transmission gate tgn0 of the a-th 2T2R unit block Block is connected to the a-th enable signal terminal RWN[a - 1]. The first CMOS transmission gate tgp0 and the second CMOS transmission gate tgn0 are jointly connected to the reverse inference signal terminal INB.

8. A control method for a memristor synaptic array supporting online learning of spiking neural networks, characterized in that, Using the memristor synaptic array according to any one of claims 1 to 7, the method includes a memristor synaptic array training part and an inference part; The inference part includes: When receiving the network inference current, control the NMOS transistors mpi0 and mni0 in all sub-arrays to be in the off state; the NMOS transistors mpa0 and mna0 are in the on state, and the current flows from the bias signal terminal SL through each 2T2R unit and is aggregated to the weight output terminal IBLP and the weight output terminal IBLN. Perform addition and subtraction operations on the currents of the weight output terminal IBLP and the weight output terminal IBLN to complete the reading of the positive and negative weights of the network; The training part includes: Control the inference signal terminal INF in the 2T2R unit block Block to be trained to be turned off. For the training of the positive unit memristor of the upper 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by turning on the word line signal terminal WL[2b - 2] and the enable signal terminal RWP[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block; For the training of the negative unit memristor of the upper 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by turning on the word line signal terminal WL[2b - 2] and the enable signal terminal RWN[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLN[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block; For the training of the positive unit memristor of the lower 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by turning on the word line signal terminal WL[2b - 1] and the enable signal terminal RWP[a - 1], determine the training operation of the positive unit memristor based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block; For the training of the negative unit memristor of the lower 2T2R structure in the b-th 2T2R unit of the a-th 2T2R unit block Block to be trained in the SubArray, by enabling the word line signal terminal WL[2b - 1] and the enable signal terminal RWN[a - 1], the training operation of the positive unit memristor is determined based on the relative potential of the bit line signal terminal ABLN[a] of the a-th 2T2R unit block Block and the bias signal terminal SL[b - 1] of the b-th 2T2R unit of the a-th 2T2R unit block Block.

9. The control method of a memristor synapse array supporting online learning of spiking neural networks according to claim 8, wherein Determining the training operation of the memristor according to the relative potential includes: performing a set operation when a positive voltage is applied to the top electrode terminal of the memristor, that is, the end where the memristor is not directly connected to the corresponding 2T2R internal transistor, and writing the device as a low resistance state; performing a reset operation when a positive voltage is applied to the bottom electrode terminal of the memristor, that is, the end where the memristor is directly connected to the corresponding 2T2R internal transistor, and writing the device as a high resistance state.

10. A control method for a memristor synaptic array supporting online learning of spiking neural networks, characterized in that, In the inference part, in the resting state before receiving the network inference current, all the inference signal terminals INF are in the enabled state, and all the bias signals SL also maintain their own inference voltages.

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