Delay power down control circuit, memory chip and reset method thereof

Abstract

The application provides a delay power-off control circuit, a memory chip and a reset method thereof. The delay power-off control circuit comprises: a delay power-off module, which receives an initial reset signal and generates a delay reset signal by performing a delay operation on the initial reset signal; and a power-off control module, which receives the initial reset signal and the delay reset signal and generates a chip reset signal based on the initial reset signal and the delay reset signal. The application solves the problem of false reset caused by power supply jitter in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and in particular to a delayed power-down control circuit, a memory chip, and a reset method thereof. Background Technology

[0002] Traditional reset circuits reset the chip by monitoring the power supply voltage in real time during normal operation using a power-down detection circuit. For memory chips, operations such as reading, writing, and erasing generate significant instantaneous current, causing a sudden drop in power supply voltage. Although this voltage drop is short and recovers quickly, it may still trigger the power-down detection circuit, leading to a chip reset. This type of reset is considered a false reset, and it's generally necessary to eliminate this problem caused by power supply fluctuations.

[0003] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a delayed power-down control circuit, a memory chip and a reset method thereof, to solve the problem of false reset caused by power supply jitter in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a time-delay power-down control circuit, applicable to memory chips, comprising:

[0006] The delayed power-down module receives an initial reset signal and performs a delay operation on the initial reset signal to generate a delayed reset signal;

[0007] The power-down control module receives the initial reset signal and the delayed reset signal, and generates a chip reset signal based on the initial reset signal and the delayed reset signal.

[0008] Optionally, the delayed power-down module is implemented using a D flip-flop.

[0009] Optionally, the delayed power-down module includes N D flip-flops, where N is a natural number greater than 1; wherein, the clock terminals of all N D flip-flops are connected to a clock signal, the output terminal of the preceding D flip-flop is connected to the data terminal of the following D flip-flop, the data terminal of the first D flip-flop receives the initial reset signal, and the output terminal of the Nth D flip-flop outputs the delayed reset signal.

[0010] Optionally, N can be greater than or equal to 10 and less than or equal to 20.

[0011] Optionally, the power-down control module performs logical operations on the initial reset signal and the delayed reset signal to generate a valid chip reset signal when both the initial reset signal and the delayed reset signal are valid.

[0012] Optionally, the initial reset signal, the delayed reset signal, and the chip reset signal are all active low, and the power-down control module is implemented using an OR gate.

[0013] The present invention also provides a memory chip, comprising:

[0014] The power-down detection circuit monitors the power supply voltage in real time after the memory chip is powered on, and generates an initial reset signal based on the comparison result between the power supply voltage value and the power-down detection threshold.

[0015] The delayed power-down control circuit described in any of the above is connected to the power-down detection circuit; the control logic circuit is connected to both the power-down detection circuit and the delayed power-down control circuit, and performs a true reset based on the initial reset signal and the chip reset signal, and executes a reset operation when the true reset is determined.

[0016] Optionally, it also includes a clock circuit connected to the delay power-down control circuit to provide a clock signal.

[0017] Optionally, it also includes a power supply circuit connected to the power failure detection circuit for outputting a power supply voltage.

[0018] The present invention also provides a method for resetting a memory chip as described in any one of the above claims, comprising:

[0019] The memory chip is powered on;

[0020] Determine whether the initial reset signal is valid;

[0021] If the initial reset signal is invalid, the memory chip will work normally; if the initial reset signal is valid, the determination of whether the chip reset signal is valid will continue.

[0022] If the chip reset signal is invalid, it is determined to be a false reset, and the memory chip will work normally. If the chip reset signal is valid, it is determined to be a true reset, and the memory chip will be reset.

[0023] As described above, the delayed power-down control circuit, memory chip, and reset method of the present invention, through the design of the delayed power-down module and the power-down control module, combine the initial reset signal and the chip reset signal to judge the true and false resets and trigger the chip reset when a true reset occurs. This can effectively eliminate the false reset caused by the power supply being too low due to transient voltage, which is beneficial to improving the reliability of the memory chip. Attached Figure Description

[0024] Figure 1 The diagram shown is a schematic diagram of the delayed power-down control circuit in Embodiment 1 of the present invention.

[0025] Figure 2 The diagram shown is a schematic diagram of the memory chip structure in Embodiment 2 of the present invention.

[0026] Figure 3 The flowchart shown is a memory chip reset method in Embodiment 2 of the present invention.

[0027] Figure 4 The diagram shows the waveforms of the relevant signals of the memory chip in Embodiment 2 of the present invention.

[0028] Component designation explanation

[0029] 100 memory chips

[0030] 110 Delayed Power-Off Control Circuit

[0031] 111 Delayed Power-Off Module

[0032] 112 Power-off control module

[0033] 120 Power Failure Detection Circuit

[0034] 121 Sampling Module

[0035] 122 Comparison Module

[0036] 130 Control Logic Circuit

[0037] 140 Clock Circuit

[0038] 150 power supply circuit Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please see Figures 1 to 4It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0041] Example 1

[0042] like Figure 1 As shown, this embodiment provides a delayed power-down control circuit 110, including a delayed power-down module 111 and a power-down control module 112. The delayed power-down control circuit 110 of this embodiment is applicable to the memory chip 100 and can effectively eliminate the false reset caused by the power supply being too low due to transient voltage, which is beneficial to improving the reliability of the memory chip 100.

[0043] The delayed power-down module 111 receives the initial reset signal POR_RST and performs a delay operation on the initial reset signal POR_RST to generate the delayed reset signal POR_RST_DLY.

[0044] In one example, the delayed power-down module 111 is implemented using D flip-flops. Of course, other module structures capable of signal delay are also feasible and are not limited thereto. In one specific implementation, the delayed power-down module 111 includes N D flip-flops, where N is a natural number greater than 1. The clock inputs of all N D flip-flops are connected to the clock signal CLK. The output of the preceding D flip-flop is connected to the data input of the following D flip-flop. The data input of the first D flip-flop receives the initial reset signal POR_RST, and the output of the Nth D flip-flop outputs the delayed reset signal POR_RST_DLY. Taking N=3 as an example, the clock input CK of the first D flip-flop is connected to the clock signal CLK, the data input D of the first D flip-flop receives the initial reset signal POR_RST, the output Q of the first D flip-flop is connected to the data input D of the second D flip-flop, the clock input CK of the second D flip-flop is connected to the clock signal CLK, the output Q of the second D flip-flop is connected to the data input D of the third D flip-flop, the clock input CK of the third D flip-flop is connected to the clock signal CLK, and the output Q of the third D flip-flop outputs the delayed reset signal POR_RST_DLY. It should be noted that the clock signal CLK is usually provided by the clock circuit 140 inside the memory chip 100.

[0045] In practice, a false reset will trigger the initial reset signal POR_RST to be active, but the active time of POR_RST will not be very long, usually within 600ns. Therefore, when delaying the initial reset signal POR_RST, the delay time should be greater than 600ns, typically designed to be greater than 1μs, to avoid overlap between the active levels of the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY in the event of a false reset. In application, the delay time is designed by setting the value of N, which is typically greater than or equal to 10 and less than or equal to 20, i.e., 10≤N≤20. The initial reset signal POR_RST is active low, meaning its active level is low; the delayed reset signal POR_RST_DLY is also active low, meaning its active level is also low.

[0046] The power-down control module 112 receives the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY, and generates the chip reset signal CHIP_RST based on the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY.

[0047] In one example, the power-down control module 112 performs a logical operation (e.g., a logical OR operation) on the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY to generate a valid chip reset signal CHIP_RST when both the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY are valid. Since both the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY are active low, and the chip reset signal CHIP_RST is also active low, a low-level chip reset signal CHIP_RST is generated when both the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY are low. In one specific implementation, the power-down control module 112 is implemented using an OR gate, wherein the first input of the OR gate receives the initial reset signal POR_RST, the second input of the OR gate receives the delayed reset signal POR_RST_DLY, and the output of the OR gate outputs the chip reset signal CHIP_RST; of course, other module structures that can implement logical OR operation functions (e.g., combinational logic gate structures) are also feasible and are not limited thereto.

[0048] Example 2

[0049] like Figure 2As shown, this embodiment provides a memory chip 100 (e.g., a NOR FLASH chip), including a delay power-down control circuit 110, a power-down detection circuit 120, and a control logic circuit 130; further, it also includes at least one of a clock circuit 140 and a power supply circuit 150.

[0050] The power-down detection circuit 120 monitors the power supply voltage in real time after the memory chip 100 is powered on, and generates an initial reset signal POR_RST based on the comparison result between the power supply voltage value and the power-down detection threshold. In one example, the power-down detection circuit 120 includes a sampling module 121 and a comparison module 122; wherein, the sampling module 121 samples the power supply voltage value and obtains a sampled value; the comparison module 122 is connected to the sampling module 121, compares the sampled value with the power-down detection threshold, and generates a valid initial reset signal POR_RST when the sampled value is less than the power-down detection threshold. In one specific embodiment, the sampling module 121 is implemented using a sampling resistor; of course, other module structures capable of voltage sampling are also feasible and are not limited thereto; the comparison module 122 is implemented using a comparator, wherein the non-inverting input of the comparator receives the sampled value, the inverting input of the comparator receives the power-down detection threshold, and the output of the comparator outputs the initial reset signal POR_RST.

[0051] The delayed power-down control circuit 110, connected to the power-down detection circuit 120, performs a delay operation on the initial reset signal POR_RST to generate a delayed reset signal POR_RST_DLY, and generates a chip reset signal CHIP_RST based on the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY. The delayed power-down control circuit 110 is implemented using the circuit structure described in Embodiment 1, the relevant details of which are described above and will not be repeated here.

[0052] The control logic circuit 130 is connected to the power-down detection circuit 120 and the delayed power-down control circuit 110, respectively. It determines whether a true reset is needed based on the initial reset signal POR_RST and the chip reset signal CHIP_RST, and performs a reset operation when a true reset is determined, thereby completing the reset of the memory chip 100. In fact, during normal operation, the control logic circuit 130 outputs logic control signals required for the operation of other circuits (e.g., the memory circuit). After reset, it no longer outputs relevant logic control signals or outputs invalid relevant logic control signals, thus completing the reset of the memory chip 100.

[0053] Clock circuit 140, connected to delay-power-down control circuit 110, provides clock signal CLK as the sampling clock for the D flip-flop in delay-power-down module 111 of delay-power-down control circuit 110. In application, clock circuit 140 can be implemented using any known clock generation circuit, without limitation.

[0054] The power supply circuit 150, connected to the power-down detection circuit 120, is used to output a power supply voltage. In one example, the power supply circuit 150 receives an external power supply voltage and processes the external power supply voltage (e.g., filtering, level conversion, etc.) to generate a power supply voltage; furthermore, the power supply circuit 150 also generates at least one internal power supply voltage based on the power supply voltage to power other circuits in the memory chip 100.

[0055] Of course, the memory chip 100 may also include a storage circuit (not shown in the figure) connected to the control logic circuit 130, which performs write, read and erase operations on data based on relevant logic control signals.

[0056] Correspondingly, such as Figure 3 As shown, this embodiment also provides a reset method for a memory chip 100, including the following steps; wherein the memory chip 100 is implemented using the structure described above.

[0057] Step S1: Power on memory chip 100. Powering on memory chip 100 is well known to those skilled in the art, and therefore will not be described in detail.

[0058] Step S2: Determine whether the initial reset signal POR_RST is valid, that is, determine whether the initial reset signal POR_RST is low.

[0059] If the initial reset signal POR_RST is invalid, that is, the initial reset signal POR_RST is high, it means that the power supply voltage is maintained above the power failure detection threshold. At this time, no reset occurs, and the memory chip 100 works normally.

[0060] If the initial reset signal POR_RST is valid, that is, the initial reset signal POR_RST is low, it means that the power supply voltage is less than the power failure detection threshold. At this time, a reset has occurred, and the process jumps to step S3.

[0061] In this step, the initial reset signal POR_RST is obtained through the power-down detection circuit 120, and the validity of the initial reset signal POR_RST is determined by the control logic circuit 130.

[0062] Step S3: Continue to determine whether the chip reset signal CHIP_RST is valid, that is, determine whether the chip reset signal CHIP_RST is low, so as to determine whether the above reset is an erroneous reset.

[0063] If the chip reset signal CHIP_RST is invalid, that is, the chip reset signal CHIP_RST is high, it means that the reset that makes the initial reset signal POR_RST low is a false reset (usually caused by a sudden drop in power supply voltage). In this case, the above reset is judged as a false reset, and the memory chip 100 works normally.

[0064] If the chip reset signal CHIP_RST is valid, that is, the chip reset signal CHIP_RST is low, it means that the reset that makes the initial reset signal POR_RST low is a true reset rather than a false reset. At this time, the above reset is determined to be a true reset, and a reset operation is performed on the memory chip 100; in fact, a reset operation is performed on the control logic circuit 130, thereby realizing the reset of the memory chip 100.

[0065] In this step, the chip reset signal CHIP_RST is obtained through the delayed power-down control circuit 110, and the chip reset signal CHIP_RST is determined to be valid through the control logic circuit 130.

[0066] Below, please combine Figure 4 The process of applying the delayed power-down control circuit 110 to the memory chip 100 and eliminating false resets is explained.

[0067] The memory chip 100 requires a power supply voltage of 3.3V to operate normally. During operation, such as writing, reading, or erasing data, the power supply voltage fluctuates to 1.6V, but quickly returns to 3.3V. Figure 4 It can be clearly seen that by combining the initial reset signal POR_RST and the chip reset signal CHIP_RST to trigger the reset, the false reset caused by power supply voltage jitter can be effectively filtered out, and the reset can still be performed normally even when the power supply voltage is continuously low.

[0068] In summary, the delayed power-down control circuit, memory chip, and reset method of the present invention, through the design of the delayed power-down module and the power-down control module, combine the initial reset signal and the chip reset signal to determine whether a reset is true or false, and trigger the chip reset when a true reset occurs. This effectively eliminates false resets caused by transient low power supply voltage, thus improving the reliability of the memory chip. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A memory chip, characterized in that, include: The power-down detection circuit monitors the power supply voltage in real time after the memory chip is powered on, and generates an initial reset signal based on the comparison result between the power supply voltage value and the power-down detection threshold. A delayed power-down control circuit is connected to the power-down detection circuit; wherein, the delayed power-down control circuit includes: The delayed power-down module receives an initial reset signal and performs a delay operation on the initial reset signal to generate a delayed reset signal; The power-down control module receives the initial reset signal and the delayed reset signal, and generates a chip reset signal based on the initial reset signal and the delayed reset signal; The control logic circuit is connected to the power-down detection circuit and the delayed power-down control circuit respectively. It determines whether a true reset is possible based on the initial reset signal and the chip reset signal, and performs a reset operation when the determination is a true reset.

2. The memory chip according to claim 1, characterized in that, The delayed power-down module is implemented using a D flip-flop.

3. The memory chip according to claim 2, characterized in that, The delayed power-down module includes N D flip-flops, where N is a natural number greater than 1; wherein, the clock terminals of all N D flip-flops are connected to a clock signal, the output terminal of the previous D flip-flop is connected to the data terminal of the next D flip-flop, the data terminal of the first D flip-flop receives the initial reset signal, and the output terminal of the Nth D flip-flop outputs the delayed reset signal.

4. The memory chip according to claim 3, characterized in that, The value of N is greater than or equal to 10 and less than or equal to 20.

5. The memory chip according to claim 1, characterized in that, The power-down control module performs logical operations on the initial reset signal and the delayed reset signal to generate a valid chip reset signal when both the initial reset signal and the delayed reset signal are valid.

6. The memory chip according to claim 5, characterized in that, The initial reset signal, the delayed reset signal, and the chip reset signal are all active low, and the power-down control module is implemented using an OR gate.

7. The memory chip according to claim 1, characterized in that, It also includes a clock circuit, which is connected to the delay power-down control circuit, for providing a clock signal.

8. The memory chip according to claim 1 or 7, characterized in that, It also includes a power supply circuit, which is connected to the power failure detection circuit and is used to output the power supply voltage.

9. A method for resetting a memory chip as described in any one of claims 1 to 8, characterized in that, include: The memory chip is powered on; Determine whether the initial reset signal is valid; If the initial reset signal is invalid, the memory chip will work normally; if the initial reset signal is valid, the determination of whether the chip reset signal is valid will continue. If the chip reset signal is invalid, it is determined to be a false reset, and the memory chip will work normally. If the chip reset signal is valid, it is determined to be a true reset, and the memory chip will be reset.

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