Output latch circuit for sensitive amplifier

Abstract

The invention relates to an output latch circuit for a sensitive amplifier, which comprises a first output latch circuit module and a second output latch circuit module, and the output end DOB1 of the first output latch circuit module is connected with the output end DOB2 of the second output latch circuit module. The first output latch circuit module is respectively connected with the sensitive amplifier SA1 and the sensitive amplifier SA2, and the second output latch circuit module is respectively connected with the sensitive amplifier SA1 and the sensitive amplifier SA2. According to the output latch circuit for the sensitive amplifier, the overall performance, the reliability and the integration degree of a memory can be remarkably improved, and the requirements of modern high-performance and low-power-consumption memories are met.

Description

Technical Field

[0001] The present invention relates to the technical field of output latch circuits, and particularly to an output latch circuit for a sense amplifier. Background Art

[0002] Sense amplifiers play a crucial role in modern memories (such as SRAMs and DRAMs). Its main function is to amplify the weak signal in the memory cell to a level that can be processed by subsequent circuits. However, there are many challenges in aspects such as the stability, power consumption, speed, and adaptability of the output signal of the sense amplifier. To address these challenges, a latch circuit is introduced to enhance the performance of the sense amplifier. The latch circuit can stabilize and hold the output signal of the sense amplifier, improving the accuracy and reliability of data reading. The latch circuit schemes applied to sense amplifiers in the prior art include the following several types: First, basic latch circuit The basic latch circuit is usually composed of two cross-coupled inverters to form a bistable circuit. This structure is simple, but it may be difficult to provide sufficient signal stability and speed when dealing with high-speed and high-density memories.

[0003] Second, enhanced latch circuit To improve the performance of the latch circuit, an enhanced design is an improvement based on the basic latch circuit. For example, a precharge circuit is added to accelerate the latching process, or low-threshold voltage transistors are used to reduce power consumption. These improvements enhance the signal stability and speed, but the complex circuit structure may lead to an increase in area and design complexity.

[0004] Third, power noise suppression latch circuit In the design of high-density memories, the impact of power noise on the latch circuit is particularly significant. Therefore, a latch circuit with power noise suppression function is designed. For example, decoupling capacitors or filters are added between the power supply and the ground to reduce noise interference. These measures improve the noise immunity of the latch circuit, but also increase the circuit complexity and power consumption.

[0005] Fourth, dynamic latch circuit The dynamic latch circuit adapts to different operating states by dynamically adjusting circuit parameters. For example, by adjusting the operating voltage and current, efficient signal latching and power management are achieved. The dynamic latch circuit performs well in terms of speed and power consumption, but its adaptability to process variations is poor, which may lead to inconsistent performance under different manufacturing conditions.

[0006] Fifth, differential latch circuit The differential latch circuit improves the anti-interference ability by using differential input signals. The differential design can effectively suppress common-mode noise, improve signal stability and reading accuracy. However, the design complexity of the differential circuit is relatively high, and the chip area occupied is relatively large, which is not conducive to high-density integration.

[0007] Sixth, current-mode latch circuit The current-mode latch circuit operates through current signals instead of traditional voltage signals. This design can provide higher stability and speed in high-speed operations, but the power consumption of the current-mode circuit is relatively high, and the requirements for power supply design are relatively high.

[0008] Therefore, however, with the continuous progress of process technology and the increase in memory density, the traditional sense amplifier and output latch circuit can no longer meet the new requirements in some aspects, and it is necessary to re-design the sense amplifier and output latch circuit to solve the technical problems such as poor stability, high power consumption, and slow speed existing in the current output latch circuit design. Summary of the Invention

[0009] For this reason, the technical problem to be solved by the present invention is to overcome the technical problems such as poor stability, high power consumption, and slow speed existing in the output latch circuit in the prior art.

[0010] To solve the above technical problems, the present invention provides an output latch circuit for a sense amplifier, including a first output latch circuit module and a second output latch circuit module. The output end DOB1 of the first output latch circuit module is connected to the output end DOB2 of the second output latch circuit module. The first output latch circuit module is respectively connected to the sense amplifier SA1 and the sense amplifier SA2, and the second output latch circuit module is respectively connected to the sense amplifier SA1 and the sense amplifier SA2; The first output latch circuit module includes transistors P10, P11, P12, P13, P14, P15, N10, N11, N12, N13, N14, and N15; The source of the transistor P15 is connected to the power supply VDD. The node GDB2 of the gate of the transistor P15 is connected to the sense amplifier SA2. The drain of the transistor P15 is connected to the source of the transistor P10. The gate of the transistor P10 includes a first branch and a second branch. The first branch of the gate of the transistor P10 is connected to the gate of the transistor P11. The second branch of the gate of the transistor P10 is connected to the node GDB1 after being connected to the gate of the transistor N14 and then connected to the sense amplifier SA1. The drain of the transistor P10 and the source of the transistor P11 are connected. The drain of the transistor P11 and the source of the transistor P12 are connected. The drain of the transistor P12 includes a first branch, a second branch, and a third branch. The first branch of the drain of the transistor P12 is the output terminal DOB1. The second branch of the drain of the transistor P12 is respectively connected to the gate of the transistor P12, the drain of the transistor P13, the drain of the transistor P14, and the drain of the transistor N14. The third branch of the drain of the transistor P12 is connected to the drain of the transistor N12. The gate of the transistor P12 is also connected to the gate of the transistor N12. The source of the transistor N12 is connected to the drain of the transistor N11. The gate of the transistor N11 includes a first branch and a second branch. The first branch of the gate of the transistor N11 is connected to the gate of the transistor N10. The second branch of the gate of the transistor N11 is connected to the node GD01 after being connected to the gate of the transistor P14 and then connected to the sense amplifier SA1. The source of the transistor N10 and the drain of the transistor N15 are connected. The node GD02 of the gate of the transistor N15 is connected to the sense amplifier SA2. The source of the transistor N15 is connected to the ground wire VSS; The source of the transistor P13 is connected to the power supply VDD. The node DOPD after the gate of the transistor P13 is connected to the gate of the transistor N13 is used to control the operation or sleep of the first output latch circuit module. The source of the transistor N13 is connected to the ground wire VSS. The drain of the transistor N13 is connected to the source of the transistor N14. The source of the transistor P14 is connected to the power supply VDD; The second output latch circuit module includes transistors P20, P21, P22, P23, P24, P25, N20, N21, N22, N23, N24, and N25; The source of the transistor P25 is connected to the power supply VDD. The node GDB1 of the gate of the transistor P25 is connected to the sense amplifier SA1. The drain of the transistor P25 is connected to the source of the transistor P20. The gate of the transistor P20 includes a first branch and a second branch. The first branch of the gate of the transistor P20 is connected to the gate of the transistor P21. The second branch of the gate of the transistor P20 is connected to the gate of the transistor N24, and the resulting node GDB2 is then connected to the sense amplifier SA2. The drain of the transistor P20 and the source of the transistor P21 are connected. The drain of the transistor P21 and the source of the transistor P22 are connected. The drain of the transistor P22 includes a first branch, a second branch, and a third branch. The first branch of the drain of the transistor P22 is the output terminal DOB2, and the output terminal DOB2 is connected to the output terminal DOB1. The second branch of the drain of the transistor P22 is respectively connected to the gate of the transistor P22, the drain of the transistor P23, the drain of the transistor P24, and the drain of the transistor N24. The third branch of the drain of the transistor P22 is connected to the drain of the transistor N22. The gate of the transistor P22 is also connected to the gate of the transistor N22. The source of the transistor N22 is connected to the drain of the transistor N21. The gate of the transistor N21 includes a first branch and a second branch. The first branch of the gate of the transistor N21 is connected to the gate of the transistor N20. The second branch of the gate of the transistor N21 is connected to the gate of the transistor P24, and the resulting node GD02 is then connected to the sense amplifier SA2. The source of the transistor N20 and the drain of the transistor N25 are connected. The node GD01 of the gate of the transistor N25 is connected to the sense amplifier SA1. The source of the transistor N25 is connected to the ground wire VSS; The source of the transistor P23 is connected to the power supply VDD. The node DOPD, which is the connection of the gate of the transistor P23 and the gate of the transistor N23, is used to control the operation or sleep of the second output latch circuit module. The source of the transistor N23 is connected to the ground wire VSS. The drain of the transistor N23 is connected to the source of the transistor N24. The source of the transistor P24 is connected to the power supply VDD.

[0011] In an embodiment of the present invention, the second branch of the gate of the transistor P10 is connected to the gate of the transistor N14 and then connected to the output terminal of the inverter INV10. The input terminal of the inverter INV10 is connected to the node GDB1.

[0012] In an embodiment of the present invention, the second branch of the gate of the transistor P20 is connected to the gate of the transistor N24 and then connected to the output terminal of the inverter INV20, and the input terminal of the inverter INV20 is connected to the node GDB2.

[0013] In an embodiment of the present invention, the second branch of the drain of the transistor P12 is connected to the gate of the transistor P12 through the inverter INV11.

[0014] In an embodiment of the present invention, the second branch of the drain of the transistor P22 is connected to the gate of the transistor P22 through the inverter INV21.

[0015] In an embodiment of the present invention, the node GDB1 of the gate of the transistor P25, after passing through the first inverter of the sense amplifier SA1, is then connected to the node DL of the sense amplifier SA1; The node GDB1 after the second branch of the gate of the transistor P10 is connected to the gate of the transistor N14, after passing through the first inverter of the sense amplifier SA1, is then connected to the node DL of the sense amplifier SA1; The node GD01 after the second branch of the gate of the transistor N11 is connected to the gate of the transistor P14, after passing through the second inverter of the sense amplifier SA1, is then connected to the node DLB of the sense amplifier SA1; The node GD01 of the gate of the transistor N25, after passing through the second inverter of the sense amplifier SA1, is then connected to the node DLB of the sense amplifier SA1; Wherein, the node DL of the sense amplifier SA1 is the first data storage node of the sense amplifier SA1, and the node DLB of the sense amplifier SA1 is the second data storage node of the sense amplifier SA1.

[0016] In an embodiment of the present invention, the node GDB2 of the gate of the transistor P15, after passing through the first inverter of the sense amplifier SA2, is then connected to the node DL of the sense amplifier SA2; The node GDB2 after the second branch of the gate of the transistor P20 is connected to the gate of the transistor N24, after passing through the first inverter of the sense amplifier SA2, is then connected to the node DL of the sense amplifier SA1; The node GD02 after the second branch of the gate of the transistor N21 is connected to the gate of the transistor P24, after passing through the second inverter of the sense amplifier SA2, is then connected to the node DLB of the sense amplifier SA2; The node GD02 of the gate of the transistor N15 is connected to the node DLB of the sense amplifier SA2 after passing through the second inverter of the sense amplifier SA2; Among them, the node DL of the sense amplifier SA2 is the first data storage node of the sense amplifier SA2, and the node DLB of the sense amplifier SA2 is the second data storage node of the sense amplifier SA2.

[0017] In an embodiment of the present invention, the transistors P10, P11, P12, P13, P14, P15, P20, P21, P22, P23, P24, and P25 are all P-type field effect transistors.

[0018] In an embodiment of the present invention, the transistors N10, N11, N12, N13, N14, N15, N20, N21, N22, N23, N24, and N25 are all N-type field effect transistors.

[0019] The above technical solutions of the present invention have the following advantages compared with the prior art: The output latch circuit for the sense amplifier according to the present invention avoids the direct current path by reasonably designing and controlling the on and off states of the transistors, ensures signal stability, realizes high-speed and low-power operation, and enhances the anti-interference ability and reliability; The present invention can reduce power consumption: by controlling the on and off states of the transistors, the direct current path from VDD to VSS is avoided, and unnecessary power consumption is significantly reduced. This is particularly important for low-power applications such as portable devices and Internet of Things devices, and can significantly extend the battery life and the working time of the devices; The present invention can improve energy efficiency: avoiding the direct current path not only reduces power consumption, but also improves the overall energy efficiency of the circuit, making it suitable for high-energy efficiency application scenarios; The present invention can prevent misreading: after the read operation is completed, through appropriate transistor control, the level states of internal nodes (such as DL, DLB, GDO, GDB, etc.) are ensured to be stable, preventing misreading and misoperation; The present invention can enhance reliability: the stability of the signal directly improves the accuracy of data reading and the reliability of the circuit, especially under high-speed and high-density operation conditions; The present invention can respond quickly: through the pre-charging and the fast response mechanism of the sense amplifier, high-speed read and write operations are realized, ensuring the accuracy and stability of the signal during the operation switching process. Description of the Drawings

[0020] In order to make the content of the present invention easier to be clearly understood, the following further details the present invention in accordance with specific embodiments of the present invention and in conjunction with the accompanying drawings.

[0021] Figure 1 It is the output latch circuit diagram for the sense amplifier in the embodiment of the present invention; Figure 2 It is the circuit diagram of the sense amplifier SA1 in the embodiment of the present invention; Figure 3 It is the circuit diagram of the sense amplifier SA2 in the embodiment of the present invention. Specific Embodiments

[0022] The following further describes the present invention in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments cited are not intended to limit the present invention. Embodiment

[0023] Referring to Figure 1 As shown, the present invention relates to an output latch circuit for a sense amplifier, including a first output latch circuit module and a second output latch circuit module. The output terminal DOB1 of the first output latch circuit module is connected to the output terminal DOB2 of the second output latch circuit module. The first output latch circuit module is respectively connected to the sense amplifier SA1 and the sense amplifier SA2, and the second output latch circuit module is respectively connected to the sense amplifier SA1 and the sense amplifier SA2; The first output latch circuit module includes transistors P10, P11, P12, P13, P14, P15, N10, N11, N12, N13, N14, and N15; The source of the transistor P15 is connected to the power supply VDD. The node GDB2 (serving as an input node) of the gate of the transistor P15 is connected to the sense amplifier SA2. The drain of the transistor P15 is connected to the source of the transistor P10. The gate of the transistor P10 includes a first branch and a second branch. The first branch of the gate of the transistor P10 is connected to the gate of the transistor P11. The node GDB1 (serving as an input node) after the second branch of the gate of the transistor P10 is connected to the gate of the transistor N14 is then connected to the sense amplifier SA1. The drain of the transistor P10 and the source of the transistor P11 are connected. The drain of the transistor P11 and the source of the transistor P12 are connected. The drain of the transistor P12 includes a first branch, a second branch, and a third branch. The first branch of the drain of the transistor P12 is the output terminal DOB1. The second branch of the drain of the transistor P12 is respectively connected to the gate of the transistor P12, the drain of the transistor P13, the drain of the transistor P14, and the drain of the transistor N14. The third branch of the drain of the transistor P12 is connected to the drain of the transistor N12. The gate of the transistor P12 is also connected to the gate of the transistor N12. The source of the transistor N12 is connected to the drain of the transistor N11. The gate of the transistor N11 includes a first branch and a second branch. The first branch of the gate of the transistor N11 is connected to the gate of the transistor N10. The node GD01 after the second branch of the gate of the transistor N11 is connected to the gate of the transistor P14 is then connected to the sense amplifier SA1. The source of the transistor N10 and the drain of the transistor N15 are connected. The node GD02 of the gate of the transistor N15 is connected to the sense amplifier SA2. The source of the transistor N15 is connected to the ground wire VSS; The source of the transistor P13 is connected to the power supply VDD. The node DOPD after the gate of the transistor P13 is connected to the gate of the transistor N13 is used to control the operation or dormancy of the first output latch circuit module. The source of the transistor N13 is connected to the ground wire VSS. The drain of the transistor N13 is connected to the source of the transistor N14. The source of the transistor P14 is connected to the power supply VDD; The second output latch circuit module includes transistors P20, P21, P22, P23, P24, P25, N20, N21, N22, N23, N24, and N25; The source of the transistor P25 is connected to the power supply VDD. The node GDB1 of the gate of the transistor P25 is connected to the sense amplifier SA1. The drain of the transistor P25 is connected to the source of the transistor P20. The gate of the transistor P20 includes a first branch and a second branch. The first branch of the gate of the transistor P20 is connected to the gate of the transistor P21. The second branch of the gate of the transistor P20 is connected to the gate of the transistor N24, and the resulting node GDB2 is then connected to the sense amplifier SA2. The drain of the transistor P20 and the source of the transistor P21 are connected. The drain of the transistor P21 and the source of the transistor P22 are connected. The drain of the transistor P22 includes a first branch, a second branch, and a third branch. The first branch of the drain of the transistor P22 is the output terminal DOB2. The output terminal DOB2 and the output terminal DOB1 are connected and share a common output terminal DOB. The second branch of the drain of the transistor P22 is respectively connected to the gate of the transistor P22, the drain of the transistor P23, the drain of the transistor P24, and the drain of the transistor N24. The third branch of the drain of the transistor P22 is connected to the drain of the transistor N22. The gate of the transistor P22 is also connected to the gate of the transistor N22. The source of the transistor N22 is connected to the drain of the transistor N21. The gate of the transistor N21 includes a first branch and a second branch. The first branch of the gate of the transistor N21 is connected to the gate of the transistor N20. The second branch of the gate of the transistor N21 is connected to the gate of the transistor P24, and the resulting node GD02 is then connected to the sense amplifier SA2. The source of the transistor N20 and the drain of the transistor N25 are connected. The node GD01 of the gate of the transistor N25 is connected to the sense amplifier SA1. The source of the transistor N25 is connected to the ground wire VSS; The source of the transistor P23 is connected to the power supply VDD. The node DOPD, which is the connection of the gate of the transistor P23 and the gate of the transistor N23, is used to control the operation or sleep of the second output latch circuit module. The source of the transistor N23 is connected to the ground wire VSS. The drain of the transistor N23 is connected to the source of the transistor N24. The source of the transistor P24 is connected to the power supply VDD.

[0024] Further, the second branch of the gate of the transistor P10 is connected to the gate of the transistor N14 and then connected to the output terminal of the inverter INV10. The input terminal of the inverter INV10 is connected to the node GDB1.

[0025] Furthermore, the second branch of the gate of the transistor P20 is connected to the gate of the transistor N24 and then connected to the output end of the inverter INV20, and the input end of the inverter INV20 is connected to the node GDB2.

[0026] Furthermore, the second branch of the drain of the transistor P12 is connected to the gate of the transistor P12 through the inverter INV11, the second branch of the source of the transistor P12 is connected to the input of the inverter INV11, and the output of the inverter INV11 is connected to the gate of the transistor P12.

[0027] Furthermore, the second branch of the drain of the transistor P22 is connected to the gate of the transistor P22 through the inverter INV21, the second branch of the source of the transistor P22 is connected to the input of the inverter INV21, and the output of the inverter INV21 is connected to the gate of the transistor P22.

[0028] Furthermore, the node GDB1 of the gate of the transistor P25 passes through the first inverter (i.e. Figure 2 After INV12 in the circuit, it is connected to the node DL of the sense amplifier SA1; The node GDB1 where the second branch of the gate of the transistor P10 is connected to the gate of the transistor N14 passes through the first inverter of the sense amplifier SA1 and is then connected to the node DL of the sense amplifier SA1; The node GD01 where the second branch of the gate of the transistor N11 is connected to the gate of the transistor P14 passes through the second inverter of the sense amplifier SA1 and then is connected to the node DLB of the sense amplifier SA1; The node GD01 of the gate of the transistor N25 is connected to the sense amplifier SA1 through the second inverter (i.e. Figure 2 After INV13 in the circuit, it is connected to the node DLB of the sense amplifier SA1; The node DL of the sense amplifier SA1 is a first data storage node of the sense amplifier SA1 , and the node DLB of the sense amplifier SA1 is a second data storage node of the sense amplifier SA1 .

[0029] Further, the node GDB2 of the gate of the transistor P15 passes through the first inverter (i.e. Figure 3 After INV22 in the circuit, it is connected to the node DL of the sense amplifier SA2; The node GDB2 where the second branch of the gate of the transistor P20 is connected to the gate of the transistor N24 passes through the first inverter of the sense amplifier SA2 and is then connected to the node DL of the sense amplifier SA1; The node GD02 after the second branch of the gate of the transistor N21 is connected to the gate of the transistor P24 passes through the second inverter of the sense amplifier SA2 (i.e., Figure 3 INV23 in ), and then is connected to the node DLB of the sense amplifier SA2; Among them, the node DL of the sense amplifier SA2 is the first data storage node of the sense amplifier SA2, and the node DLB of the sense amplifier SA2 is the second data storage node of the sense amplifier SA2.

[0030] Further, the transistors P10, P11, P12, P13, P14, P15, P20, P21, P22, P23, P24, and P25 are all P-type field effect transistors.

[0031] Further, the transistors N10, N11, N12, N13, N14, N15, N20, N21, N22, N23, N24, and N25 are all N-type field effect transistors.

[0032] The working principle of this embodiment is as follows: As follows Figure 1 As shown, when two sense amplifiers SA1 and SA2 share an output DOB, assume that the nodes DL and DLB of the sense amplifier SA1 are connected to GDO1 and GDB1 through corresponding inverters respectively, and the nodes DL and DLB of the sense amplifier SA2 are connected to GDO2 and GDB2 through corresponding inverters respectively.

[0033] When the read 1 operation of sense amplifier SA2 ends and sense amplifier SA1 starts the read 0 operation. Since sense amplifier SA2 has performed the read 1 operation first, the DL of the internal node of sense amplifier SA2 is high level 1, DLB is low level 0, GDO2 is high level 1, GDB2 is low level 0, DOPD is high level 1. Then transistors P20, P21, P23, P24 are in the cut-off state, and transistors N20, N21, N23, N24 are in the conducting state. DOB2 is pulled down to low level 0 through N23 and N24. Due to the existence of inverter INV21, node DOX2 is pulled up to high level 1. Due to the existence of inverter INV11, node DOX1 is pulled up to high level 1. After connecting an inverter to DOB, a high level 1 can be read. After the read 1 operation of sense amplifier SA2 ends, the values of the two internal nodes DL and DLB of sense amplifier SA2 are both high level 1, and the values of GDO2 and GDB2 are also both high level 1. At this time, P24 and N24 are in the cut-off state, and transistors P20, P21, N20, N21 are in the conducting state. Since the value of DOX2 is high level 1 at this time, transistor P22 is in the cut-off state, and transistor N22 is in the conducting state. DOB2 is stabilized at low level 0 through transistors N20, N21, N22. When sense amplifier SA1 starts the read 0 operation, the DLB of the internal node of sense amplifier SA1 is high level 1, DL is low level 0, GDB1 is high level 1, GDO1 is low level 0, DOPD is high level 1. Then transistors P13, N10, N11, N14 are in the cut-off state, transistors P10, P11 are in the conducting state, and transistor P14 is in the conducting state to pull DOB1 up to high level 1. At the same time, since GDO1 is low level 0, transistor N25 is in the cut-off state, thus cutting off the path of DOB through transistors N20, N21, N22 to ground wire VSS. At this time, there is only one path of DOB through transistor P14 to power supply VDD, thus avoiding the appearance of a direct current path from power supply VDD to ground wire VSS.

[0034] When the read 0 operation of sense amplifier SA2 ends and sense amplifier SA1 starts the read 1 operation. Since sense amplifier SA2 has performed the read 0 operation first, the DLB of the internal node of sense amplifier SA2 is high level 1, DL is low level 0, GDB2 is high level 1, GDO2 is low level 0, DOPD is high level 1, then transistors P23, N24, N20, N21 are in the cut-off state, transistors P20, P21 are in the conducting state, transistor P24 is in the conducting state, DOB2 is pulled up to high level 1 through transistor P24. Due to the existence of inverter INV21, DOX2 is pulled down to low level 0. Due to the existence of inverter INV11, DOX1 is pulled down to low level 0. After connecting an inverter to DOB, the low level 0 can be read out. After the read 0 operation of sense amplifier SA2 ends, the values of the two internal nodes DL and DLB of sense amplifier SA2 are both high level 1, and the values of GDO2 and GDB2 are also both high level 1. At this time, transistors P24 and N24 are in the cut-off state, transistors P20, P21, N20, N21 are in the conducting state. Since the value of DOX2 is low level 0 at this time, transistor N22 is in the cut-off state, transistor P22 is in the conducting state, and DOB2 is stabilized at high level 1 through P20, P21, P22. When sense amplifier SA1 starts the read 1 operation, the DL of the internal node of sense amplifier SA1 is high level 1, DLB is low level 0, GDO1 is high level 1, GDB1 is low level 0, DOPD is high level 1, then transistors P10, P11, P13, P14 are in the cut-off state, transistors N10, N11 are in the conducting state, transistors N13, N14 are in the conducting state and pull DOB1 down to low level 0. At the same time, since GDB1 is low level 0, transistor P25 is in the cut-off state, thus cutting off the path of DOB through transistors P20, P21, P22 to power supply VDD. At this time, there is only one path of DOB through transistors N13, N14 to ground wire VSS, thus avoiding the occurrence of a direct current path from power supply VDD to ground wire VSS.

[0035] In the above logic, by cleverly designing the output signals GDB2 and GDO2 of the sense amplifier SA2 to control the output latch circuit of the sense amplifier SA1, this mechanism not only effectively isolates the potential interference of the sense amplifier SA2 on the output stability of the sense amplifier SA1 during the output latch operation, but also significantly reduces the delay that may be introduced due to waiting for the latch to complete, ensuring that the data of the sense amplifier SA1 remains unchanged during the read / write operation of the sense amplifier SA2, providing a strong guarantee for the continuity and stability of the entire data path. For high-performance systems, this improvement can significantly accelerate the flip speed of the DOB, thereby improving the overall data throughput rate and system response speed. Similarly, the precise control of the output GDB1 and GDO1 of the sense amplifier SA1 over the output latch circuit of the sense amplifier SA2 achieves two-way protection and optimization. It ensures that when the sense amplifier SA1 performs its output latch task, the output state of the sense amplifier SA2 will not have an adverse effect on it, further consolidating the stability and reliability of the data path.

[0036] It should be noted that both the sense amplifier SA1 and the sense amplifier SA2 in this embodiment are latch-type sense amplifiers. The following is a detailed introduction to the circuit structure of the sense amplifier SA1: Please refer to Figure 2 , the sense amplifier SA1 includes transistors PM11, PM12, PM13, PM14 (all P-type field-effect transistors), transistors NM11, NM12, NM13, NM14 (all N-type field-effect transistors), and inverters INV12 and INV13. Among them, transistors PM11, PM12, NM11, and NM12 form a latch unit. The main function of the latch unit is to lock the nodes DL and DLB of the sense amplifier SA1 in a fixed state. The latch unit is respectively connected to the drains of transistors PM13, PM14, and NM13. Transistors PM13 and PM14 are used to transfer the values of nodes RBL1 and RBLB1 to nodes DL and DLB respectively. Transistor NM13 serves as the enable transistor of the sense amplifier. Only when transistor NM13 works, the sense amplifier SA1 has the amplification function. The drain of transistor PM13 is connected to the latch unit to form node DL. Node DL forms node GDB1 after passing through inverter INV12. The drain of transistor PM14 is connected to the latch unit to form node DLB. Node DLB forms node GDO1 after passing through inverter INV13. The source input terminal of transistor PM13 is defined as node RBL1, and the source input terminal of transistor PM14 is defined as output node RBLB1. Both node RBL1 and node RBLB1 are used to receive the first set of signals to be amplified.

[0037] The circuit structure principle of the sense amplifier SA1 is as follows: Nodes RBL1 and RBLB1 are used to connect the first group of signals to be amplified. The initial states of nodes RBL1 and RBLB1 are both high-level signal 1, the initial state of SAEN is low-level signal 0, transistors PM13, PM14, NM11, and NM12 are turned on, and transistors NM13, PM11, and PM12 are turned off. The high-level signal of node RBL1 is transmitted through transistor PM13 to node DL of sense amplifier SA1, the high-level signal of node RBLB1 is transmitted through transistor PM14 to node DLB of sense amplifier SA1, the high-level signal of node DL is transmitted to GDB1 through inverter INV12, and the high-level signal of node DLB1 is transmitted to GDO1 through inverter INV13.

[0038] When the signal to be amplified is a low-level signal, node RBLB1 remains high, node RBL1 slowly decreases from high level, and node DL also slowly decreases from high level. As node DL slowly decreases, transistor PM12 gradually turns on. After transistor PM12 is fully turned on, SAEN is set to high level. At this time, transistors PM13, PM14, NM12, and PM11 are turned off, transistors PM12, NM11, and NM13 are turned on. Node DLB is maintained at high level through transistor PM12, node DL is quickly pulled down to a low-level signal through transistors NM11 and NM13. The high-level signal of node DLB is transmitted to GDO1 through inverter INV13, and the low-level signal of node DL is transmitted to GDB1 through inverter INV12, thus realizing the amplification of the low-level signal.

[0039] When the signal to be amplified is a high-level signal, node RBL1 remains high, node RBLB1 slowly decreases from high level, and node DLB also slowly decreases from high level. As node DLB slowly decreases, transistor PM11 gradually turns on. After transistor PM11 is fully turned on, SAEN is set to high level. At this time, transistors PM13, PM14, NM11, and PM12 are turned off, transistors PM11, NM12, and NM13 are turned on. Node DL is maintained at high level through transistor PM11, node DLB is quickly pulled down to a low-level signal through transistors NM12 and NM13. The high-level signal of node DL is transmitted to GDB1 through inverter INV12, and the low-level signal of node DLB1 is transmitted to GDO1 through inverter INV13, thus realizing the amplification of the high-level signal.

[0040] Since the structures and principles of sense amplifier SA2 and sense amplifier SA1 are the same, the purpose is to amplify the second group of signals from nodes RBL2 and RBLB2. For details, please refer to Figure 3 , which will not be elaborated in this embodiment.

[0041] In summary, the present invention cleverly controls the on and off states of the transistors between different read operations, effectively avoiding the appearance of a DC path from the power supply VDD to the ground line VSS. Specifically, by controlling the state of the transistors, the possible DC path is cut off after the read operation is completed, which not only reduces unnecessary power consumption, but also improves the energy efficiency of the circuit, meeting the needs of modern high-performance, low-power memory. These advantages make the circuit have broad prospects in practical applications, especially in memory systems that require high performance and reliability.

[0042] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0043] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. An output latch circuit for a sense amplifier, characterized in that: It includes a first output latch circuit module and a second output latch circuit module. The output terminal DOB1 of the first output latch circuit module is connected to the output terminal DOB2 of the second output latch circuit module. The first output latch circuit module is respectively connected to sense amplifiers SA1 and SA2, and the second output latch circuit module is respectively connected to sense amplifiers SA1 and SA2; The first output latch circuit module includes transistors P10, P11, P12, P13, P14, P15, N10, N11, N12, N13, N14, and N15; The source of transistor P15 is connected to the power supply VDD. The node GDB2 of the gate of transistor P15 is connected to sense amplifier SA2. The drain of transistor P15 is connected to the source of transistor P10. The gate of transistor P10 includes a first branch and a second branch. The first branch of the gate of transistor P10 is connected to the gate of transistor P11. The second branch of the gate of transistor P10 is connected to the gate of transistor N14, and then the node GDB1 is connected to sense amplifier SA1. The drain of transistor P10 is connected to the source of transistor P11. The drain of transistor P11 is connected to the source of transistor P12. The drain of transistor P12 includes a first branch, a second branch, and a third branch. The first branch of the drain of transistor P12 is the output terminal DOB1. The second branch of the drain of transistor P12 is respectively connected to the gate of transistor P12, the drain of transistor P13, the drain of transistor P14, and the drain of transistor N14. The third branch of the drain of transistor P12 is connected to the drain of transistor N12. The gate of transistor P12 is also connected to the gate of transistor N12. The source of transistor N12 is connected to the drain of transistor N11. The gate of transistor N11 includes a first branch and a second branch. The first branch of the gate of transistor N11 is connected to the gate of transistor N10. The second branch of the gate of transistor N11 is connected to the gate of transistor P14, and then the node GD01 is connected to sense amplifier SA1. The source of transistor N10 is connected to the drain of transistor N15. The node GD02 of the gate of transistor N15 is connected to sense amplifier SA2. The source of transistor N15 is connected to the ground wire VSS; The source of transistor P13 is connected to the power supply VDD. The node DOPD, which is the connection of the gate of transistor P13 and the gate of transistor N13, is used to control the operation or sleep of the first output latch circuit module. The source of transistor N13 is connected to the ground wire VSS. The drain of transistor N13 is connected to the source of transistor N14. The source of transistor P14 is connected to the power supply VDD; The second output latch circuit module includes transistors P20, P21, P22, P23, P24, P25, transistors N20, N21, N22, N23, N24, and transistor N25; The source of transistor P25 is connected to power supply VDD. The node GDB1 of the gate of transistor P25 is connected to sense amplifier SA1. The drain of transistor P25 is connected to the source of transistor P20. The gate of transistor P20 includes a first branch and a second branch. The first branch of the gate of transistor P20 is connected to the gate of transistor P21. The second branch of the gate of transistor P20 is connected to the gate of transistor N24, and the resulting node GDB2 is then connected to sense amplifier SA2. The drain of transistor P20 and the source of transistor P21 are connected. The drain of transistor P21 and the source of transistor P22 are connected. The drain of transistor P22 includes a first branch, a second branch, and a third branch. The first branch of the drain of transistor P22 is the output terminal DOB2. The output terminal DOB2 is connected to the output terminal DOB1. The second branch of the drain of transistor P22 is respectively connected to the gate of transistor P22, the drain of transistor P23, the drain of transistor P24, and the drain of transistor N24. The third branch of the drain of transistor P22 is connected to the drain of transistor N22. The gate of transistor P22 is also connected to the gate of transistor N22. The source of transistor N22 is connected to the drain of transistor N21. The gate of transistor N21 includes a first branch and a second branch. The first branch of the gate of transistor N21 is connected to the gate of transistor N20. The second branch of the gate of transistor N21 is connected to the gate of transistor P24, and the resulting node GD02 is then connected to sense amplifier SA2. The source of transistor N20 and the drain of transistor N25 are connected. The node GD01 of the gate of transistor N25 is connected to sense amplifier SA1. The source of transistor N25 is connected to ground wire VSS; The source of transistor P23 is connected to power supply VDD. The node DOPD, which is the connection of the gate of transistor P23 and the gate of transistor N23, is used to control the operation or sleep of the second output latch circuit module. The source of transistor N23 is connected to ground wire VSS. The drain of transistor N23 is connected to the source of transistor N24. The source of transistor P24 is connected to power supply VDD.

2. The output latch circuit for a sense amplifier according to claim 1, characterized in that: The second branch of the gate of transistor P10 is connected to the gate of transistor N14 and then connected to the output terminal of inverter INV10. The input terminal of inverter INV10 is connected to node GDB1.

3. The output latching circuit for a sense amplifier according to claim 1, wherein: The second branch of the gate of the transistor P20 is connected to the gate of the transistor N24 and then connected to the output terminal of the inverter INV20, and the input terminal of the inverter INV20 is connected to the node GDB2.

4. The output latch circuit for a sense amplifier according to claim 1, characterized in that: The second branch of the drain of the transistor P12 is connected to the gate of the transistor P12 through the inverter INV11.

5. The output latch circuit for a sense amplifier according to claim 1, wherein: The second branch of the drain of the transistor P22 is connected to the gate of the transistor P22 through the inverter INV21.

6. The output latch circuit for a sense amplifier according to claim 1, wherein: The node GDB1 of the gate of the transistor P25 is connected to the node DL of the sense amplifier SA1 after passing through the first inverter of the sense amplifier SA1; The node GDB1 after the second branch of the gate of the transistor P10 is connected to the gate of the transistor N14 is connected to the node DL of the sense amplifier SA1 after passing through the first inverter of the sense amplifier SA1; The node GD01 after the second branch of the gate of the transistor N11 is connected to the gate of the transistor P14 is connected to the node DLB of the sense amplifier SA1 after passing through the second inverter of the sense amplifier SA1; The node GD01 of the gate of the transistor N25 is connected to the node DLB of the sense amplifier SA1 after passing through the second inverter of the sense amplifier SA1; Wherein, the node DL of the sense amplifier SA1 is the first data storage node of the sense amplifier SA1, and the node DLB of the sense amplifier SA1 is the second data storage node of the sense amplifier SA1.

7. The output latch circuit for a sense amplifier according to claim 1, characterized in that: The node GDB2 of the gate of the transistor P15 is connected to the node DL of the sense amplifier SA2 after passing through the first inverter of the sense amplifier SA2; The node GDB2 after the second branch of the gate of the transistor P20 is connected to the gate of the transistor N24 is connected to the node DL of the sense amplifier SA1 after passing through the first inverter of the sense amplifier SA2; The node GD02 after the second branch of the gate of the transistor N21 is connected to the gate of the transistor P24 is connected to the node DLB of the sense amplifier SA2 after passing through the second inverter of the sense amplifier SA2; The node GD02 of the gate of the transistor N15 is connected to the node DLB of the sense amplifier SA2 after passing through the second inverter of the sense amplifier SA2; Wherein, the node DL of the sense amplifier SA2 is the first data storage node of the sense amplifier SA2, and the node DLB of the sense amplifier SA2 is the second data storage node of the sense amplifier SA2.

8. The output latching circuit for a sense amplifier according to claim 1, characterized in that: The transistors P10, P11, P12, P13, P14, P15, P20, P21, P22, P23, P24, and P25 are all P-type field effect transistors.

9. The output latch circuit for a sense amplifier according to claim 1, characterized in that: The transistor N10, transistor N11, transistor N12, transistor N13, transistor N14, transistor N15, transistor N20, transistor N21, transistor N22, transistor N23, transistor N24, and transistor N25 are all N-type field effect transistors.

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