Word line drive module, word line decoding circuit and memory chip

Abstract

This invention provides a word line driving module, a word line decoding circuit, and a memory chip. The word line driving module includes a voltage transmission unit. The voltage transmission unit includes a first voltage transmission section and a second voltage transmission section. The first voltage transmission section is turned on or off based on a first control signal and a second control signal, and when turned on, it transmits and outputs a first voltage signal. The second voltage transmission section is turned on or off based on the first control signal, and when turned on, it transmits and outputs a second voltage signal. The second voltage transmission section is implemented using a PMOS transistor and is turned on when the first control signal is a negative voltage. This invention solves the problem in the prior art where the voltage transmission unit is implemented using four thick-gate oxide MOS transistors, ultimately resulting in high cost and large area of ​​the memory chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor memory, in particular to a word line driving module, a word line decoding circuit and a memory chip. BACKGROUND

[0002] With the rapid development and wide application of modern electronic devices and embedded structures, the demand for high-integration circuit chips is increasing, thus giving rise to a series of requirements for limiting the area of integrated circuit chips. For memory chips, reducing the area of memory chips has always been the goal pursued by large-capacity or even super-large-capacity storage design.

[0003] The selected word line of the non-volatile memory needs positive high voltage when programming, and needs negative high voltage when erasing; the word line driving module injects different voltages into the corresponding word line under different operations through a voltage transmission unit, wherein the voltage transmission unit is usually composed of two PMOS tubes and two NMOS tubes, but the operating voltage range of each MOS tube fluctuates greatly, which requires that the MOS tube must be able to withstand high voltage, so thick gate oxide MOS tubes need to be selected. However, thick gate oxide MOS tubes have high cost and large area, which is not conducive to the realization of low cost and small area of memory chips.

[0004] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art merely because it is described in the background section of the present application. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a word line driving module, a word line decoding circuit and a memory chip, which are used to solve the problem that the cost and area of the memory chip are ultimately high and large due to the use of four thick gate oxide MOS tubes in the voltage transmission unit in the prior art.

[0006] To achieve the above object and other related objects, the present application provides a word line driving module, which comprises:

[0007] a voltage transmission unit comprising a first voltage transmission part and a second voltage transmission part; the first voltage transmission part is opened or closed based on a first control signal and a second control signal, and when opened, it transmits and outputs a first voltage signal; the second voltage transmission part is opened or closed based on the first control signal, and when opened, it transmits and outputs a second voltage signal;

[0008] wherein the second voltage transmission part is implemented by a PMOS tube and is opened when the first control signal is a negative voltage.

[0009] Optionally, the first voltage transmission unit comprises an NMOS transistor and a first PMOS transistor, a gate of the NMOS transistor is connected to the first control signal, a gate of the first PMOS transistor is connected to the second control signal, a drain of the NMOS transistor is connected to a source of the first PMOS transistor and receives the first voltage signal, a source of the NMOS transistor is connected to a drain of the first PMOS transistor and serves as an output terminal of the first voltage transmission unit, wherein the output terminal of the first voltage transmission unit is connected to an output terminal of the second voltage transmission unit and serves as an output terminal of the voltage transmission unit.

[0010] Optionally, the second voltage transmission unit comprises a second PMOS transistor, a gate of the second PMOS transistor is connected to the first control signal, a source of the second PMOS transistor receives the second voltage signal, and a drain of the second PMOS transistor serves as an output terminal of the second voltage transmission unit, wherein the output terminal of the second voltage transmission unit is connected to the output terminal of the first voltage transmission unit and serves as the output terminal of the voltage transmission unit.

[0011] Optionally, the word line driving module further comprises:

[0012] a level conversion unit comprising a first level conversion unit, a second level conversion unit and a third level conversion unit; the first level conversion unit outputs different first voltage signals under different operations based on a first input signal, the second level conversion unit outputs different second voltage signals under different operations based on a second input signal, and the third level conversion unit outputs different first control signals and second control signals under different operations based on a third input signal;

[0013] wherein the first control signal and the second control signal are used to open control corresponding PMOS transistors based on negative voltage.

[0014] Optionally, in the first level conversion unit:

[0015] under programming operation, if the first input signal is a logic high level, the first voltage signal is a positive voltage, and if the first input signal is a logic low level, the first voltage signal is a first power voltage;

[0016] under erasing operation, if the first input signal is a logic high level, the first voltage signal is a first negative voltage, and if the first input signal is a logic low level, the first voltage signal is a second power voltage;

[0017] wherein the first power voltage is less than the second power voltage.

[0018] Optionally, in the second level conversion unit:

[0019] In the programming operation, the second input signal is a logic low level, and the second voltage signal is a first power voltage;

[0020] In the erasing operation, the second input signal is a logic high level, and the second voltage signal is a second power voltage;

[0021] The first power voltage is less than the second power voltage.

[0022] Optionally, in the third level conversion unit:

[0023] In the programming operation, if the third input signal is a logic high level, the first control signal is a positive voltage and the second control signal is a second negative voltage, and if the third input signal is a logic low level, the first control signal is a second negative voltage and the second control signal is a positive voltage;

[0024] In the erasing operation, if the third input signal is a logic high level, the first control signal is a second power voltage and the second control signal is a first negative voltage, and if the third input signal is a logic low level, the first control signal is a first negative voltage and the second control signal is a second power voltage;

[0025] The first negative voltage is less than the second negative voltage.

[0026] The application further provides a word line decoding circuit, which comprises the word line driving module according to any one of the above.

[0027] The application further provides a memory chip, which comprises the word line decoding circuit according to the above.

[0028] Optionally, the memory chip is a NOR FLASH memory chip.

[0029] As described above, the word line driving module, the word line decoding circuit and the memory chip of the application reduce the number of MOS tubes in the voltage transmission unit from four to three by introducing a negative voltage (i.e. a second negative voltage) in the programming operation, thereby reducing the cost and the area. For large-capacity or even super-large-capacity storage design, the cost and the area are reduced more obviously. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 The structure schematic diagram of a conventional word line driving module is shown.

[0031] Figure 2 The structure schematic diagram of a conventional word line driving module is shown. Figure 1 The schematic diagram of the corresponding relationship between the signals in the level conversion unit in the programming and erasing operations is shown.

[0032] Figure 3 The diagram shown is a structural schematic of the word line driving module in an embodiment of the present invention.

[0033] Figure 4 Displayed as Figure 3 This diagram illustrates the correspondence between the signals in the level conversion unit under programming and erasing operations.

[0034] Component designation explanation

[0035] 100 and 200 character line driver modules

[0036] 110, 210 level conversion unit

[0037] 111, 211 First Level Conversion Section

[0038] 112, 212 Second Level Conversion Section

[0039] 113, 213 Third Level Conversion Section

[0040] 120 and 220 voltage transmission units

[0041] 121, 221 First Voltage Transmission Section

[0042] 122, 222 Second Voltage Transmission Section Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] Figure 1 A word line driving module 100 is shown, including a level conversion unit 110 and a voltage transmission unit 120; wherein, the level conversion unit 110 includes a first level conversion section 111, a second level conversion section 112 and a third level conversion section 113, and the voltage transmission unit 120 includes a first voltage transmission section 121 and a second voltage transmission section 122.

[0046] The first level conversion unit 111 receives the first input signal A and outputs the first voltage signal GWL. Wherein: Figure 2 As shown, during the programming operation, if the first input signal A is at a logic high level, then the first voltage signal GWL is a positive voltage Vpos; if the first input signal A is at a logic low level, then the first voltage signal GWL is a first power supply voltage Vpwr1. During the erase operation, if the first input signal A is at a logic high level, then the first voltage signal GWL is a negative voltage Vneg; if the first input signal A is at a logic low level, then the first voltage signal GWL is a second power supply voltage Vpwr2.

[0047] The second level conversion unit 112 receives the second input signal B and outputs the second voltage signal VB. Wherein: Figure 2 As shown, during the programming operation, the second input signal B is at a logic low level, and the second voltage signal VB is the first power supply voltage Vpwr1; during the erase operation, the second input signal B is at a logic high level, and the second voltage signal VB is the second power supply voltage Vpwr2.

[0048] The third level conversion unit 113 receives the third input signal C and outputs the first control signal VN and the second control signal VP. Wherein: Figure 2 As shown, during programming operations, if the third input signal C is at a logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is a zero voltage. If the third input signal C is at a logic low level, the first control signal VN is a zero voltage, and the second control signal VP is a positive voltage Vpos. During erasing operations, if the third input signal C is at a logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is a negative voltage Vneg. If the third input signal C is at a logic low level, the first control signal VN is a negative voltage Vneg, and the second control signal VP is the second power supply voltage Vpwr2.

[0049] The first voltage transmission unit 121 is turned on or off based on a first control signal VN and a second control signal VP, and when turned on, it transmits and outputs a first voltage signal GWL. Specifically, the first voltage transmission unit 121 includes a first NMOS transistor M1 and a first PMOS transistor M2; the gate of the first NMOS transistor M1 is connected to the first control signal VN, the gate of the first PMOS transistor M2 is connected to the second control signal VP, the drain of the first NMOS transistor M1 is connected to the source of the first PMOS transistor M2 and receives the first voltage signal GWL, and the source of the first NMOS transistor M1 is connected to the drain of the first PMOS transistor M2 and serves as the output terminal of the first voltage transmission unit 121.

[0050] The second voltage transmission unit 122 is turned on or off based on a first control signal VN and a second control signal VP, and when turned on, it transmits and outputs a second voltage signal VB. Specifically, the second voltage transmission unit 122 includes a second NMOS transistor M3 and a second PMOS transistor M4; the gate of the second NMOS transistor M3 is connected to the second control signal VP, the gate of the second PMOS transistor M4 is connected to the first control signal VN, the drain of the second NMOS transistor M3 is connected to the source of the second PMOS transistor M4 and receives the second voltage signal VB, and the source of the second NMOS transistor M3 is connected to the drain of the second PMOS transistor M4 and serves as the output terminal of the second voltage transmission unit 122. Furthermore, the output terminal of the first voltage transmission unit 121 is connected to the output terminal of the second voltage transmission unit 122 and serves as the output terminal of the voltage transmission unit 120 to output a word line drive signal LWL.

[0051] In the aforementioned word line driver module 100, whether in programming or erasing operations, a simultaneous high logic level for both the first input signal A and the third input signal C indicates selection; otherwise, it indicates non-selection. Furthermore, during programming operations, the second input signal B is always at a low logic level; during erasing operations, the second input signal B is always at a high logic level. Below, please refer to... Figure 1 and Figure 2 The programming and erasing operations of the word line driver module 100 described above are explained.

[0052] During programming operations:

[0053] When both the first input signal A and the third input signal C are at logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is zero voltage. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. Thus, the positive voltage Vpos is output as the word line drive signal LWL.

[0054] When the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is at zero voltage and the second control signal VP is at a positive voltage Vpos. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0055] When the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is a zero voltage. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0056] When both the first input signal A and the third input signal C are at logic low level, the first control signal VN is at zero voltage and the second control signal VP is at positive voltage Vpos. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0057] During the erasure operation:

[0058] When both the first input signal A and the third input signal C are at logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is the negative voltage Vneg. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. Thus, the negative voltage Vneg is output as the word line drive signal LWL.

[0059] When the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is a negative voltage Vneg, and the second control signal VP is a second power supply voltage Vpwr2. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL.

[0060] When the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is the negative voltage Vneg. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL.

[0061] When both the first input signal A and the third input signal C are at logic low level, the first control signal VN is the negative voltage Vneg, and the second control signal VP is the second power supply voltage Vpwr2. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL.

[0062] As can be seen, the word line driving module 100 performs the following functions: During programming, a positive voltage Vpos is applied to the selected word line, and a first power supply voltage Vpwr1 is applied to the unselected word line; during erasure, a negative voltage Vneg is applied to the selected word line, and a second power supply voltage Vpwr2 is applied to the unselected word line. The positive voltage Vpos is the programming voltage, which injects electrons into the gate of the memory transistor corresponding to the selected word line; the negative voltage Vneg is the erasure voltage, which erases electrons from the gate of the memory transistor corresponding to the selected word line; furthermore, the second power supply voltage Vpwr2 is the power supply voltage of the word line driving circuit 100, and the first power supply voltage Vpwr1 is a voltage lower than the second power supply voltage Vpwr2.

[0063] In the aforementioned word line driver module 100, the voltage transmission unit 120 consists of two PMOS transistors and two NMOS transistors, used to transmit different voltage values ​​for the same or different signals. Since the operating voltage range of each MOS transistor fluctuates significantly, each MOS transistor must be able to withstand high voltages; therefore, thick-gate oxide MOS transistors are required. However, thick-gate oxide MOS transistors are expensive and have a large area, which is detrimental to achieving low cost and small area in memory chips. Therefore, the applicant proposes the word line driver module 200 of this application embodiment, which reduces cost and area by eliminating one MOS transistor.

[0064] like Figure 3 As shown, this embodiment provides a word line driving module 200, including a voltage transmission unit 220; further, it also includes a level conversion unit 210.

[0065] The level conversion unit 210 is used to provide the voltage transmission unit 220 with a first voltage signal GWL, a second voltage signal VB, a first control signal VN, and a second control signal VP. In one example, the level conversion unit 210 includes a first level conversion section 211, a second level conversion section 212, and a third level conversion section 213.

[0066] The first level conversion unit 211 outputs different first voltage signals GWL based on the first input signal A under different operations. Wherein: Figure 4As shown, during the programming operation, if the first input signal A is at a logic high level (i.e., A = 1), then the first voltage signal GWL is a positive voltage Vpos; if the first input signal A is at a logic low level (i.e., A = 0), then the first voltage signal GWL is a first power supply voltage Vpwr1. During the erase operation, if the first input signal A is at a logic high level, then the first voltage signal GWL is a first negative voltage Vneg1; if the first input signal A is at a logic low level, then the first voltage signal GWL is a second power supply voltage Vpwr2.

[0067] In one embodiment, the first level conversion unit 211 includes a first selector and a second selector (not shown in the figure). The first selector is triggered by a programming instruction and switches based on a first input signal A to output a positive voltage Vpos or a first power supply voltage Vpwr1. The second selector is triggered by an erase instruction and switches based on the first input signal A to output a first negative voltage Vneg1 or a second power supply voltage Vpwr2. Of course, this embodiment is only illustrative, and it is also feasible for the first level conversion unit 211 to adopt other circuit structures that can achieve the above functions. There is no limitation on this.

[0068] The second level conversion unit 212 outputs different second voltage signals VB based on the second input signal B under different operations. Wherein: (e.g.) Figure 4 As shown, during the programming operation, the second input signal B is at a logic low level (i.e., B = 0), and the second voltage signal VB is the first power supply voltage Vpwr1; during the erase operation, the second input signal B is at a logic high level (i.e., B = 1), and the second voltage signal VB is the second power supply voltage Vpwr2.

[0069] In one embodiment, the second level conversion unit 212 includes a third selector and a fourth selector (not shown in the figure). The third selector is triggered by a programming instruction and switches based on the second input signal B to output a first power supply voltage Vpwr1. Since the second input signal B is always at a logic low level during programming, the high selection terminal of the two-to-one switch in the third selector is floating and the low selection terminal is connected to the first power supply voltage Vpwr1. The fourth selector is triggered by an erase instruction and switches based on the second input signal B to output a second power supply voltage Vpwr2. Since the second input signal B is always at a logic high level during erase, the high selection terminal of the two-to-one switch in the fourth selector is connected to the second power supply voltage Vpwr2 and the low selection terminal is floating. Of course, this embodiment is only illustrative, and it is also feasible for the second level conversion unit 212 to adopt other circuit structures that can achieve the above functions. There is no limitation on this.

[0070] The third level conversion unit 213 outputs different first control signals VN and second control signals VP under different operations based on the third input signal C. At least the first control signal VN controls the second PMOS transistor M3 to turn on based on a negative voltage. Furthermore, both the first control signal VN and the second control signal VP control the corresponding PMOS transistors (including the first PMOS transistor M2 and the second PMOS transistor M3) to turn on based on negative voltages. For example: Figure 4 As shown, under programming operation, if the third input signal C is at a logic high level (i.e., C = 1), then the first control signal VN is a positive voltage Vpos, and the second control signal VP is a second negative voltage Vneg2. If the third input signal C is at a logic low level (i.e., C = 0), then the first control signal VN is a second negative voltage Vneg2, and the second control signal VP is a positive voltage Vpos. Under erasing operation, if the third input signal C is at a logic high level, then the first control signal VN is a second power supply voltage Vpwr2, and the second control signal VP is a first negative voltage Vneg1. If the third input signal C is at a logic low level, then the first control signal VN is a first negative voltage Vneg1, and the second control signal VP is a second power supply voltage Vpwr2.

[0071] In one embodiment, the third level conversion unit 213 includes a fifth selector, a sixth selector, a seventh selector, and an eighth selector (not shown in the figure). The fifth selector is triggered by a programming instruction and switches based on a third input signal C to output a positive voltage Vpos or a second negative voltage Vneg2. The sixth selector is also triggered by a programming instruction and switches based on the third input signal C to output a second negative voltage Vneg2 or a positive voltage Vpos. The seventh selector is triggered by an erase instruction and switches based on the third input signal C to output a second power supply voltage Vpwr2 or a first negative voltage Vneg1. The eighth selector is also triggered by an erase instruction and switches based on the third input signal C to output a first negative voltage Vneg1 or a second power supply voltage Vpwr2. Of course, this embodiment is only illustrative, and it is also feasible for the third level conversion unit 213 to adopt other circuit structures that can achieve the above functions. There is no limitation on this.

[0072] Regarding the voltages, the positive voltage Vpos is the programming voltage, which enables the injection of electrons into the gate of the corresponding memory transistor, and is typically a positive high voltage; the first negative voltage Vneg1 is the erase voltage, which enables the erasure of electrons from the gate of the corresponding memory transistor, and is typically a negative high voltage; the second power supply voltage Vpwr2 is the power supply voltage of the word line driving circuit 200, and the first power supply voltage Vpwr1 is a voltage lower than the second power supply voltage Vpwr2; the second negative voltage Vneg2 is the driving voltage that controls the PMOS transistor to be fully turned on, and is typically a negative voltage higher than the first negative voltage Vneg1. Furthermore, taking the above embodiments as examples, the word line driving module 200 may also include an instruction generation unit, which generates programming instructions or erase instructions based at least on the second input signal B.

[0073] The voltage transmission unit 220 includes a first voltage transmission section 221 and a second voltage transmission section 222. During programming or erasing operations, the first voltage transmission section 221 and the second voltage transmission section 222 are in a mutually exclusive state, that is, when the first voltage transmission section 221 is turned on, the second voltage transmission section 222 is turned off, and when the first voltage transmission section 221 is turned off, the second voltage transmission section 222 is turned on. In addition, the output terminal of the first voltage transmission section 221 is connected to the output terminal of the second voltage transmission section 222 and serves as the output terminal of the voltage transmission unit 220 to output the word line drive signal LWL.

[0074] The first voltage transmission unit 221 turns on or off based on the first control signal VN and the second control signal VP, and transmits and outputs the first voltage signal GWL when it is turned on.

[0075] In one embodiment, the first voltage transmission unit 221 includes an NMOS transistor M1 and a first PMOS transistor M2; wherein, the gate of the NMOS transistor M1 is connected to a first control signal VN, the gate of the first PMOS transistor M2 is connected to a second control signal VP, the drain of the NMOS transistor M1 is connected to the source of the first PMOS transistor M2 and receives a first voltage signal GWL, and the source of the NMOS transistor M1 is connected to the drain of the first PMOS transistor M2 and serves as the output terminal of the first voltage transmission unit 221.

[0076] The second voltage transmission unit 222 is turned on or off based on the first control signal VN, and when it is turned on, it transmits and outputs the second voltage signal VB.

[0077] Specifically, the second voltage transmission unit 222 is implemented using a PMOS transistor and is turned on when the first control signal VN is a negative voltage (a second negative voltage Vneg2 during programming operations and a first negative voltage Vneg1 during erase operations). In one embodiment, the second voltage transmission unit 222 includes a second PMOS transistor M3; wherein the gate of the second PMOS transistor M3 is connected to the first control signal VN, the source of the second PMOS transistor M3 receives the second voltage signal VB, and the drain of the second PMOS transistor M3 serves as the output terminal of the second voltage transmission unit 222. By introducing the second negative voltage Vneg2 during programming operations to turn on the second PMOS transistor M3, the second voltage signal VB can be completely transmitted to the output, thereby reducing the number of NMOS transistors.

[0078] In this embodiment, the word line driver module 200, whether in programming or erasing operations, indicates selection when both the first input signal A and the third input signal C are at a logic high level; otherwise, it indicates non-selection. Additionally, during programming, the second input signal B is at a logic low level; during erasing, the second input signal B is at a logic high level. Below, please refer to... Figure 3 and Figure 4 The working process of programming and erasing operations of the word line driver module 200 in this embodiment will be described.

[0079] During programming operations:

[0080] When both the first input signal A and the third input signal C are at logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is a second negative voltage Vneg2. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission section 221 are turned on, and the second PMOS transistor M3 in the second voltage transmission section 222 is turned off. Thus, the positive voltage Vpos is output as the word line drive signal LWL.

[0081] When the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is the second negative voltage Vneg2, and the second control signal VP is the positive voltage Vpos. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission section 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission section 222 is turned on. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0082] When the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is a second negative voltage Vneg2. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned off. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0083] When both the first input signal A and the third input signal C are at logic low level, the first control signal VN is the second negative voltage Vneg2, and the second control signal VP is the positive voltage Vpos. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission section 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission section 222 is turned on. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0084] During the erasure operation:

[0085] When both the first input signal A and the third input signal C are at logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is the first negative voltage Vneg1. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission section 221 are turned on, and the second PMOS transistor M3 in the second voltage transmission section 222 is turned off. Thus, the first negative voltage Vneg1 is output as the word line drive signal LWL.

[0086] When the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is the first negative voltage Vneg1, and the second control signal VP is the second power supply voltage Vpwr2. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission section 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission section 222 is turned on. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL.

[0087] When the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is the first negative voltage Vneg1. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission section 221 are turned on, and the second PMOS transistor M3 in the second voltage transmission section 222 is turned off. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL.

[0088] When both the first input signal A and the third input signal C are at logic low level, the first control signal VN is the first negative voltage Vneg1, and the second control signal VP is the second power supply voltage Vpwr2. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission section 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission section 222 is turned on. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL.

[0089] As can be seen, the output of the word line driver module 200 in this embodiment is the same as that of the traditional word line driver module 100. However, the voltage transmission unit 220 in the word line driver module 200 in this embodiment only requires three MOS transistors, which is one less than the voltage transmission unit 120 in the traditional word line driver module 100. Therefore, the word line driver module 200 in this embodiment has lower cost and smaller area, which is more conducive to realizing low cost and small area of ​​memory chip.

[0090] Accordingly, this embodiment also provides a word line decoding circuit, including a word line driving module 200; wherein, the word line driving module 200 is implemented using the module structure described above, the relevant details of which can be found above and will not be repeated here. Of course, the word line decoding circuit may also include other module structures, such as decoding modules, etc., and there is no limitation on this.

[0091] Accordingly, this embodiment also provides a memory chip, including a word line decoding circuit; wherein, the word line decoding circuit is implemented using the circuit structure described above, the relevant details of which can be found above and will not be repeated here. Of course, the memory chip may also include other circuit structures, such as memory arrays, readout circuits, etc., and there is no limitation thereto. In practical applications, the memory chip in this embodiment is usually a NOR FLASH (non-volatile flash memory) memory chip.

[0092] In summary, the word line driving module, word line decoding circuit, and memory chip of the present invention reduce the number of MOS transistors in the voltage transmission unit from four to three by introducing a negative voltage (i.e., a second negative voltage) during programming operations, thereby reducing cost and area. This is particularly significant for large-capacity and even ultra-large-capacity memory designs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A word line driver module, characterized in that, The word line driving module includes: The voltage transmission unit includes a first voltage transmission section and a second voltage transmission section; the first voltage transmission section is turned on or off based on a first control signal and a second control signal, and when turned on, it transmits and outputs a first voltage signal; the second voltage transmission section is turned on or off based on the first control signal, and when turned on, it transmits and outputs a second voltage signal. The first voltage transmission unit includes an NMOS transistor and a first PMOS transistor. The gate of the NMOS transistor is connected to the first control signal, the gate of the first PMOS transistor is connected to the second control signal, the drain of the NMOS transistor is connected to the source of the first PMOS transistor and receives the first voltage signal, and the source of the NMOS transistor is connected to the drain of the first PMOS transistor and serves as the output terminal of the first voltage transmission unit. The second voltage transmission section is implemented using a second PMOS transistor and is turned on when the first control signal is a negative voltage; the gate of the second PMOS transistor is connected to the first control signal, the source of the second PMOS transistor receives the second voltage signal, and the drain of the second PMOS transistor serves as the output terminal of the second voltage transmission section. The output terminal of the first voltage transmission unit is connected to the output terminal of the second voltage transmission unit and serves as the output terminal of the voltage transmission unit.

2. The word line driving module according to claim 1, characterized in that, The word line driving module further includes: The level conversion unit includes a first level conversion section, a second level conversion section, and a third level conversion section; the first level conversion section outputs different first voltage signals based on a first input signal under different operations, the second level conversion section outputs different second voltage signals based on a second input signal under different operations, and the third level conversion section outputs different first control signals and second control signals based on a third input signal under different operations; The first control signal and the second control signal control the turn-on of the corresponding PMOS transistors based on the negative voltage.

3. The word line driving module according to claim 2, characterized in that, In the first level conversion section: Under programming operation, if the first input signal is at a logic high level, then the first voltage signal is a positive voltage; if the first input signal is at a logic low level, then the first voltage signal is a first power supply voltage. During the erase operation, if the first input signal is at a logic high level, then the first voltage signal is the first negative voltage; if the first input signal is at a logic low level, then the first voltage signal is the second power supply voltage. Wherein, the first power supply voltage is less than the second power supply voltage.

4. The word line driving module according to claim 2, characterized in that, In the second level conversion section: Under programming operation, the second input signal is a logic low level, and the second voltage signal is the first power supply voltage; During the erase operation, the second input signal is a logic high level, and the second voltage signal is the second power supply voltage; Wherein, the first power supply voltage is less than the second power supply voltage.

5. The word line driving module according to claim 2, characterized in that, In the third level conversion section: Under programming operation, if the third input signal is at a logic high level, then the first control signal is a positive voltage and the second control signal is a second negative voltage; if the third input signal is at a logic low level, then the first control signal is a second negative voltage and the second control signal is a positive voltage. During the erase operation, if the third input signal is at a logic high level, then the first control signal is the second power supply voltage and the second control signal is the first negative voltage; if the third input signal is at a logic low level, then the first control signal is the first negative voltage and the second control signal is the second power supply voltage. Wherein, the first negative pressure is less than the second negative pressure.

6. A word-line decoding circuit, characterized in that, The word line decoding circuit includes: a word line driving module as described in any one of claims 1 to 5.

7. A memory chip, characterized in that, The memory chip includes: the word line decoding circuit as described in claim 6.

8. The memory chip according to claim 7, characterized in that, The memory chip is a NOR FLASH memory chip.

Images