Memory testing device, three-dimensional stacked memory chip and memory testing method and system

Abstract

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and particularly relates to a memory testing device, a three-dimensional stacked memory chip, and a memory testing method and system. Background Art

[0002] With the development of artificial intelligence, the demand for computing power is getting higher and higher, and more and more scenarios require the use of DRAM (Dynamic Random Access Memory) chips. How to efficiently test the timing parameters and functions of DRAM chips has become one of the core issues for those skilled in the art.

[0003] Currently, the testing of DRAM chips mainly relies on corresponding machines for testing. These machines use robotic arms to pick up and classify chips, and can test 128 to 256 DRAM chips at a time under high-temperature conditions (such as 88°C). However, the testing methods of these machines are costly and inflexible.

[0004] At the same time, due to some inevitable delays in the access of DRAM chips themselves, the bandwidth utilization rate of the data interface in system integration is greatly restricted. Summary of the Invention

[0005] The purpose of the present invention is to provide a memory testing device, a three-dimensional stacked memory chip, and a memory testing method and system, which can efficiently test the corresponding functional parameters of the three-dimensional stacked memory chip and save testing time and costs.

[0006] To achieve the above purpose, the present invention provides a memory testing device, which is embedded in the three-dimensional stacked memory chip or arranged outside the three-dimensional stacked memory chip. The three-dimensional stacked memory chip includes multiple layers of memory die stacked together. The memory testing device is embedded with: A first configuration register for configuring the test gear of the current functional parameter to be tested; A second configuration register for configuring the test mode corresponding to the current functional parameter; A third configuration register for configuring the test instruction of the current functional parameter, and at least one of the test directions and operation types indicated by different test instructions is different; A built-in self-test module, which is embedded with a built-in self-test process, and is used to receive corresponding test stimuli, and under the test gear configured by the first configuration register and the test mode configured by the second configuration register, activate the corresponding word lines or bit lines in the three-dimensional stacked memory chip according to the test instruction configured in the third configuration register, so as to execute the built-in self-test process and test the current functional parameter of the three-dimensional stacked memory chip; Among them, the configuration values of at least one of the first configuration register, the second configuration register, and the third configuration register are adjusted according to the test results of the built-in self-test module.

[0007] Optionally, the built-in self-test process includes: Writing test vector data into the three-dimensional stacked memory chip; Reading out the corresponding data in the three-dimensional stacked memory chip and comparing whether the read data is consistent with the written data; If they are consistent, the configuration value in the first configuration register is adjusted to reduce the test gear, so that the built-in self-test module re-tests the current functional parameters of the three-dimensional stacked memory chip at the reduced test gear.

[0008] Optionally, if the read data is inconsistent with the written data, the built-in self-test module is further used to perform a Shmoo plot analysis on the test results to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter.

[0009] Optionally, after the built-in self-test module completes the test of the current functional parameter, the configuration values of at least one of the first configuration register, the second configuration register, and the third configuration register are adjusted so that the built-in self-test module tests the next functional parameter of the three-dimensional stacked memory chip.

[0010] Optionally, when the test direction indicated by the test instruction in the third configuration register is the word line direction, after activating the corresponding word line and writing data of a predetermined number of test vectors, the address in the bit line direction automatically points to the next bit line; when the test direction indicated by the test instruction in the third configuration register is the bit line direction, after writing data of a predetermined number of test vectors, the address in the word line direction automatically points to the next word line.

[0011] Optionally, when the test direction is the word line direction, different configuration values in the second configuration register can implement a basic mode and an extended mode. The basic mode includes at least one of an all-0 mode, an all-1 mode, and a checkerboard mode. The extended mode includes at least one of an inter-row alternating mode and a word line adjustable step mode; And / or, when the test direction is the bit line direction, different configuration values in the second configuration register can implement an odd-even column alternating activation test mode and a diagonal column interference test mode.

[0012] Optionally, the built-in self-test process executed in the word line direction further includes at least one of the following operations (1) to (4): (1) Perform a voltage gradient scan on the corresponding word lines in the three-dimensional stacked memory chip using a corresponding voltage step; (2) Perform a negative over-drive on the corresponding word lines in the three-dimensional stacked memory chip to detect leakage through a reverse bias voltage; (3) Update the reference voltage once every preset number of writes to the three-dimensional stacked memory chip; (4) Add a row interference test enhancement test instruction to the current functional parameter test, and the row interference test enhancement test instruction is used to implement the coupling test between adjacent word lines and / or the insertion of a refresh interval in the three-dimensional stacked memory chip.

[0013] Optionally, the built-in self-test process performed in the bit line direction further includes at least one of the following operations (1) to (3): (1) Dynamically adjust the bias voltage of the sense amplifier for reading the corresponding data in the three-dimensional stacked memory chip; (2) Inject enable timing jitter into the sense amplifier for reading the corresponding data in the three-dimensional stacked memory chip; (3) Apply a high-speed data transition and measure the bit line voltage establishment time to implement a bit line slew rate test.

[0014] Optionally, the current functional parameters include at least one timing parameter, and the timing parameters include at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, tFAW.

[0015] Optionally, the three-dimensional stacked memory chip further includes a memory controller, the memory test device is embedded in the memory controller, the memory controller is disposed on the buffer die, and the multi-layer memory dies are hybrid-bonded together through through-silicon vias between them and with the buffer die; or, the memory test device is disposed in the main control chip outside the three-dimensional stacked memory chip.

[0016] Based on the same inventive concept, the present invention also provides a three-dimensional stacked memory chip, which includes a memory controller and multi-layer memory dies stacked together, and the memory test device as described in the present invention is embedded in the memory controller.

[0017] Based on the same inventive concept, the present invention further provides a memory test system, which includes: a three-dimensional stacked memory chip, a test host, and the memory test device as described in the present invention; wherein, the three-dimensional stacked memory chip includes a memory controller and multiple memory dies stacked together, and the memory test device is embedded in the memory controller, or the memory test device is disposed in a test chip outside the three-dimensional stacked memory chip, and the test host applies corresponding test stimuli to the memory test device to activate corresponding word lines or bit lines in the three-dimensional stacked memory chip, so as to perform corresponding functional parameter tests on the three-dimensional stacked memory chip.

[0018] Based on the same inventive concept, the present invention further provides a memory test method, which includes the following steps: Providing the memory test device as described in the present invention and a three-dimensional stacked memory chip to be tested, the memory test device is disposed outside the three-dimensional stacked memory chip or embedded in a memory controller inside the three-dimensional stacked memory chip, and corresponding built-in self-test processes, a first configuration register, a second configuration register, and a third configuration register are embedded in the memory test device; Determining the current functional parameter to be tested and its test direction, and configuring the test gear of the current functional parameter by writing corresponding configuration values into the first configuration register, configuring the test mode corresponding to the current functional parameter by writing corresponding configuration values into the second configuration register, and configuring the test instruction corresponding to the current functional parameter by writing corresponding configuration values into the third configuration register, at least one of the test directions and operation types indicated by different test instructions is different; Applying corresponding test stimuli to the memory test device by the test host, the memory test device receives the test stimuli, and in the test gear configured by the first configuration register and the test mode configured by the second configuration register, according to the test instruction configured by the third configuration register, activates corresponding word lines or bit lines in the three-dimensional stacked memory chip to execute the built-in self-test process and perform the test of the current functional parameter on the three-dimensional stacked memory chip.

[0019] Optionally, the built-in self-test process includes: Receiving the test stimuli sent by the test host and writing data of a test vector into the three-dimensional stacked memory chip; Reading out corresponding data in the three-dimensional stacked memory chip and comparing whether the read data is consistent with the written data; If they are consistent, adjust the configuration value in the first configuration register to decrease the test gear, and then, under the decreased test gear, re - execute the built - in self - test process until the read data is inconsistent with the written data; If they are inconsistent, perform a Shmoo plot analysis on the current test result to determine the final value of the current functional parameter, and then complete the test of the current functional parameter; After completing the test of the current functional parameter, determine whether the current functional parameter is the last functional parameter to be tested. If so, end the test; if not, adjust the configuration value of at least one of the first configuration register, the second configuration register, and the third configuration register to perform the test of the next current functional parameter on the three - dimensional stacked memory chip.

[0020] Compared with the prior art, the memory test device, the three - dimensional stacked memory chip, and the memory test method and system provided by the present invention embed a built - in self - test (BIST) test process and first to third configuration registers in the memory test device. Thus, on the test host, only a specified test stimulus needs to be applied to automatically implement the test of the corresponding functional parameters of the three - dimensional stacked memory chip. During the test, the switching of functional parameters, test directions, and test modes can be achieved only by adjusting the configuration values in the first to third configuration registers. Therefore, the test process of the functional parameters of the memory is optimized, greatly saving the test time and test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them: Figure 1 and Figure 2 are schematic diagrams of the memory test device and test system architecture according to an embodiment of the present invention.

[0022] Figure 3 is a schematic diagram of the structure of a storage unit of a three - dimensional stacked memory chip according to an embodiment of the present invention.

[0023] Figure 4 is a schematic diagram of a packaging structure of a three - dimensional stacked memory chip according to an embodiment of the present invention.

[0024] Figure 5 is a schematic diagram of some configuration values in the third configuration register of the memory test device according to an embodiment of the present invention.

[0025] Figure 6 is a schematic diagram of Shmoo plot parameters established according to measurement results when the memory test device according to an embodiment of the present invention is applied to testing.

[0026] Figure 7 It is a schematic flowchart of a memory test method according to an embodiment of the present invention. Detailed implementation manners

[0027] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some well-known technical features in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals represent the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. On the contrary, when an element is referred to as "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0028] An embodiment of the present invention provides a memory test device 10a, which can be embedded in a three-dimensional stacked memory chip 1, as Figure 1 shown; the memory test device 10a can also be externally disposed outside the three-dimensional stacked memory chip 1, as Figure 2 shown.

[0029] In one example, please refer to Figure 2 , the memory test device 10a is disposed in a main control chip outside the three-dimensional stacked memory chip 1. The main control chip serves as a test host 2 after the three-dimensional stacked memory chip 1 leaves the factory, and may include a main control processor 20 and the memory test device 10a, etc. The main control processor may include any type of processor device with computing and processing capabilities such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a dedicated processor, etc. The processor device may be configured to execute instructions or software (including code, operating system or application programs, etc.), firmware or a combination thereof that can be executed by one or more computers.

[0030] Based on this, please refer to Figure 1 and Figure 4 , this embodiment also provides a three-dimensional stacked memory chip 1, which includes a memory controller 10 and n + 1 layers of memory die D0~Dn stacked together. The memory controller 10 is embedded with a memory test device 10a as described in this embodiment.

[0031] Among them, the n + 1 layers of memory die D0~Dn are stacked to form a memory stack 11. Each memory die D0~Dn can be a DRAM or any other suitable type of memory die structure. Among them, the DRAM can be any suitable one such as synchronous DRAM (SDRAM), wide I / O DRAM, etc. The memory stack 11 can be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc. The memory test device 10a is embedded in the memory controller 10. The memory controller 10 is disposed on the buffer die 105. The n + 1 layers of memory die D0~Dn and between them and the buffer die 105 are bonded together by through-silicon vias (TSV) hybrid bonding.

[0032] Please refer to Figure 3 , each memory die D0~Dn can include multiple storage units (which can also be called "data units"). Each storage unit can have a storage array determined by the intersection of multiple word lines WL (each word line can be regarded as a row) and multiple bit lines BL (each bit line can be regarded as a column). The storage array has multiple cells. Each cell is located at the intersection of a corresponding word line WL and a bit line BL of the storage unit, that is, corresponding to a storage address, which is determined by the word line WL and the bit line BL. The word line WL (wordline) is addressed by the row address (RA) in the storage address, and the bit line BL (bitline) is addressed by the column address (CA) in the storage address. Among them, a storage unit can be an arbitrary suitable level of management unit higher than the cell level, such as a storage block (block), a sector, or a page, etc. of the memory stack 11. Among them, a page contains multiple bytes (whose address range can be determined by multiple word lines and multiple bit lines), a sector contains multiple pages, a storage block contains multiple sectors, and multiple storage units can form a bank.

[0033] It should be understood that in the example where the memory test device 10a is embedded in the memory controller 10 of the three-dimensional stacked memory chip 1, in addition to the memory test device 10a, the memory controller 10 may also have other logic modules (not shown) such as an input / output interface 100 to implement other functions. For example, other logic modules in the memory controller 1 may include circuits for error correction of the memory (such as ECC correction), circuits for clock and frequency control (such as a phase-locked loop PLL), circuits for managing power consumption and temperature, first-in-first-out queue registers (fifo), and any other required circuits. These circuits are not the focus of the present invention and will not be described in detail herein. Among them, the input / output interface 100 can be any suitable parallel communication protocol interface that supports multiple I / Os, such as an AXI (Advanced eXtensible Interface) interface or a CHI (Coherent Hub Interface) interface, or any other suitable high-bandwidth protocol interface. The present invention is not limited thereto. Among them, the AXI interface is an on-chip bus interface for a master-slave architecture oriented to high performance, high bandwidth, and low latency. Its address, instruction, and data phases are separated, supporting unaligned data transmission. At the same time, in burst transmission, only the first address is required, and the separate read and write data channels support the transmission access and out-of-order access of a large number of outstanding instructions to be executed (such as the number of uncompleted transactions such as read and write instructions), and it is easier to perform timing convergence, which is suitable for high-speed memory access.

[0034] Please continue to refer to Figure 1 and Figure 2 、 Figure 4 , the memory test device 10a is embedded with a first configuration register 101, a second configuration register 102, a third configuration register 103, and a built-in self-test module 104.

[0035] Among them, the first configuration register 101 is used to configure the test gear of the current function parameter to be tested, the second configuration register 102 is used to configure the test mode corresponding to the current function parameter, and the third configuration register 103 is used to configure the test instruction of the current function parameter. At least one of the test directions and operation types indicated by different test instructions is different.

[0036] In addition, the configuration value of at least one of the first configuration register 101, the second configuration register 102, and the third configuration register 103 is adjusted according to the test result of the built-in self-test module 104. This adjustment can be implemented by a test program on the test host 2, or can be automatically implemented by the memory test device 10a according to the test result (that is, the memory test device 10a automatically adjusts the corresponding configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103).

[0037] In one example, the test instruction cmd_t configured in the third configuration register 103 is as Figure 5 shown in the table. In this example, the high 4 bits of the third configuration register MR2 can be selected to represent the test instruction cmd_t, and by configuring these high 4 bits to be equal to different values, the corresponding test direction and the operation type implemented in this test direction can be represented. For example: cmd_t[3:0]=h1=0001 represents a write operation in the word line WL direction (abbreviated as "WR" in Figure 5 ); cmd_t[3:0]=h2=0010 represents a read operation in the word line WL direction (abbreviated as "RD" in Figure 5 ); cmd_t[3:0]=h3=0011 represents a read-then-write operation in the word line WL direction ( Figure 5 abbreviated as "RD-WR" in); cmd_t[3:0]=h4=0100 represents a write-then-read operation in the word line WL direction ( Figure 5 abbreviated as "WR-RD" in); cmd_t[3:0]=h5=0101 represents a refresh operation in the word line WL direction; ……(other operations in the word line WL direction); cmd_t[3:0]=ha=1010 represents a write operation in the bit line BL direction; cmd_t[3:0]=hb=1011 represents a read operation in the bit line BL direction; cmd_t[3:0]=hc=1100 represents a read-then-write operation in the bit line BL direction; cmd_t[3:0]=hd=1101 represents a write-then-read operation in the bit line BL direction; cmd_t[3:0]=he=1110 represents a refresh operation in the bit line BL direction; ……(other operations in the bit line WL direction).

[0038] It should be understood that the values of the test instructions configured in the third configuration register 103 are not limited to the above h0 to h8, and there can be other configuration values to represent other operation types and test directions, such as write-then-read operations in the word line direction, write-then-read operations in the bit line direction, etc. The present invention does not make specific limitations on this.

[0039] In addition, when the test direction indicated by the test instruction cmd_t in the third configuration register 103 is the word line WL direction, after activating the corresponding word line WL in the three-dimensional stacked memory chip 1 and writing data of a predetermined number (for example, 1 burst) of test vectors (a test pattern, for example, 1 test pattern includes 1 byte of data), the address in the bit line BL direction (i.e., the column address) automatically points to the next bit line BL (i.e., the column address is incremented); when the test direction indicated by the test instruction cmd_t in the third configuration register 103 is the bit line direction, after writing data of a predetermined number (for example, 1 burst) of test vectors (1 test vector includes 1 byte of data), the address in the word line direction (i.e., the row address) automatically points to the next word line (i.e., the row address is incremented). Thus, when testing 1 functional parameter of the three-dimensional stacked memory chip 1 using the memory test device of this embodiment, the entire memory array of the corresponding 1 storage unit in the three-dimensional stacked memory chip 1 can be read / written / write-then-read / read-then-write / refreshed, etc. The specific operations depend on which test instructions cmd_t are configured in the third configuration register 103. Here, 1 burst refers to the number of data blocks that the three-dimensional stacked memory chip 1 (for example, DRAM) can transfer in one access, and the length of 1 burst is, for example, 8 / 34 / 64 bytes.

[0040] For another example, when the test direction represented by the test instruction in the third configuration register 103 is the word line direction, different configuration values in the second configuration register 102 can achieve: (1) Basic mode; this basic mode includes any suitable at least one test mode such as all 0 (0x00) mode, all 1 (0xFF) mode, checkerboard (0xAA / 0x55) mode, etc. (or the test pattern is 0x00, 0xFF, 0xAA, 0x55); (2) Extended mode; this extended mode includes at least one of the inter-row alternating mode (writing complementary data to adjacent rows) and the word line adjustable step number (for example, the step number step can be 0 / 1 / 2 / 4 / 8 / 16 / 32) mode, and the step jump method is adjustable through the configuration of the second configuration register 102 (for example, when activating row x, precharge row x±1 / 2 / 4 / 8).

[0041] For another example, when the test direction indicated by the test instruction in the third configuration register 103 is the bit line direction, different configuration values in the second configuration register 102 can achieve the following: (1) The even-odd column alternating activation test mode: write 0x00 to the even columns and write 0xFF to the odd columns; (2) The diagonal column interference test mode: when activating column y, apply reverse data to columns y+1 / 2 / 4 / 8 through configuration.

[0042] In this embodiment, a built-in self-test (BIST) process is embedded in the built-in self-test module 104. The built-in self-test module 104 is used to receive test stimuli applied by a test host, and in the test gear configured in the first configuration register 101 and the test mode configured in the second configuration register 102, activate the corresponding word line WL or bit line BL in the three-dimensional stacked memory chip 1 according to the test instruction configured in the third configuration register 103, so as to execute the corresponding built-in self-test process and test the current functional parameters of the three-dimensional stacked memory chip 1. Among them, the configuration value of at least one of the first configuration register 101, the second configuration register 102, and the third configuration register 103 can be adjusted according to the test result of the built-in self-test module 104. The specific implementation of this adjustment can be achieved through the test program of the test host 2 or automatically by the memory test device 10a.

[0043] In an example, the built-in self-test process in the built-in self-test module 104 includes: Writing test vector data into the three-dimensional stacked memory chip 1, for example, writing "0" (e.g., data is 0x00) or "1" (e.g., data is 0xFF) to the entire memory array of the corresponding storage unit unit, or writing "0" or "1" in a checkerboard pattern (e.g., data is the cross of 0xAA and 0x55), etc.; Reading out the corresponding data in the three-dimensional stacked memory chip 1 and comparing whether the read data is consistent with the written data (as shown in step S4 in Figure 7 ); If they are consistent, the configuration value in the first configuration register 101 is adjusted to reduce the test gear, so that the built-in self-test module 104 re-tests the current functional parameters of the three-dimensional stacked memory chip 1 at the reduced test gear; If they are inconsistent, perform a Shmoo plot analysis on the current test result (as shown in Figure 6 ) to determine the final value of the current functional parameter, and thus complete the test of the current functional parameter (as shown in Figure 7as shown in step S5 in (). Among them, the Shmoo plot is a key analysis method in semiconductor manufacturing and integrated circuit testing. During testing, the current functional parameters of the three-dimensional stacked memory chip 1 are repeatedly tested within a specific parameter range (for example, the bit line voltage margin), and the pass / fail results are recorded, and a two-dimensional visualization chart between the two variables of the current functional parameter and the specific parameter can be generated.

[0044] Optionally, after the built-in self-test module 104 completes the test of the current functional parameter, the configuration values of at least one of the first configuration register 101, the second configuration register 102, and the third configuration register 103 are adjusted so that the built-in self-test module 104 tests the next functional parameter of the three-dimensional stacked memory chip 1.

[0045] Among them, when changing to the next functional parameter test, the test mode and test instructions (that is, the configuration values of the second configuration register 102 and the third configuration register 103) may both need to be adjusted. At this time, the test program of the test host 2 or the built-in self-test module 104 of the memory test device 10a can be used to select the functional parameter with the configuration value closest to the configuration value when the previous functional parameter test is completed as the next test functional parameter.

[0046] In an example, the built-in self-test process executed by the built-in self-test module 104 in the word line WL direction further includes at least one of the following operations (1) to (4): (1) Perform a voltage gradient scan on the corresponding word lines in the three-dimensional stacked memory chip 1 with a corresponding voltage step. For example, the step range of the applied excitation voltage VPP: 2.5V to 3.3V, and the voltage step is 50mV.

[0047] (2) Perform negative over-driving on the corresponding word line WL in the three-dimensional stacked memory chip 1 to detect leakage through a reverse bias voltage (for example, -100mV).

[0048] (3) Update the reference voltage VREF once every preset number of writes (for example, 32 times) in the three-dimensional stacked memory chip 1 to achieve dynamic reference voltage VREF calibration.

[0049] (4) Add a row interference test enhancement test instruction to the current functional parameter test, and the row interference test enhancement test instruction is used to implement the coupling test between adjacent word lines and / or the insertion of a refresh interval in the three-dimensional stacked memory chip.

[0050] In an example, the built-in self-test process executed by the built-in self-test module 104 in the bit line BL direction further includes at least one of the following operations (1) to (3): (1)Dynamically adjust the bias voltage VBL (which is also the bit line voltage) of the sense amplifier for reading corresponding data in the three-dimensional stacked memory chip. For example, in the normal mode: VBL = 0.5VDDQ; in the extreme test mode: VBL is scanned from 0.45VDDQ to 0.55VDDQ. Here, the voltage VDDQ is the supply voltage of the input / output interface circuit of the three-dimensional stacked memory chip 1, which is mainly used to drive data transmission between the memory controller 10 of the three-dimensional stacked memory chip 1 and external devices (such as the CPU).

[0051] (2)Inject jitter into the enable timing of the sense amplifier (SA) for reading corresponding data in the three-dimensional stacked memory chip 1. For example, add ±20ps timing perturbation within the tRCD window. tRCD (RAS to CAS Delay) is the row-to-column delay time, that is, the delay time from row address strobe (RAS) to column address strobe (CAS). In the operation of the three-dimensional stacked memory chip 1, tRCD is an important timing parameter of the three-dimensional stacked memory chip 1, which determines the minimum time interval required from activating a row address of the three-dimensional stacked memory chip 1 to reading or writing the column address in that row.

[0052] (3)Apply high-speed data transitions (such as alternating between 0→1 and 1→0), and measure the bit line voltage rise time to achieve bit line slew rate testing. During the bit line slew rate testing, an on-chip time-voltage converter (TVC) can be used for bit line sampling, and the sampling point density is, for example, one measurement point every 10ps.

[0053] The memory test device 10a of this embodiment can test any suitable one or more functional parameters of the three-dimensional stacked memory chip 1. These functional parameters include at least one timing parameter, and these timing parameters can include at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, tFAW, etc. Each timing parameter can be selected to be measured in the word line WL direction or in the bit line BL direction. That is to say, when writing the test vector data, operations such as write / read / read-after-write / write-after-read / refresh can be performed in the order of increasing row address (test direction is the bit line BL direction), or operations such as write / read / read-after-write / write-after-read / refresh can be performed in the order of increasing column address (test direction is the word line WL direction).

[0054] Among them, tRAS (Active to Precharge Delay) represents the minimum time interval between issuing a row activation command and being able to issue a row precharge command. This interval is also measured in clock cycles tck. In the operation of 3D stacked memory chips 1 such as DRAM, each data access starts with row activation, and a specific row selection command is used to activate the required data row. Subsequently, the system accesses a specific column address in that row for data reading or writing. Once the data access is completed, in order to release resources and prepare for the next access, the system issues a row precharge command to close the current row. And tRAS strictly stipulates the shortest time interval between row activation and row precharge. For system performance, a smaller tRAS value means that the 3D stacked memory chip 1 can complete the conversion from row activation to row precharge more quickly, thereby improving the data access speed and overall system performance. tRCD (Row Command Delay) refers to the minimum time interval between issuing a row activation (Active) command and being able to issue a column address strobe command (which is also the time for data to transfer from the storage unit of the 3D stacked memory chip 1 such as DRAM to the sense amplifier (SA) after a row is activated). This interval is measured in clock cycles tck. During the addressing process of the 3D stacked memory chip 1, generally, the bank address of the memory bank, the unit address of the storage unit are first determined, followed by the row address, and finally the specific cell is located through the column address. In actual operation, the bank address of the memory bank, the unit address of the storage unit and the corresponding row address are issued synchronously, and this process is called "row activation". After row activation is completed, a column address addressing command and corresponding operation instructions are issued to indicate whether it is a read operation or a write operation, and these two commands can be collectively referred to as "read / write commands".

[0055] ‌tCOLOFF2WLOFF (column off to WL off Delay) refers to the minimum time interval between the invalidation of the column address strobe command and the invalidation of the row activation command. This interval is measured in clock cycles tck.

[0056] tRP (Row Precharge Time) represents the minimum time interval between issuing a row precharge command and being able to issue a row activation command again. This interval is also measured in clock cycles tck. In the operation of 3D stacked memory chips 1 such as DRAM, each data access requires first activating a row and then reading or writing data through column addresses. When a row of data access is completed, in order to release resources and prepare for the next access, a row precharge command needs to be issued to close the current row. And tRP defines the shortest time required from closing one row to being able to activate another row. Regarding the impact on performance, a smaller tRP value means that the 3D stacked memory chip 1 can complete row switching in a shorter time, thus improving access speed and overall performance.

[0057] tWR (Write Recovery Time) refers to the shortest time interval from issuing the last write command to being able to issue a row precharge command. This interval is also measured in clock cycles. In the working process of DDR memory, after a data write operation is completed, in order to ensure that the data can be correctly stored in the storage unit, a certain recovery time must be given. And tWR exists precisely to define such a recovery time interval. Through it, we can ensure that there is sufficient time for data recovery after the write operation is completed, thus avoiding possible data errors.

[0058] tCAS (Column Access Time) refers to the shortest time that the CAS signal used to lock the column address and initiate a read or write operation must remain active, and this time is measured in clock cycles tck. For most memory operations such as 3D stacked memory chips 1 like DRAM, the CAS signal must also remain inactive for at least tCP time before being reactivated.

[0059] tCL (CAS Latency) is the time interval from the memory controller 10 issuing a read command to the first data being available, measured in clock cycles tck. A smaller tCAS value means a faster memory response speed.

[0060] tWTR (Write to Read Delay) represents the shortest time interval required from the execution of a write command to the ability to issue a read command. This interval is also measured in clock cycles tck. In a three-dimensional stacked memory chip 1 such as DRAM, it reflects the number of clock cycles that the same cell must wait after the last valid write operation until the next read operation. During the operation of a three-dimensional stacked memory chip 1 such as DRAM, a certain time interval must be maintained between the write and read operations to ensure that the newly written data can be correctly stored and will not interfere with subsequent read operations. The existence of tWTR is precisely to define such a necessary time interval, thus ensuring sufficient recovery time after the write operation is completed and avoiding possible data errors.

[0061] tRC (Row Cycle Time) refers to the shortest time interval from the issuance of an activation command for a row to the issuance of an activation command for the same row again. This interval is measured in clock cycles tck, and its calculation formula is: tRC = tRAS + tRP. The size of tRC directly affects the row switching speed of the memory, and thus is related to the overall performance of the system. The smaller tRC is, the faster the row switching speed of the memory is, and the better the performance of the system is.

[0062] tRFC (Row Refresh Cycle Time) represents the shortest time interval from the issuance of a row refresh command to the issuance of the next row refresh command. This interval is measured in nanoseconds, and its function is to ensure that all data rows in the memory can be refreshed within a predetermined cycle.

[0063] tCCD (CAS to CAS Delay) refers to the time interval between CAS commands, representing the timing of the minimum burst duration, or the minimum column-to-column command timing tRTP (Read to Precharge Delay) refers to the time interval between the completion of a read operation and the start of precharge.

[0064] tFAW (Four Activation Window) refers to the minimum time interval of row strobe commands issued within the same refresh cycle.

[0065] These above-mentioned timing parameters jointly determine the performance and stability of a three-dimensional stacked memory chip 1 such as DRAM, and are crucial for the design and optimization of the memory system.

[0066] Based on the same inventive concept, please refer to Figures 1 to 4, this embodiment also provides a memory test system, which includes: a three-dimensional stacked memory chip 1, a test host 2, and the memory test device 10a as described in this embodiment. Among them, the three-dimensional stacked memory chip 1 includes a memory controller 10 and n + 1 layers of memory dies D0~Dn stacked together. The memory test device 10a is embedded in the memory controller 10, or the memory test device 10a is arranged in the main control chip outside the three-dimensional stacked memory chip 1.

[0067] In one example, please refer to Figure 1 As shown, the test host 2 can be a test machine before the three-dimensional stacked memory chip 1 leaves the factory. It can be coupled to the memory test device 10a through a probe card to apply corresponding test stimuli to the memory test device 10a, so that the memory test device 10a can activate the corresponding word line WL or bit line BL in the three-dimensional stacked memory chip 1, and then test the corresponding functional parameters of the three-dimensional stacked memory chip 1.

[0068] In another example, please refer to Figure 1 and Figure 2 , the test host 2 can also be the main control chip after the three-dimensional stacked memory chip 1 leaves the factory. The memory test device 10a can be integrated in the memory controller 10 of the three-dimensional stacked memory chip 1 or outside the main control chip, so as to apply corresponding test stimuli to the memory test device 10a, so that the memory test device 10a can activate the corresponding word line WL or bit line BL in the three-dimensional stacked memory chip 1, and then test the corresponding functional parameters of the three-dimensional stacked memory chip 1.

[0069] Based on the same inventive concept, please refer to Figure 7 and combine with Figures 1 to 6 , this embodiment also provides a memory test method, which includes the following steps: S1, provide the memory test device 10a as described in this embodiment and the three-dimensional stacked memory chip 1 to be tested. The memory test device 10a can be arranged outside the three-dimensional stacked memory chip 1 or embedded in the memory controller 10a inside the three-dimensional stacked memory chip 1. The memory test device 10a embeds corresponding built-in self-test (BIST) processes (for example, test processes including adjustable timing parameter ranges such as tRP, tRCD, tRAS, etc.), a first configuration register 101, a second configuration register 102, and a third configuration register 103; S2, determine the current functional parameter to be tested and its test direction; S3. Write corresponding configuration values to the first configuration register 101 to configure the test gear of the current functional parameter, write corresponding configuration values to the second configuration register 102 to configure the test mode corresponding to the current functional parameter, and write corresponding configuration values to the third configuration register 103 to configure the test instruction of the current functional parameter. At least one of the test directions and operation types indicated by different test instructions is different; S4. Apply corresponding test stimuli to the memory test device 10a through the test host 3. The memory test device 10a receives the test stimuli and, under the test gear configured in the first configuration register 101 and the test mode configured in the second configuration register 102, activates the corresponding word line WL or bit line BL in the three-dimensional stacked memory chip 1 according to the test instruction configured in the third configuration register 103 to execute the corresponding built-in self-test process and test the current functional parameter of the three-dimensional stacked memory chip 1. Data of test vectors can be written into the three-dimensional stacked memory chip 1. For example, the entire memory array array of the corresponding storage unit unit is written with all "0" (e.g., data is 0x00) or all "1" (e.g., data is 0xFF) or written with "0" or "1" in a checkerboard pattern (e.g., data is the intersection of 0xAA and 0x55), etc.; S5. Read out the corresponding data in the three-dimensional stacked memory chip 1 and compare whether the read data is consistent with the written data (i.e., compare whether the read value is consistent with the expected value); If they are consistent, return to S3 to adjust the configuration value in the first configuration register 101, and then reduce the test gear (e.g., reduce by one gear). Thus, repeat the operations of S4 - S5 to re-execute the above-mentioned built-in self-test process at the reduced test gear to re-test the current functional parameter of the three-dimensional stacked memory chip 1 until it is determined in S5 that the read data is inconsistent with the written data; If they are inconsistent, execute S6 to perform a Shmoo plot analysis on the current test result, as Figure 6 shown, to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter; S7. Determine whether the current functional parameter is the last functional parameter to be tested. If so, end the test. If not, return to S2 and then repeat the operations of S3 - S7 to test the next functional parameter of the three-dimensional stacked memory chip 1. Among them, in step S3, it is necessary to adaptively adjust the configuration values of at least one of the first configuration register 101, the second configuration register 102, and the third configuration register 103 according to the result of S2 to meet the requirements for testing the next functional parameter.

[0070] Thus, through the above test method, various functional parameters required for testing can be completed, and the final values of various functional parameters can be determined, so as to adjust the three-dimensional stacked memory chip 1 to its optimal performance.

[0071] It should be understood that among the various functional parameters that the memory test device 10a can test, some are suitable for testing in the word line direction, and some are suitable for testing in the bit line direction. The above test process can dynamically adjust the configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103 according to the test requirements, and then the corresponding functional parameters in the word line WL direction or the bit line BL direction can be tested. That is, after configuring the test gear, test mode, and test instruction (this test instruction can represent the test direction and operation type) through the first configuration register 101, the second configuration register 102, and the third configuration register 103, the storage test device 10 can realize the automatic test of the corresponding functional parameters of the three-dimensional stacked memory chip.

[0072] These functional parameters may include at least one timing parameter, and these timing parameters may include at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, tFAW, etc.

[0073] For example, when testing timing parameters such as tRP, tRCD, and tRAS, in step S1, the BIST test process of these timing parameters is pre-embedded in the memory test device 10a. In step S2, it is determined that the timing parameters such as tRP, tRCD, and tRAS are suitable for testing in the word line WL direction. In step S3, by configuring the configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103, the test gear, test mode, and test direction are prepared. Then, in step S4, under the configured test mode and test direction, the three-dimensional stacked memory chip 1 is activated row by row and a voltage is applied (i.e., a test excitation is applied) to write data into the corresponding storage unit of the three-dimensional stacked memory chip 1, and the read data is compared with the written data. If the data is consistent, return to step S3, and by adjusting the configuration value of the first configuration register, the test gear of this timing parameter is reduced by one gear, and the above operation is repeated until the comparison between the written data and the read data is inconsistent. Then, in step S5, the test result is analyzed through a Shmoo plot, and in step S6, the tightest timing of this timing parameter is determined according to the analysis result.

[0074] Among them, the test pattern in the word line direction can be configured as a basic mode or an extended mode. The basic mode can be any suitable mode such as all 0s (0x00), all 1s (0xFF), checkerboard (0xAA / 0x55), etc. The extended mode can be an inter - row alternating mode (writing complementary data to adjacent rows), a word line WL adjustable step mode, and the jump method can be adjusted through configuration (pre - charging row n±1 / 2 / 4 / 8 when activating row n). During the test, any suitable operations such as voltage control, adding row interference test to enhance test instructions can be performed, for example, any suitable operations such as word line WL voltage gradient scanning, negative over - drive, dynamic VREF calibration, etc. can be performed. For details, refer to the above description.

[0075] For another example, for timing parameters such as tRCD, tCOLOFF2WLOFF, tRP, etc., it is suitable to perform tests in the bit line BL direction. In step S1, the BIST test process of these timing parameters is pre - embedded in the memory test device 10a. In step S2, it is determined that the timing parameters such as tRCD, tCOLOFF2WLOFF, tRP, etc. are suitable for testing in the bit line BL direction. In step S3, by configuring the configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103, the test gear, test mode, test direction, etc. are prepared. Then, in step S4, under the configured test mode and test direction, the three - dimensional stacked memory chip 1 is activated row - by - row and voltage is applied (i.e., test excitation is applied) to write data into the corresponding storage units of the three - dimensional stacked memory chip 1, and the read - out data is compared with the written data. If the data is consistent, return to step S3, and by adjusting the configuration value of the first configuration register, the test gear of this timing parameter is reduced by one gear, and the above operations are repeated until the comparison between the written data and the read - out data is inconsistent. Then, in step S5, the test results are analyzed through a Shmoo plot, and in step S6, the tightest timing of this timing parameter is determined according to the analysis results.

[0076] Among them, the test pattern in the bit line direction can be configured as any suitable mode such as an even - odd column alternating activation mode (writing 0x00 to even columns and 0xFF to odd columns) or a diagonal column interference test mode (when activating column m, applying reverse data to column m + 1 / 2 / 4 / 8 through configuration).

[0077] During the test, the bias voltage VBL of the sense amplifier (SA, also known as the sensitive amplifier or sense amplifier) can be dynamically adjusted. For example, in the normal mode: VBL = 0.5VDDQ; in the extreme test mode: VBL is scanned from 0.45VDDQ to 0.55VDDQ. The sense amplifier enable timing jitter injection can also be performed. For example, ±20 ps timing perturbations are added within the tRCD window. The bit line slew rate test can also be carried out. For example, high-speed data transitions (alternating between 0→1 and 1→0) are applied, and the on-chip time-voltage converter (TVC) is used to measure the bit line BL voltage setup time at a sampling density of one measurement point per 10 ps, and then a Shmoo plot is established based on the measurement results. Thus, for the test results, through the analysis of the Shmoo plot, the final values of the timing parameters of the current test can be determined. After testing each timing parameter, the three-dimensional stacked memory chip can be adjusted to the best performance.

[0078] For example, in one example, the Shmoo plot established according to the measurement results is specifically as Figure 6 shown in the table in. The Shmoo plot generates a two-dimensional visualization chart showing the relationship between two variables, namely the bit line voltage VBL margin and tRCD. During the test, the memory test device 1 repeatedly tests the three-dimensional stacked memory chip 1 at the corresponding bit line voltage VBL margin, records the test results of pass (PASS) / fail (FAIL), and then determines the final value of the timing parameter tRCD of the current test.

[0079] In summary, the memory test device, three-dimensional stacked memory chip, memory test method, and test system provided by the present invention embed the built-in self-test (BIST) test process and the first to third configuration registers in the memory test device. Thus, only the specified test stimuli need to be applied on the test host to automatically implement the test of the corresponding functional parameters of the three-dimensional stacked memory chip. Moreover, the switching of the functional parameters, test directions, and test modes only needs to adjust the configuration values in the first to third configuration registers. Therefore, the test process of the functional parameters of the memory is optimized, and the test time and test cost are greatly saved.

[0080] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the protection scope of the technical solution of the present invention.

Claims

1. A memory test device, which is embedded in a three-dimensional stacked memory chip or disposed outside the three-dimensional stacked memory chip, the three-dimensional stacked memory chip comprising a plurality of memory dies stacked together, characterized in that, The memory test device is embedded with: A first configuration register for configuring the test gear of the current functional parameter to be tested; A second configuration register for configuring the test mode corresponding to the current functional parameter; A third configuration register for configuring the test instruction of the current functional parameter, with at least one of the test directions and operation types indicated by different test instructions being different; A built-in self-test module, which is embedded with a built-in self-test process and is used to receive corresponding test stimuli, and under the test gear configured by the first configuration register and the test mode configured in the second configuration register, activate corresponding word lines or bit lines in the three-dimensional stacked memory chip according to the test instruction configured in the third configuration register to execute the built-in self-test process and test the current functional parameter of the three-dimensional stacked memory chip; Wherein, the configuration value of at least one of the first configuration register, the second configuration register and the third configuration register is adjusted according to the test result of the built-in self-test module.

2. The memory test device according to claim 1, wherein The built-in self-test process includes: Writing data of a test vector into the three-dimensional stacked memory chip; Reading out the corresponding data in the three-dimensional stacked memory chip and comparing whether the read data is consistent with the written data; If they are consistent, the configuration value in the first configuration register is adjusted to reduce the test gear, so that the built-in self-test module re-tests the current functional parameter of the three-dimensional stacked memory chip under the reduced test gear.

3. The memory test device according to claim 2, wherein If the read data is inconsistent with the written data, the built-in self-test module is further used to perform a Shmoo plot analysis on the test result to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter.

4. The memory test device according to any one of claims 1 to 3, characterized in that, After the built-in self-test module completes the test of the current functional parameter, the configuration value of at least one of the first configuration register, the second configuration register and the third configuration register is adjusted to enable the built-in self-test module to test the next functional parameter of the three-dimensional stacked memory chip.

5. The memory test device according to any one of claims 1-3, characterized in that, When the test direction indicated by the test instruction in the third configuration register is the word line direction, after activating the corresponding word line and writing data of a predetermined number of test vectors, the address in the bit line direction automatically points to the next bit line; When the test direction indicated by the test instruction in the third configuration register is the bit line direction, after writing data of a predetermined number of test vectors, the address in the word line direction automatically points to the next word line.

6. The memory test device according to claim 5, wherein When the test direction is the word line direction, different configuration values in the second configuration register can implement a basic mode and an extended mode. The basic mode includes at least one of an all-0 mode, an all-1 mode, and a checkerboard mode, and the extended mode includes at least one of an inter-row alternating mode and a word line adjustable step mode; And / or, when the test direction is the bit line direction, different configuration values in the second configuration register can implement an odd-even column alternating activation test mode and a diagonal column interference test mode.

7. The memory test device according to claim 5, wherein, The built-in self-test process performed in the word line direction further includes at least one of the following operations (1) to (4): (1) Performing a voltage gradient scan on corresponding word lines in the three-dimensional stacked memory chip with corresponding voltage steps; (2) Performing negative over-driving on corresponding word lines in the three-dimensional stacked memory chip to detect leakage through reverse biasing; (3) Updating the reference voltage once every preset number of writes are completed in the three-dimensional stacked memory chip; (4) Adding a row interference test enhancement test instruction to the current functional parameter test, and the row interference test enhancement test instruction is used to implement the coupling test of adjacent word lines and / or the insertion of refresh intervals in the three-dimensional stacked memory chip.

8. The memory test device according to claim 5, wherein The built-in self-test process performed in the bit line direction further includes at least one of the following operations (1) to (3): (1) Dynamically adjusting the bias voltage of the sense amplifier for reading corresponding data in the three-dimensional stacked memory chip; (2) Injecting enable timing jitter into the sense amplifier for reading corresponding data in the three-dimensional stacked memory chip; (3) Applying a high-speed data transition and measuring the bit line voltage establishment time to implement the bit line slew rate test.

9. The memory test device according to any one of claims 1-3 and 6-8, characterized in that, The current functional parameters include at least one timing parameter, and the timing parameter includes at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, tFAW.

10. The memory test device according to any one of claims 1-3 and 6-8, characterized in that, The three-dimensional stacked memory chip further includes a memory controller, the memory test device is embedded in the memory controller, the memory controller is disposed on the buffer die, and the multi-layer memory dies are bonded together through through-silicon vias and hybrid bonding between them and with the buffer die; or, the memory test device is disposed in the main control chip outside the three-dimensional stacked memory chip.

11. A three-dimensional stacked memory chip, characterized in that, It includes a memory controller and multi-layer memory dies stacked together, and the memory test device as described in any one of claims 1-10 is embedded in the memory controller.

12. A memory test system, characterized in that, It includes: A three-dimensional stacked memory chip, a test host, and the memory test device as described in any one of claims 1-10; wherein, the three-dimensional stacked memory chip includes a memory controller and multi-layer memory dies stacked together, the memory test device is embedded in the memory controller, or the memory test device is disposed in a test chip outside the three-dimensional stacked memory chip, and the test host applies corresponding test stimuli to the memory test device to activate corresponding word lines or bit lines in the three-dimensional stacked memory chip, and then performs corresponding functional parameter tests on the three-dimensional stacked memory chip.

13. A memory testing method, characterized in that, It includes the following steps: Provide a memory test device and a three-dimensional stacked memory chip to be tested as described in any one of claims 1-10, wherein the memory test device is arranged outside the three-dimensional stacked memory chip or embedded in a memory controller inside the three-dimensional stacked memory chip, and a corresponding built-in self-test process, a first configuration register, a second configuration register, and a third configuration register are embedded in the memory test device; Determine the current function parameter to be tested and its test direction, and configure the test gear of the current function parameter by writing corresponding configuration values into the first configuration register, configure the test mode corresponding to the current function parameter by writing corresponding configuration values into the second configuration register, and configure the test instruction corresponding to the current function parameter by writing corresponding configuration values into the third configuration register. At least one of the test directions and operation types indicated by different test instructions is different; Apply corresponding test stimuli to the memory test device through a test host. The memory test device receives the test stimuli and, under the test gear configured in the first configuration register and the test mode configured in the second configuration register, activates corresponding word lines or bit lines in the three-dimensional stacked memory chip according to the test instruction configured in the third configuration register to execute the built-in self-test process and test the current function parameter of the three-dimensional stacked memory chip.

14. The memory testing method according to claim 13, wherein, The built-in self-test process includes: Write the data of the test vector into the three-dimensional stacked memory chip; Read out the corresponding data in the three-dimensional stacked memory chip and compare whether the read data is consistent with the written data; If they are consistent, adjust the configuration value in the first configuration register to reduce the test gear, and then, under the reduced test gear, re-execute the built-in self-test process until the read data is inconsistent with the written data; If they are inconsistent, perform a Shmoo plot analysis on the current test result to determine the final value of the current function parameter, and then complete the test of the current function parameter; After completing the test of the current function parameter, determine whether the current function parameter is the last function parameter to be tested. If so, end the test. If not, adjust the configuration value of at least one of the first configuration register, the second configuration register, and the third configuration register to test the next current function parameter of the three-dimensional stacked memory chip.

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