Method for realizing heterogeneous integrated preparation of through silicon via based on vanadium dioxide

Abstract

The invention discloses a heterogeneous integration preparation method for realizing a silicon through hole based on vanadium dioxide, and relates to the technical field of nano devices, and the method comprises the following steps: S1, sequentially sputtering a bottom metal coating, a vanadium dioxide coating and a top metal coating on an etching substrate; s2, coating positive photoresist on the etching substrate slice, forming a through-silicon-via hole contour, removing part of the bottom metal coating by dry etching, and stripping a positive photoresist layer; s3, performing magnetic field induced etching on the three layers of catalytic bodies containing vanadium dioxide on the substrate sheet to realize directional etching of the through silicon via; s4, insulating layer deposition, barrier layer deposition, seed layer deposition and electrocoppering layer backfilling are sequentially carried out on the silicon through holes in the etching substrate slice; and S5, stacking the plurality of etched substrate slices to realize heterogeneous integration. According to the method, the depth-to-width ratio of etching can be remarkably improved, the etching shape can be greatly kept especially in a deep silicon etching scene, a vertical etching scene and a certain inclination angle scene, and the roughness of the side wall of the etched silicon through hole structure is small.

Description

Technical Field

[0001] The invention relates to the technical field of nano devices, and in particular to a heterogeneous integrated preparation method for silicon through vias based on vanadium dioxide. Background Art

[0002] With the continuous development of the semiconductor industry, the integration density of electronic components continues to increase, and more components can be integrated into a given area by continuously reducing the minimum component size. Through silicon vias that can be used for heterogeneous integration technology are a solution to improve integration and can meet the above needs. Through silicon vias enable stacked chips in three-dimensional integrated circuits to be interconnected. And it has the advantages of small size, high density, high integration, and small interconnection delay. The use of through silicon vias can greatly reduce the size and weight of electronic devices. However, the preparation of traditional through silicon vias is limited in terms of aspect ratio and etching rate.

[0003] Traditional silicon through-hole vias usually adopt dry etching process, among which inductively coupled plasma etching (ICP) is the mainstream. However, the achievable depth of ICP etching in deep silicon etching is limited by some factors. At the same time, the etching rate of ICP etching is not easy to control. As the aspect ratio or depth increases, the etching rate decreases significantly. When the depth of ICP etching exceeds 200μm, etching becomes difficult and the etching track bends. The maximum aspect ratio of ICP etching is only 30:1, which is difficult to meet the high requirements of microelectronics technology for through-hole aspect ratio. In addition, due to the relatively high cost and complex process, production efficiency is reduced. Another adverse side effect of ICP etching is the damage of ions to the sidewalls and bottom of the semiconductor, which is easy to produce microgrooves and increase surface roughness. After ions enter the surface of the sample, they form carrier traps, which will cause lattice defects or impurities. For some special electronic devices that rely on surface conductivity and carrier distribution, the ion damage formed by reactive ion etching will change the performance of these devices. Subsequent processes such as annealing or wet chemical etching are required to remove the damage.

[0004] Secondly, the wet etching process can be used, which has a relatively simple process and relatively low cost. Wet etching uses a liquid etching medium, which is usually a chemically reactive solution or acid-base mixture. These solutions can react chemically with the material to be etched to achieve etching. However, due to its low etching rate, it is extremely dependent on the role of catalysts. Common catalysts for wet etching are mostly acids. For example, the addition of acetic acid can inhibit the decomposition of nitric acid in the silicon dioxide etching solution, thereby increasing the reaction rate. The hot phosphoric acid solution at 150-170°C can catalyze the etching rate of silicon nitride to reach However, even with the addition of a catalyst, it is difficult for conventional wet etching of vias in silicon to meet the requirements of a high aspect ratio (>50:1), and there are problems with the recovery and treatment of reaction waste liquid. Improper treatment will make it difficult to ensure the safety of operators and cause environmental pollution. Summary of the Invention

[0005] Based on the technical problems existing in the background art, the present invention proposes a heterogeneous integration preparation method for vias in silicon based on vanadium dioxide, which can significantly improve the aspect ratio of etching. Especially in the scenarios of deep silicon etching, vertical etching, and etching at a certain inclination angle, it can greatly maintain the etching shape, and the sidewall roughness of the etched via structure in silicon is small.

[0006] The heterogeneous integration preparation method for vias in silicon based on vanadium dioxide proposed by the present invention has the following method steps:

[0007] S1: Evaporate and sputter a bottom metal coating, magnetron sputter a vanadium dioxide coating, and evaporate and sputter a top metal coating on the etched substrate wafer in sequence;

[0008] S2: Coat a positive photoresist on the side of the top metal coating away from the vanadium dioxide coating, and open the via hole contour in the positive photoresist layer. Dry-etch and remove the bottom metal coating, vanadium dioxide coating, and top metal coating located outside the via hole contour, and strip the positive photoresist layer;

[0009] S3: Place the etched substrate wafer processed in S2 into a reaction chamber containing an etching solution, and induce the three-layer catalytic body of bottom metal coating - vanadium dioxide coating - top metal coating containing vanadium dioxide through a magnetic field to achieve directional etching of the etched substrate wafer to form vias in silicon;

[0010] S4: Remove the bottom metal coating, vanadium dioxide coating, and top metal coating in the vias in silicon, and sequentially deposit an insulating layer, a barrier layer, a seed layer, and backfill with an electroplated copper layer in the vias in silicon;

[0011] S5: Stack multiple etched substrate wafers to achieve heterogeneous integration.

[0012] Preferably, the etched substrate wafer is one of silicon, germanium, silicon carbide, gallium arsenide, and gallium nitride.

[0013] Preferably, the bottom metal coating is titanium with a thickness of 3 - 15 nm.

[0014] Preferably, the thickness of the vanadium dioxide coating is 10 - 50 nm.

[0015] Preferably, the top metal coating is gold with a thickness of 3 - 15 nm.

[0016] Preferably, the etching temperature is 70 - 100 °C.

[0017] Preferably, the insulating layer is silicon nitride with a thickness of 10 - 30 nm.

[0018] Preferably, the barrier layer is titanium nitride with a thickness of 10 - 30 nm.

[0019] Preferably, the seed layer is copper with a thickness of 1 - 100 nm.

[0020] Advantageous technical effects of the present invention:

[0021] (1) Traditional through - silicon vias use inductively coupled plasma etching technology. However, as the etching depth increases, the etching trajectory is difficult to control, and the roughness of the etched sidewalls increases significantly. The present invention utilizes vanadium dioxide - assisted chemical etching technology, which can significantly improve the aspect ratio of etching, reaching more than 90:1. Especially in deep silicon etching scenarios, vertical etching, and certain inclined - angle scenarios, it can greatly maintain the etching shape, and the roughness of the sidewalls of the etched through - silicon via structure is less than 10 nm. Moreover, it controls the etching direction by converting current into magnetic field, and the process is simple.

[0022] (2) The present invention uses a three - layer catalyst body (metal - vanadium dioxide - metal) containing vanadium dioxide as a catalyst. Due to the phase - change characteristics of vanadium dioxide, the start and stop of hole transport can be controlled, and based on the metal - assisted chemical etching mechanism, the occurrence and stop of the reaction can be controlled by etching temperature, realizing the autonomous control of the etching process. At the same time, it has low manufacturing cost, fast catalytic rate, easy recovery and treatment, better performance than traditional acid - base catalysts, and is applicable to the etching catalysis of a variety of different semiconductor materials, with good versatility and chemical selectivity.

[0023] (3) The present invention controls the magnitude of the current applied to the Helmholtz coil, the type and thickness of the metal catalyst, and the ratio of the etching solution to change the etching rate, meeting the requirements of etching different chips and etching silicon deep holes with different depths on the chips. At the same time, by controlling the magnitude of the current passing through three pairs of six - direction Helmholtz coils, three - dimensional vector etching inside the chip can be achieved, which can be applied to a variety of etching scenarios. Description of the Drawings

[0024] Figure 1 It is a schematic structural diagram of an etching substrate for the etched through - silicon via hole contour after sputtering the bottom - layer metal plating, vanadium dioxide plating, and top - layer metal plating and coating positive photoresist in Embodiment 1 proposed by the present invention;

[0025] Figure 2 It is a schematic structural diagram of a three - layer catalyst body structure cluster containing vanadium dioxide after removing the positive photoresist and part of the bottom - layer metal plating in Embodiment 1 proposed by the present invention;

[0026] Figure 3Cross-sectional view of the etched substrate wafer of Example 1 proposed by the present invention after being etched by a three-layer catalyst body containing vanadium dioxide;

[0027] Figure 4 Cross-sectional view of the through-silicon via of Example 1 proposed by the present invention after forming an insulating layer, a barrier layer, and a seed layer therein;

[0028] Figure 5 Schematic diagram of the metal backfill of the through-silicon via of Example 1 proposed by the present invention;

[0029] Figure 6 Schematic diagram of the scene of the etched substrate wafer of Example 1 proposed by the present invention;

[0030] Figure 7 Schematic diagram of the metal backfill of the through-silicon via of Example 2 proposed by the present invention;

[0031] Figure 8 Schematic diagram of the scene of the etched substrate wafer of Example 2 proposed by the present invention.

[0032] In the figure: 1 - etched substrate wafer, 2 - bottom metal coating, 3 - vanadium dioxide coating, 4 - top metal coating, 5 - positive photoresist layer, 6 - through-silicon via hole profile, 7 - through-silicon via, 8 - insulating layer, 9 - barrier layer, 10 - seed layer, 11 - electroplated copper layer, 12 - etching device. Detailed implementation manners

[0033] The present invention will be further explained below with reference to specific embodiments.

[0034] Example 1

[0035] Take a two-inch high-resistance silicon wafer and cut it into an etched substrate wafer 1 of 1 cm × 1 cm with a laser dicing machine. Clean the obtained high-resistance silicon successively with methanol, acetone, and isopropyl alcohol, blow it dry with a nitrogen gun, then remove the oxide layer of the silicon substrate with a hydrofluoric acid solution, and blow it dry with a nitrogen gun.

[0036] Refer to Figure 1 , using the electron beam evaporation process, in the electron beam evaporation equipment, with a vacuum degree of 10 -3 -10 -4Under a high vacuum environment of Pa, on the cleaned etched substrate wafer 1, the bottom metal (titanium) coating 2, the vanadium dioxide coating 3 by magnetron sputtering, and the top metal (gold) coating 4 by evaporation sputtering are successively evaporated and sputtered. By heating and evaporating the metal titanium (Ti) with an electron beam and setting the metal sputtering rate to 0.2 nm / min, a 5-nm bottom metal (titanium) coating 2 is sputtered on the silicon substrate. Then, in a high-energy pulsed target magnetron sputtering device, using vanadium as the target, setting the sputtering time to 50 - 200 min and the pulse frequency to 20 - 800 Hz, a 20-nm vanadium dioxide coating 3 is sputtered on the sputtered titanium layer. Then, by heating and evaporating the metal gold (Au) with an electron beam and setting the metal sputtering rate to 0.2 nm / min, a 10-nm top metal (gold) coating 4 is sputtered on the vanadium dioxide coating.

[0037] A positive photoresist layer 5 is coated on the obtained etched substrate wafer. Then, it is baked at a constant temperature of 100 °C for 60 s to remove the moisture in the adhesion layer, so as to improve the adhesion between the positive photoresist and the wafer. Using an i-line contact aligner, aligning with the crosshair alignment mark, the required silicon via hole pattern on the mask is transferred to the positive photoresist layer 5, and the exposure time is 5.5 s. It should be noted that the exposure time varies according to factors such as the thickness of the photoresist layer. Subsequently, it is baked at a constant temperature of 100 °C for 60 s to cure the photosensitive material, and the exposed silicon substrate after heating is developed in a positive-negative photoresist developer for 30 s to remove the excess positive photoresist part, and a silicon via hole hole profile 6 is formed on the positive photoresist layer 5. It should be noted that the development time is related to the thickness of the positive photoresist layer and the concentration of the effective active substance in the developer.

[0038] See Figure 2 , using a dry etching process to remove the bottom metal coating 2, the vanadium dioxide coating 3, and the top metal coating 4 located outside the silicon via hole hole profile 6 and stripping the positive photoresist to obtain a three-layer catalytic body structure cluster containing vanadium dioxide that realizes the silicon via hole.

[0039] Refer to Figure 3 and Figure 6, the obtained three-layer catalytic body structure cluster containing a vanadium dioxide coating 3 for realizing through-silicon vias is placed with the cluster facing upward into a reaction chamber filled with an etching solution. The etching solution is prepared by uniformly mixing hydrogen peroxide with a concentration of 30%, hydrofluoric acid (HF) with a concentration of 49%, and deionized water, and the ratio of the three is 1:3 - 6:2 - 7. The etching solution is heated to 85°C, and then a pair of two-way Helmholtz coils of the etching device is energized with a current of 9 A, resulting in a uniform electric field strength of 200 mT. The high-intensity magnetic field generated will generate a downward magnetic force, generating a downward induced force on the titanium layer on the silicon wafer substrate inside the reaction chamber, realizing vertical etching of the through-silicon vias. Under the catalytic action of the three-layer catalytic body containing vanadium dioxide, the etching solution can rapidly etch the substrate, removing the three-layer catalytic body structure cluster containing vanadium dioxide to obtain through-silicon vias 7. It should be noted that different ratios of the etching solution, different magnitudes of the etching current, the affected magnetic field gradient, and the inconsistent performance of vanadium dioxide prepared in different laboratories resulting in different etching problems will affect the etching rate and etching appearance.

[0040] Refer to Figure 4 , the silicon nitride insulating layer 8 is prepared by plasma-enhanced chemical vapor deposition (PECVD). The reaction gases are high-purity ammonia gas (99.9999%) and silane with a concentration of 5% (the diluent gas is nitrogen), and the carrier gas is nitrogen. The pressure in the reaction chamber is controlled at 130 Pa. A silicon wafer with a size of 1 cm × 1 cm and having deep-aspect-ratio vias after vanadium dioxide-assisted chemical etching is used as the substrate, and the substrate is heated to a temperature of 300°C. The flow rates of the reaction gases are controlled, and the reaction gases are guided into the through-silicon vias. Among them, the flow rate of silane is 280 mL / min, and the flow rate of ammonia gas is 10 mL / min. After the reaction gases are introduced into the chamber, a radio frequency power supply with a power of 100 W is used to ionize the gases to generate plasma, which reacts with the substrate to form silicon nitride. After deposition for 25 min, a silicon nitride insulating layer 8 film with good uniformity and a dense structure is formed.

[0041] The titanium nitride barrier layer 9 is prepared by atomic layer deposition (ALD). After the substrate is placed in the chamber, the chamber is evacuated, and the chamber is heated in an environment where nitrogen is continuously introduced. The pressure in the chamber is always maintained at 100 Pa. Wait for the chamber temperature to rise to 380°C, and set the experimental reaction procedure to conduct the experiment. First, a 0.2 s pulse of the precursor titanium tetrachloride enters the reaction chamber and undergoes a chemical adsorption reaction on the exposed surface of the silicon nitride film. High-purity nitrogen is introduced for purging for 2 s to carry out the reaction by-products out of the chamber. Then, a 0.2 s pulse of ammonia gas enters the reaction chamber and reacts chemically with the surface adsorbed with the titanium tetrachloride precursor to form titanium nitride. Then, nitrogen is introduced for purging for 3 s to remove the excess precursor and reaction by-products. A titanium nitride barrier layer 9 with good chemical stability, high mechanical strength, and low resistivity is formed.

[0042] The copper seed layer 10 is prepared by physical vapor deposition (PVD). The copper target is placed in the crucible inside the electron beam evaporation chamber, and then the chamber is evacuated so that the air pressure drops to 5×10 -6 Pa. Turn on the main power switch of the electron gun, adjust the tungsten filament current and set the coating thickness. Adjust the voltage regulator to accelerate the electron beam and bombard the target to evaporate it. When the required coating thickness is reached, turn off the switches one by one according to the above steps to complete the deposition of the seed layer 10.

[0043] Refer to Figure 5 and conduct a vacuum pre-wetting treatment experiment on the substrate after the above operations. Place the substrate face up in the pre-wetting chamber. Evacuate the pre-wetting chamber and inject deionized water. When the vacuum degree is 10 kPa, it is observed that no bubbles are generated on the surface of the wafer, and complete infiltration inside the through-silicon vias of the wafer is achieved. Place the vacuum pre-wetted substrate in the electroplating solution tank inside the copper plating deposition chamber. The deposition chamber is equipped with a plating solution rapid stirring system to ensure sufficient copper ion supply on the pore walls of the through-holes. After electroplating and exchanging for 5 - 10 minutes, turn on the power supply for electroplating to achieve the backfilling of the electroplated copper layer 11, and adjust the current density and time according to the aspect ratio of the through-silicon vias.

[0044] The first and second substrate wafers are prepared by the above method. Then, use the electron beam evaporation process to sputter a metal seed layer on the upper surface of the first substrate wafer and the lower surface of the second substrate wafer after metal backfilling. After photolithography, grow microbumps and sealing rings using the electroplating process. Then, photolithograph and etch the pads, and then perform wafer-level encapsulation, and use the pattern electroplating method to fabricate the redistribution layer of the through-silicon via substrate wafer. Flip the first and second substrate wafers and use the copper-copper direct bonding technology to achieve the hermetic bonding of the second substrate wafer and the first substrate wafer. The present invention can hermetically bond multiple substrate wafers through this method.

[0045] Example 2

[0046] Refer to Figure 7 and Figure 8 , use a two-inch SiC wafer as the substrate material. The etching device uses three pairs of six-directional Helmholtz coils. By controlling the magnitude of the current passed through the six-directional Helmholtz coils, a magnetic field gradient with a certain inclination angle inside the etching chamber is obtained, thereby controlling the direction of magnetron-assisted chemical etching of vanadium dioxide. Other process conditions and operation steps are the same as the repeated experimental steps in Example 1.

[0047] Table 1 Comparison of aspect ratios of different metal-assisted chemical etching

[0048]

[0049] As can be seen from the test results in Table 1, the present invention uses the vanadium dioxide-assisted chemical etching technology, which can significantly improve the aspect ratio of etching, reaching more than 90:1. Especially in the deep silicon etching scenario and the vertical etching and certain inclination angle scenarios, it can greatly maintain the etching shape, and the aspect ratio is significantly superior to the existing metal-assisted chemical etching methods.

[0050] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the appended claims and their equivalents, and all should be included within the protection scope of the present application.

Claims

1. A heterogeneous integration preparation method for silicon through vias based on vanadium dioxide, characterized in that The method steps are as follows: S1: Evaporate and sputter a bottom metal coating (2), a vanadium dioxide coating (3) by magnetron sputtering, and a top metal coating (4) on the etched substrate wafer (1) in sequence; S2: Coat a positive photoresist (5) on the side of the top metal coating (4) away from the vanadium dioxide coating (3), and open a via hole profile (6) in the positive photoresist layer (5). Dry-etch to remove the bottom metal coating (2), the vanadium dioxide coating (3), and the top metal coating (4) located outside the via hole profile (6), and strip the positive photoresist layer (5); S3: Place the etched substrate wafer (1) processed in S2 into a reaction chamber containing an etching solution, and induce a three-layer catalytic body of bottom metal coating - vanadium dioxide coating - top metal coating containing vanadium dioxide through a magnetic field to achieve directional etching of the etched substrate wafer (1) to form a via hole (7); S4: Remove the bottom metal coating (2), the vanadium dioxide coating (3), and the top metal coating (4) in the via hole (7), and deposit an insulating layer (8), a barrier layer (9), a seed layer (10), and backfill with an electroplated copper layer (11) in the via hole (7) in sequence; S5: Stack multiple etched substrate wafers (1) to achieve heterogeneous integration.

2. The heterogeneous integration preparation method for realizing through-silicon vias based on vanadium dioxide according to claim 1, wherein, The etched substrate wafer (1) is one of silicon, germanium, silicon carbide, gallium arsenide, and gallium nitride.

3. The heterogeneous integration preparation method for realizing through-silicon vias based on vanadium dioxide according to claim 1, characterized in that, The bottom metal coating (2) is titanium with a thickness of 3 - 15 nm.

4. The heterogeneous integration preparation method for realizing through-silicon vias based on vanadium dioxide according to claim 1, wherein The thickness of the vanadium dioxide coating (3) is 10 - 50 nm.

5. The heterogeneous integration preparation method for realizing through-silicon vias based on vanadium dioxide according to claim 1, wherein, The thickness of the top metal coating (4) is 3 - 10 nm.

6. The heterogeneous integration preparation method for realizing through-silicon vias based on vanadium dioxide according to claim 1, wherein, The etching temperature is 70 - 100 °C.

7. The heterogeneous integration preparation method for realizing through-silicon vias based on vanadium dioxide according to claim 1, wherein, The insulating layer (8) is silicon nitride with a thickness of 10 - 30 nm.

8. The method for heterogeneous integration preparation of silicon through vias based on vanadium dioxide according to claim 1, wherein, The barrier layer (9) is titanium nitride with a thickness of 10 - 30 nm.

9. The heterogeneous integration preparation method for realizing through-silicon vias based on vanadium dioxide according to claim 1, characterized in that, The seed layer (10) is copper with a thickness of 1 - 100 nm.

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