Semiconductor chip packaging machine and packaging method thereof

Abstract

According to the semiconductor chip packaging machine and the packaging method thereof, the plastic deformation characteristic of the middle layer is utilized, micro gaps between the micro columns and the bottom of the chip layer are actively filled in the pressing process, the temporary heat conduction bridge is formed, efficient heat conduction is achieved at the initial stage of packaging through the temporary heat conduction bridge structure, local hot spots are avoided, and the packaging efficiency is improved. And meanwhile, accurate structure support is provided for subsequent three-dimensional grid channel forming. The formed three-dimensional grid channels are combined with filling and curing of the high-heat-conduction medium, a three-dimensional penetrating heat conduction path is constructed, and the heat stability is remarkably improved. Through multi-stage temperature control, polymer decomposition and middle layer stripping processes are synchronously matched with material thermal expansion coefficient differences, and chip cracking and interface layering defects are effectively prevented. And the three-dimensional heat dissipation network and the heat dissipation cover with the laser welding top form a vertical-horizontal composite heat dissipation system, so that the heat dissipation capability of the packaging structure is enhanced. Therefore, the technical problem of poor heat dissipation performance of the semiconductor chip packaging structure in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and particularly to a semiconductor chip packaging machine and a packaging method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, chip packaging technology plays a crucial role in the manufacturing process of electronic products. Semiconductor chip packaging can not only protect the chip from the influence of the external environment, but also improve the working stability and performance of the chip. With the increase of chip power density, the chip heat dissipation problem has gradually become one of the bottlenecks restricting its performance and service life.

[0003] In the prior art, traditional chip packaging technologies mainly include plastic packaging, ceramic packaging, and metal packaging, etc. However, these packaging methods face certain limitations under the heat dissipation requirements of high-power density chips. First, the thermal conductivity of traditional packaging materials is relatively low, making it difficult to effectively conduct the heat generated by the chip in a timely manner. Second, the traditional packaging structure cannot provide sufficient thermal management capabilities, resulting in too high a temperature inside the packaging structure, affecting the stability and long-term service life of semiconductor chips. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor chip packaging machine and a packaging method thereof, which solve the technical problem of poor heat dissipation performance of the semiconductor chip packaging structure in the prior art.

[0005] To achieve this purpose, the present invention adopts the following technical solutions: According to the first aspect, the present invention discloses a packaging method for a semiconductor chip, including: Step S1, preparing a composite substrate with an intermediate layer; the composite substrate includes a first substrate and an intermediate layer, micro-columns are formed on the surface of the first substrate in a matrix distribution, a thermal decomposition polymer is filled in the gaps between the micro-columns, and the intermediate layer covers the surface of the micro-columns; Step S2, laminating the chip layer on the surface of the composite substrate to form a preliminary packaging structure; wherein, the intermediate layer undergoes plastic deformation under pressure and fills the microscopic voids between the bottom of the chip layer and the micro-columns, and forms a temporary heat conduction bridge; Step S3, performing gradient heating bonding on the preliminary packaging structure, sequentially removing the thermal decomposition polymer and the intermediate layer, and forming a three-dimensional grid channel between the chip layer and the composite substrate; Step S4, filling a high thermal conductivity medium into the three-dimensional grid channel and curing it to form a three-dimensional heat dissipation network; Step S5: Stack a heat dissipation cover on top of the chip layer and bond the heat dissipation cover to the edge of the composite substrate by laser welding to form a semiconductor chip packaging structure with high heat dissipation performance.

[0006] Optionally, step S1 includes: Step S11: Form copper micro-columns distributed in a matrix on the surface of the first substrate; the height of the micro-columns is 20 - 50 μm, the diameter is 10 - 30 μm, and the pitch is 5 - 15 μm. Step S12: Spin-coat a polycarbonate propylene solution in the gaps between the micro-columns, with the filling thickness covering 80 - 90% of the height of the micro-columns, and form a dense filling layer through thermal curing. Step S13: Deposit an aluminum-titanium alloy on the surfaces of the micro-columns and the filling layer in sequence to form an intermediate layer with a thickness of 1 - 3 μm.

[0007] Optionally, after step S13, step S1 further includes: Step S14: Remove the intermediate layer on the surface of the filling layer so that the intermediate layer only covers the surface of the micro-columns and form a continuously covered metallized interface. Step S15: Laser-etch pits with a diameter of 1 - 3 μm on the surface of the intermediate layer. Step S16: Inject boron nitride nanosheets into the pits.

[0008] Optionally, step S2 includes: Step S21: Perform plasma activation treatment on the bonding surface of the chip layer, with the volume ratio of argon / oxygen mixed gas being 4:1, the radio frequency power being 300 W, and the treatment time being 120 s. Step S22: After positioning the chip layer and the composite substrate, apply a gradient pressure for lamination; among them, the vertical pressure in the first stage is 10 - 15 MPa, the temperature is 80 - 100 °C, and it is maintained for 30 s to cause plastic deformation of the intermediate layer; in the second stage, the pressure is increased to 20 - 25 MPa, the temperature is raised to 150 - 180 °C, and it is maintained for 60 s to make the intermediate layer fill the microscopic voids between the bottom of the chip layer and the micro-columns. Step S23: After the plastic deformation of the intermediate layer, the thickness of the intermediate layer is 0.2 - 0.5 μm, covering more than 98% of the bottom surface of the chip.

[0009] Optionally, after step S23, step S2 further includes: Step S24: Cool down to below 50 °C at a rate of 2 °C / s in a nitrogen atmosphere and relieve the pressure synchronously.

[0010] Optionally, step S3 includes: Step S31: Gradually heat the preliminary encapsulation structure. Under a nitrogen protection atmosphere, raise the temperature to 280 - 300 °C at a rate of 5 °C / min and keep it at a constant temperature for 30 - 45 min to remove the thermally decomposed polymer. Step S32: Introduce an oxygen / argon mixed gas with a volume ratio of 1:5. Raise the temperature to 450 - 480 °C at a rate of 3 - 5 °C / min and maintain it for 20 min to oxidize the intermediate layer of the aluminum-titanium alloy to form a composite oxide of alumina-titania. Step S33: Selectively etch the composite oxide with a phosphoric acid / acetic acid mixed solution with a volume ratio of 3:1 at an etching rate of 8 - 10 μm / h to obtain a formed three-dimensional grid channel.

[0011] Optionally, after the step S33, step S3 further includes: Step S34: Perform ultrasonic micro-etching on the formed three-dimensional grid channel. Apply ultrasonic waves at 40 kHz in 0.1 mol / L dilute sulfuric acid to remove the nano-scale oxidation debris in the three-dimensional grid channel.

[0012] Optionally, the step S4 includes: Step S41: Perform plasma activation pretreatment on the inner wall of the three-dimensional grid channel. In an argon / hydrogen mixed atmosphere with a volume ratio of 9:1, apply a radio frequency power of 500 W and a treatment time of 180 seconds. Step S42: Inject the preheated liquid metal into the three-dimensional grid channel through vacuum negative pressure at an injection rate of 0.51 mL / min. Among them, the preheating temperature is 80 - 100 °C, the liquid metal is a gallium-indium-tin alloy, the mass fraction of gallium is 60% - 65%, the mass fraction of indium is 20% - 25%, the mass fraction of tin is 15% - 20%, and 1 - 3% by volume of aluminum nitride nanowires are incorporated. Step S43: Perform solidification treatment on the liquid metal in the three-dimensional grid channel. Among them, in the first stage of solidification, cool down to 25 °C at a rate of 2 °C / min to preliminarily solidify the liquid metal; in the second stage of solidification, heat up to 180 - 200 °C under nitrogen protection and keep it warm for 30 minutes to generate a titanium tri-aluminum-aluminum nitride (Ti3Al-AlN) interfacial transition layer.

[0013] Optionally, in the step S5, the heat dissipation cover is made of porous silicon carbide material with a pore diameter of 5 - 20 μm; micro-channels for lateral heat dissipation are etched on the surface of the heat dissipation cover.

[0014] According to the second aspect, the present invention discloses a semiconductor chip encapsulation machine for implementing the encapsulation method of a semiconductor chip as described in the first aspect, including: A preparation module for preparing a composite substrate with an intermediate layer; wherein, the preparation module includes a forming unit, a filling unit and a covering unit, the forming unit is used to form micro-columns distributed in a matrix on the surface of the first substrate, the filling unit is used to fill the gaps between the micro-columns with a thermally decomposable polymer, and the covering unit is used to cover the intermediate layer on the surface of the micro-columns; A lamination module for laminating a chip layer on the surface of the composite substrate to form a preliminary packaging structure; A heating and bonding module for performing gradient heating and bonding on the preliminary packaging structure, sequentially removing the thermally decomposable polymer and the intermediate layer, and forming a three-dimensional grid channel between the chip layer and the composite substrate; A three-dimensional heat dissipation network forming module for filling a high thermal conductivity medium into the three-dimensional grid channel and curing to form a three-dimensional heat dissipation network; An assembly module for laminating a heat dissipation cover on the top of the chip layer and joining the heat dissipation cover to the edge of the composite substrate by laser welding to form a semiconductor chip packaging structure with high heat dissipation performance.

[0015] Compared with the prior art, the present invention has the following beneficial effects: A semiconductor chip packaging machine and its packaging method provided by the present invention utilize the plastic deformation characteristics of the intermediate layer to actively fill the microscopic voids between the micro-columns and the bottom of the chip layer during the lamination process and form a temporary heat conduction bridge. The temporary heat conduction bridge structure realizes efficient heat conduction at the initial stage of packaging, avoids the generation of local hot spots, and at the same time provides precise structural support for the subsequent formation of the three-dimensional grid channel. The three-dimensional grid channel formed by removing the thermally decomposable polymer and the intermediate layer through gradient heating and bonding, combined with the high thermal conductivity medium filling and curing technology, constructs a three-dimensional through-conduction heat conduction path between the chip layer and the substrate, significantly improving the thermal stability. Through multi-stage temperature control, the polymer decomposition and the intermediate layer peeling process are synchronized to match the difference in the thermal expansion coefficients of the materials, effectively preventing chip cracking and interface delamination defects. The three-dimensional heat dissipation network and the heat dissipation cover welded by laser on the top form a vertical-horizontal composite heat dissipation system, enhancing the heat dissipation ability of the packaging structure, and at the same time improving the overall sealing performance and anti-mechanical stress of the packaging structure, meeting the increasingly strict requirements of high-performance chips for packaging technology. Therefore, the present invention solves the technical problem of poor heat dissipation performance of semiconductor chip packaging structures in the prior art. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] The structures, proportions, sizes, etc. depicted in the accompanying drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they do not have substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention.

[0018] Figure 1 It is a schematic flow chart of a packaging method for a semiconductor chip disclosed in Embodiment 1 of the present invention. Specific embodiments

[0019] In order to make the invention objectives, features, and advantages of the present invention more obvious and understandable, the following will combine the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0020] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be intermediate components present at the same time.

[0021] The following will further illustrate the technical solutions of the present invention in conjunction with the accompanying drawings and through specific embodiments.

[0022] Embodiment 1: The embodiment of the present invention provides a packaging method for a semiconductor chip, as Figure 1 shown, including: Step S1, preparing a composite substrate with an intermediate layer; the composite substrate includes a first substrate and an intermediate layer. Micro-columns are formed on the surface of the first substrate in a matrix distribution, and the gaps between the micro-columns are filled with a thermally decomposable polymer. The intermediate layer covers the surface of the micro-columns; in this embodiment, polypropylene carbonate (PPC) is used as the thermally decomposable polymer, and its thermal decomposition temperature range is 200 - 300 °C; Step S2: Laminate the chip on the surface of the composite substrate to form a preliminary packaging structure. Among them, the intermediate layer undergoes plastic deformation under pressure, fills the microscopic voids between the bottom of the chip layer and the micro-pillars, and forms a temporary heat conduction bridge. Step S3: Perform gradient heating bonding on the preliminary packaging structure, sequentially remove the thermally decomposable polymer and the intermediate layer, and form a three-dimensional grid channel between the chip layer and the composite substrate. The inner wall of the three-dimensional grid channel is composed of the surface of the first substrate, the side walls of the micro-pillars, and the bottom surface of the chip layer. Step S4: Fill the three-dimensional grid channel with a high thermal conductivity medium and cure it to form a three-dimensional heat dissipation network. In this embodiment, the high thermal conductivity medium uses a gallium-indium-tin alloy. Step S5: Stack a heat dissipation cover on the top of the chip layer and join the heat dissipation cover to the edge of the composite substrate by laser welding to form a semiconductor chip packaging structure with high heat dissipation performance.

[0023] It should be noted that for a semiconductor chip packaging machine and its packaging method provided by the present invention, by utilizing the plastic deformation characteristics of the intermediate layer, the microscopic voids between the micro-pillars and the bottom of the chip layer are actively filled during the lamination process. The temporary heat conduction bridge structure realizes efficient heat conduction at the initial stage of packaging, avoids the generation of local hot spots, and at the same time provides precise structural support for the subsequent formation of the three-dimensional grid channel. The three-dimensional grid channel formed by removing the thermally decomposable polymer and the intermediate layer through gradient heating bonding, combined with the high thermal conductivity medium filling and curing technology, constructs a three-dimensional through-going heat conduction path between the chip layer and the substrate, significantly improving the thermal stability. Through multi-stage temperature control, the polymer decomposition and the intermediate layer peeling process are synchronized to match the difference in the thermal expansion coefficients of the materials, effectively preventing chip cracking and interface delamination defects. The three-dimensional heat dissipation network and the heat dissipation cover laser-welded on the top form a vertical-horizontal composite heat dissipation system, enhancing the heat dissipation ability of the packaging structure, and at the same time improving the overall sealing performance and anti-mechanical stress of the packaging structure, meeting the increasingly strict requirements of high-performance chips for packaging technology. Therefore, the present invention solves the technical problem of poor heat dissipation performance in the existing semiconductor chip packaging structure.

[0024] In this embodiment, Step S1 includes: Step S11: Form copper micro-pillars distributed in a matrix on the surface of the first substrate. The height of the micro-pillars is 20 - 50 μm, the diameter is 10 - 30 μm, and the pitch is 5 - 15 μm. Specifically, copper micro-columns are fabricated on the surface of the first substrate (such as a ceramic substrate or a silicon substrate) using a lithography- electroplating process. A titanium / copper seed layer (with a thickness of 100 - 200 nm) is formed on the substrate surface through a sputtering process. A photoresist (SU-8 3050) is spin-coated, and matrix patterning (with a pore diameter of 10 - 30 μm and a pitch of 5 - 15 μm) is performed using a commonly used step-and-repeat exposure machine in the art. Then, copper micro-columns are electroplated in a copper sulfate electrolyte, controlling the current density at 3 - 5 ASD and the time at 10 - 30 minutes to obtain vertical micro-columns with a height of 20 - 50 μm and a diameter tolerance of ±1 μm. After stripping the photoresist, the residual seed layer is removed by plasma etching.

[0025] Step S12: Spin-coat a polycarbonate propylene solution within the micro-column gaps, with the filling thickness covering 80 - 90% of the micro-column height, and form a dense filling layer through thermal curing. Specifically, a polycarbonate propylene (PPC) solution (with a solid content of 35%) is injected into the micro-column gaps using a spin-coating process. A two-stage program is set for the spin coater: the spin rate in the first stage is 500 rpm, and the spin time is 10 s to achieve solution spreading. The spin rate in the second stage is 3000 rpm, and the spin time is 30 s to control the film thickness. Stepwise curing is carried out under nitrogen protection, with a pre-curing temperature of 80 °C and a pre-curing time of 20 min to remove the solvent. Then, the temperature is raised to 180 °C at a rate of 5 °C / min and cured for 1 h to complete crosslinking, forming a dense filling layer (covering 85 ± 5% of the micro-column height). Subsequently, the filling uniformity is detected by a laser confocal microscope to ensure that the porosity is less than 0.5%.

[0026] Step S13: Deposit an aluminum-titanium alloy successively on the surfaces of the micro-columns and the filling layer to form an intermediate layer with a thickness of 1 - 3 μm. In this embodiment, the intermediate layer is deposited successively using a magnetron sputtering process, introducing argon (with a purity of 99.999%) as the working gas, and maintaining the vacuum degree at 5×10 -3 Pa. First, deposit a pure titanium layer (with a thickness of 0.2 μm) as an adhesion layer to improve the interfacial bonding strength. Then, use an AlTi alloy target (with an Al:Ti atomic ratio of 7:3), a power of 300 W, a bias voltage of -50 V, and a deposition rate of 0.5 μm / h to form a continuous and dense intermediate layer with a thickness of 1 - 3 μm.

[0027] It should be noted that the electroplating process combined with photolithographic patterning realizes a 5-μm pitch control (error < ±0.8 μm). The aspect ratio of the micro-columns reaches 5:1 (50 μm in height / 10 μm in diameter), which improves the structural density compared with the traditional etching process, increases the heat dissipation contact points per unit area, and significantly expands the heat conduction interface. Poly(propylene carbonate) (PPC) undergoes chain segment depolymerization at 200-300 °C, and its thermal decomposition temperature is precisely matched with the gradient heating process in the subsequent step S3. The decomposition products are CO2 and H2O gases (without residual carbon slag), ensuring the cleanliness of the three-dimensional grid channels.

[0028] After step S13, step S1 further includes: Step S14, removing the intermediate layer on the surface of the filling layer so that the intermediate layer only covers the surface of the micro-columns and forms a continuously covered metallization interface; in this embodiment, an ion beam etching process is used to remove the intermediate layer on the surface of the filling layer, with Ar⁺ ion beam and an energy of 200-500 eV; the etching area is defined by a mask, and the selection ratio (intermediate layer: filling layer) needs to be greater than 10:1; Step S15, laser etching pits with a diameter of 1-3 μm on the surface of the intermediate layer; in this embodiment, an ultraviolet laser with a wavelength of 355 nm is used, the pulse width is 10 ps, and the energy density is 3-5 J / cm 2 。

[0029] Step S16, injecting boron nitride nanosheets (BNNS) into the pits. In this embodiment, an ethanol suspension of boron nitride nanosheets (with a thickness of 2-5 nm and a lateral size of 500 nm-1 μm) (concentration 1 wt%) is prepared, and 0.1 wt% of a silane coupling agent is added to improve the wettability; the sample is tilted at 15° and placed in a vacuum chamber, and the suspension is dripped at a rate of 50 μL / min, and the BNNS is directionally embedded in the pits by capillary force. Then, stepwise curing is carried out: the first curing temperature is 80 °C and the time is 1 h to volatilize the solvent; the second curing temperature is 250 °C and the time is 2 h to activate the coupling agent and form a covalently bonded BNNS enhanced structure.

[0030] It should be noted that selectively retaining the intermediate layer on the surface of the micro-columns increases the contact area of the metallization interface to 92-95% of the surface area of the micro-columns, while reducing the non-functional metal residue (weight reduction of 40%), and further reducing the interfacial thermal resistance; the laser-etched pits (step S15) and BNNS filling (step S16) form a hierarchical heat conduction structure: the pit array makes the local heat flux density distribution more uniform, avoids heat concentration at the top of the micro-columns, and constructs a radial-axial cooperative three-dimensional heat conduction network; through the covalent bonding of BNNS and the intermediate layer, the interfacial bonding strength is improved. The insulating property of BNNS effectively suppresses the leakage current between the micro-columns and reduces the dielectric loss of the packaging structure In an alternative embodiment, step S2 includes: Step S21: Perform plasma activation treatment on the bonding surface of the chip layer. The volume ratio of the argon / oxygen mixed gas is 4:1, the radio frequency power is 300 W, and the treatment time is 120 s. Step S22: After positioning the chip layer and the composite substrate, apply a gradient pressure for lamination. Among them, the vertical pressure in the first stage is 10 - 15 MPa, the temperature is 80 - 100 °C, and it is maintained for 30 s to cause plastic deformation of the intermediate layer; in the second stage, the pressure is increased to 20 - 25 MPa, the temperature is raised to 150 - 180 °C, and it is maintained for 60 s to fill the microscopic voids between the bottom of the chip layer and the micro pillars with the intermediate layer. Step S23: After the plastic deformation of the intermediate layer, the thickness of the intermediate layer is 0.2 - 0.5 μm, covering more than 98% of the bottom surface of the chip.

[0031] It should be noted that the argon - oxygen plasma activation in step S21 forms a nanoscale rough structure (0.8 - 1.2 nm) and highly reactive functional groups on the chip surface, and the surface oxygen element content is increased to 25 at% after activation; the pits and BNNS formed in step S1 provide stress buffer points for the gradient pressure loading in step S22, making the pressure distribution more uniform.

[0032] In an optional embodiment, after step S23, step S2 further includes: Step S24: Cool down to below 50 °C at a rate of 2 °C / s in a nitrogen atmosphere and relieve the pressure synchronously.

[0033] It should be noted that step S24 reduces the residual stress between the chip layer and the composite substrate, and the nitrogen cooling process in step S24 is compatible with the gradient heating bonding in step S3, avoiding the generation of aluminum nitride (AlN) insulating layer at the interface.

[0034] In an optional embodiment, step S3 includes: Step S31: Perform gradient heating on the preliminary packaging structure. Under the protection of nitrogen atmosphere, heat it up to 280 - 300 °C at a rate of 5 °C / min and keep it at a constant temperature for 30 - 45 min to remove the thermally decomposed polymer; in order to avoid deformation of the micro pillars, the nitrogen flow rate is controlled at 20 - 30 L / min; during the constant temperature stage, intermittent vacuum pumping is used to accelerate the discharge of the decomposed gas and prevent blockage of the micro pillar gaps.

[0035] Step S32: Introduce an oxygen / argon mixed gas with a volume ratio of 1:5, heat it up to 450 - 480°C at a rate of 3 - 5°C / min and hold for 20 min to oxidize the intermediate layer of the aluminum-titanium alloy to form a composite oxide of alumina-titania. In this embodiment, the heating rate is 5°C / min in the temperature range of 300 - 400°C, which can quickly cross the active oxidation temperature range of titanium; the heating rate is 3°C / min in the temperature range of 400 - 480°C, which can finely control the oxidation nucleation and growth of aluminum. The heating rate in Step S32 is strictly controlled at 3 - 5°C / min. By segmented control, the balance between the formation of a highly dense oxide layer and the protection of the integrity of the micro-nano structure is achieved, laying a process foundation for the cleaning of three-dimensional grid channels and the filling of high thermal conductivity media. The thickness of the oxide layer is 2 - 4μm, which is composed of nanocrystalline Al2O3 (grain size 50 - 100nm) and amorphous TiO2; Step S33: Selectively etch the composite oxide with a phosphoric acid / acetic acid mixed solution with a volume ratio of 3:1, and the removal rate is 8 - 10μm / h to obtain the formed three-dimensional grid channels. In this embodiment, phosphoric acid is used to preferentially dissolve Al2O3, and acetic acid is used to complex and dissolve TiO2. The micro-columns and the first substrate are passivated in an acidic environment (corrosion rate ≤ 0.01μm / h), realizing selective removal.

[0036] It should be noted that gradient heating and coordinated control of oxidation-etching ensure the consistency of channel dimensions; selective etching results in a low loss rate of copper micro-columns, ensuring the mechanical strength of the three-dimensional grid channels; the thermal decomposition polymer is completely vaporized (residual carbon ≤ 50ppm), avoiding thermal conductivity degradation caused by carbon deposition; by adjusting the oxidation temperature and etching time, the channel density and aspect ratio can be customized. The phosphoric acid / acetic acid mixed solution is recovered by distillation (recovery rate ≥ 85%), reducing hazardous waste emissions.

[0037] In an alternative embodiment, after Step S33, Step S3 further includes: Step S34: Perform ultrasonic micro-etching on the formed three-dimensional grid channels, apply ultrasonic waves of 40 kHz in 0.1 mol / L dilute sulfuric acid to remove nano-scale oxidation debris in the three-dimensional grid channels. In this embodiment, a 40 kHz piezoelectric ceramic ultrasonic generator (power density 0.5 - 1.0 W / cm 2 ) is used, equipped with an acid-resistant reaction tank made of polytetrafluoroethylene (PTFE); the etching solution is prepared as a 0.1 mol / L dilute sulfuric acid solution (pH ≈ 1.0), and the temperature is controlled at 25 ± 2°C to avoid high temperature accelerating the corrosion of micro-columns. Immerse the formed three-dimensional grid channels in the etching solution, perform ultrasonic treatment for 10 - 15 min, and simultaneously introduce nitrogen bubbling (flow rate 5 L / min) to enhance the detachment of debris.

[0038] It should be noted that 40 kHz ultrasonic waves generate micron-sized bubbles (with a diameter of 5 - 50 μm) in the liquid. When the bubbles burst, shock waves are released (pressure peak ≥ 100 MPa), stripping the oxidized debris (Al2O3 / TiO2 nanoparticles with a particle size of 50 - 200 nm) attached to the inner wall of the channel. After the three-dimensional grid channel is ultrasonically micro-etched, the inner wall roughness is optimized, which can reduce the interfacial phonon scattering during the filling of liquid metal in the subsequent step S42 and enhance the heat dissipation network performance.

[0039] In an alternative embodiment, step S4 includes: Step S41, performing plasma activation pretreatment on the inner wall of the three-dimensional grid channel; in an argon / hydrogen mixed atmosphere with a volume ratio of 9:1, the applied radio frequency power is 500 W, and the treatment time is 180 seconds; in this embodiment, a radio frequency plasma reaction chamber (frequency 13.56 MHz) is used to activate the inner wall of the three-dimensional grid channel, removing the inner wall oxide layer and forming nano-scale grooves, increasing the specific surface area; the ultrasonic micro-etching in step S34 lays the foundation for the surface cleanliness of the activation treatment in step S41.

[0040] Step S42, injecting preheated liquid metal into the three-dimensional grid channel through vacuum negative pressure, with an injection rate of 0.51 mL / min; wherein, the preheating temperature is 80 - 100 °C, the liquid metal is a gallium-indium-tin alloy, the mass fraction of gallium is 60% - 65%, the mass fraction of indium is 20% - 25%, the mass fraction of tin is 15% - 20%, and 1 - 3% by volume of aluminum nitride nanowires are incorporated; Step S43, performing solidification treatment on the liquid metal in the three-dimensional grid channel; wherein, in the first stage of solidification, the temperature is decreased to 25 °C at a rate of 2 °C / min to preliminarily solidify the liquid metal; in the second stage of solidification, it is heated to 180 - 200 °C under nitrogen protection and held for 30 minutes to generate a titanium tri-aluminum-aluminum nitride (Ti3Al - AlN) interfacial transition layer.

[0041] It should be noted that the aluminum nitride nanowires are arranged axially along the channel. Compared with pure liquid metal, it improves the axial thermal conductivity. Through vacuum injection combined with the axial alignment of nanowires, it ensures the continuous distribution of the medium in the complex grid channel, breaking through the pore residue limitation of traditional capillary filling. The gradient solidification temperature (25 °C → 200 °C) in step S43 has no conflict with the intermediate layer oxidation temperature (450 - 480 °C) in step S32, avoiding the superposition of thermal history effects. The fluidity of the liquid metal adapts to the dendritic channel morphology, and the aluminum nitride nanowires enhance the axial heat conduction, forming a multi-scale heat conduction network with the boron nitride nanosheets in step S16.

[0042] In an alternative embodiment, in step S5, the heat dissipation cover is made of porous silicon carbide material with a pore diameter of 5 - 20 μm; the surface of the heat dissipation cover is etched with microchannels for lateral heat dissipation.

[0043] Specifically, the gel casting method is adopted: using silicon carbide powder (particle size 0.5 - 1.0 μm) as the matrix, adding a pore-forming agent (polymethyl methacrylate microspheres, particle size 5 - 20 μm), and forming a porous structure with an open porosity of 60% - 70% after vacuum sintering at 1600 °C; by adjusting the pore-forming agent content (10% - 30 vol%) and the sintering temperature gradient (±10 °C / min), a gradient distribution of pore diameters of 5 - 20 μm is achieved. The microchannels of the heat dissipation cover are etched by femtosecond laser (wavelength 1030 nm, pulse width 300 fs, power 10 W), and serpentine microchannels with a depth of 80 - 120 μm, a width of 50 - 100 μm (spacing 200 - 300 μm) are etched on the surface of the heat dissipation cover, and the roughness Ra ≤ 0.8 μm. The heat dissipation cover is laser welded using a blue semiconductor laser and an annular scanning path with a linear velocity of 5 - 8 mm / s; among them, the laser wavelength is 450 nm, the power is 800 - 1000 W, and the welding depth is 200 - 300 μm; the shielding gas is a helium / hydrogen mixture with a volume ratio of 3:1 and a flow rate of 15 - 20 L / min to inhibit oxidation and reduce the porosity of the weld (≤0.1%).

[0044] It should be noted that the pore structure of the porous silicon carbide (specific surface area > 200 m 2 / g) dissipates heat through natural convection and radiation, enhancing the heat flux density carrying capacity. The microchannels can be connected to an external circulation system, and a coolant (such as deionized water or fluorinated liquid) is introduced. When the flow rate is 1 - 3 mL / min, active heat dissipation of the heat dissipation cover can be achieved.

[0045] Embodiment 2: The embodiment of the present invention provides a semiconductor chip encapsulation machine for implementing the semiconductor chip encapsulation method as in Embodiment 1, including: A preparation module for preparing a composite substrate with an intermediate layer; among them, the preparation module includes a forming unit, a filling unit, and a covering unit. The forming unit is used to form microcolumns distributed in a matrix on the surface of the first substrate, the filling unit is used to fill the gaps between the microcolumns with a thermally decomposable polymer, and the covering unit is used to cover the intermediate layer on the surface of the microcolumns; A pressing module for laminating the chip layer on the surface of the composite substrate to form a preliminary encapsulation structure; A heating and bonding module for gradient heating and bonding of the preliminary encapsulation structure, sequentially removing the thermally decomposable polymer and the intermediate layer, and forming a three-dimensional grid channel between the chip layer and the composite substrate; A three-dimensional heat dissipation network forming module is used to fill a high thermal conductivity medium into a three-dimensional grid channel and cure it to form a three-dimensional heat dissipation network; An assembly module is used to stack a heat dissipation cover on the top of the chip layer and join the heat dissipation cover to the edge of the composite substrate by laser welding to form a semiconductor chip packaging structure with high heat dissipation performance.

[0046] It should be noted that by introducing a three-dimensional grid channel and filling a high thermal conductivity medium in the packaging structure, the heat dissipation performance of the chip can be effectively improved, the working temperature can be reduced, thereby extending the service life and stability of the semiconductor chip. By using the methods of pressing and heating bonding, the tight bonding between the chip and the substrate can be ensured, reducing voids or interface defects, making the packaging structure more reliable and adaptable to more extreme working environments. Through the coordinated use of the intermediate layer and the three-dimensional grid channel, more flexibility is provided for semiconductor chip packaging, and targeted design and optimization can be carried out according to the heat dissipation requirements and packaging requirements of different chips. The integration of each module area of this packaging machine can achieve automated operation, reduce manual intervention, improve packaging efficiency, and reduce production costs. By using thermally decomposable polymers, the waste of materials can be effectively reduced during the packaging process, improving the resource utilization efficiency, which meets the requirements of sustainable development. Through the application of multi-layer structures and high thermal conductivity materials, the packaging structure can be more stable under conditions such as mechanical stress and temperature changes, and has stronger compressive and heat-resistant capabilities.

[0047] In summary, through its unique structure and process, the semiconductor chip packaging machine of the present invention can not only improve the heat dissipation ability of the semiconductor chip, but also help to improve the performance and reliability of the overall packaging, meeting the development needs of modern semiconductor technology.

[0048] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging method for a semiconductor chip, characterized in that, Including: Step S1, preparing a composite substrate with an intermediate layer; The composite substrate includes a first substrate and an intermediate layer. Micro-columns are formed on the surface of the first substrate in a matrix distribution. The gaps between the micro-columns are filled with a thermally decomposable polymer, and the intermediate layer covers the surface of the micro-columns; Step S2, laminating a chip layer on the surface of the composite substrate to form a preliminary encapsulation structure; Step S3, performing gradient heating bonding on the preliminary encapsulation structure, sequentially removing the thermally decomposable polymer and the intermediate layer, and forming a three-dimensional grid channel between the chip layer and the composite substrate; Step S4, filling a high thermal conductivity medium into the three-dimensional grid channel and curing to form a three-dimensional heat dissipation network; Step S5, laminating a heat dissipation cover on the top of the chip layer, and joining the heat dissipation cover to the edge of the composite substrate by laser welding to form a semiconductor chip encapsulation structure with high heat dissipation performance.

2. The encapsulation method of the semiconductor chip according to claim 1, wherein, The step S1 includes: Step S11, forming copper micro-columns in a matrix distribution on the surface of the first substrate; the height of the micro-columns is 20 - 50 μm, the diameter is 10 - 30 μm, and the pitch is 5 - 15 μm; Step S12, spin-coating a polycarbonate propylene solution in the gaps between the micro-columns, with the filling thickness covering 80 - 90% of the micro-column height, and forming a dense filling layer through thermal curing; Step S13, sequentially depositing an aluminum-titanium alloy on the surfaces of the micro-columns and the filling layer to form an intermediate layer with a thickness of 1 - 3 μm.

3. The encapsulation method of the semiconductor chip according to claim 2, wherein After step S13, step S1 further includes: Step S14, removing the intermediate layer on the surface of the filling layer, so that the intermediate layer only covers the surface of the micro-columns and forms a continuously covered metallized interface; Step S15, laser-etching pits with a diameter of 1 - 3 μm on the surface of the intermediate layer; Step S16, injecting boron nitride nanosheets into the pits.

4. The encapsulation method of the semiconductor chip according to any one of claims 1 to 3, characterized in that, The step S2 includes: Step S21, performing plasma activation treatment on the lamination surface of the chip layer, with the volume ratio of argon / oxygen mixed gas being 4:1, the radio frequency power being 300 W, and the treatment time being 120 s; Step S22, after positioning the chip layer and the composite substrate, applying gradient pressure for lamination; wherein, the vertical pressure in the first stage is 10 - 15 MPa, the temperature is 80 - 100 °C, and it is maintained for 30 s to cause plastic deformation of the intermediate layer; in the second stage, the pressure is increased to 20 - 25 MPa, the temperature is raised to 150 - 180 °C, and it is maintained for 60 s to fill the microscopic voids between the bottom of the chip layer and the micro-columns with the intermediate layer; Step S23, after the plastic deformation of the intermediate layer, the thickness of the intermediate layer is 0.2 - 0.5 μm, covering more than 98% of the bottom surface of the chip.

5. The encapsulation method of the semiconductor chip according to claim 4, characterized in that After step S23, step S2 further includes: Step S24, cooling down to below 50 °C at a rate of 2 °C / s in a nitrogen atmosphere and simultaneously relieving the pressure.

6. The packaging method of the semiconductor chip according to claim 1, wherein, The step S3 includes: Step S31, performing gradient heating on the preliminary encapsulation structure, under a nitrogen protection atmosphere, heating up to 280 - 300 °C at a rate of 5 °C / min and maintaining the temperature for 30 - 45 min to remove the thermally decomposable polymer; Step S32: Introduce an oxygen / argon mixed gas with a volume ratio of 1:5, heat it up to 450 - 480 °C at a rate of 3 - 5 °C / min and hold for 20 min to oxidize the intermediate layer of the aluminum-titanium alloy to form a composite oxide of aluminum oxide-titanium oxide; Step S33: Selectively etch the composite oxide with a phosphoric acid / acetic acid mixed solution with a volume ratio of 3:1, and the etching rate is 8 - 10 μm / h to obtain a formed three-dimensional grid channel.

7. The encapsulation method of the semiconductor chip according to claim 6, wherein After the step S33, step S3 further includes: Step S34: Perform ultrasonic micro-etching on the formed three-dimensional grid channel, apply ultrasonic waves at 40 kHz in 0.1 mol / L dilute sulfuric acid to remove nano-scale oxidation debris in the three-dimensional grid channel.

8. The encapsulation method of the semiconductor chip according to claim 1, wherein, The step S4 includes: Step S41: Perform plasma activation pretreatment on the inner wall of the three-dimensional grid channel; in an argon / hydrogen mixed atmosphere with a volume ratio of 9:1, the applied radio frequency power is 500 W, and the treatment time is 180 seconds; Step S42: Inject preheated liquid metal into the three-dimensional grid channel through vacuum negative pressure, and the injection rate is 0.51 mL / min; wherein, the preheating temperature is 80 - 100 °C, the liquid metal is a gallium-indium-tin alloy, the mass fraction of gallium is 60% - 65%, the mass fraction of indium is 20% - 25%, the mass fraction of tin is 15% - 20%, and 1 - 3% by volume of aluminum nitride nanowires are incorporated; Step S43: Perform solidification treatment on the liquid metal in the three-dimensional grid channel; wherein, in the first stage of solidification, cool down to 25 °C at a rate of 2 °C / min to preliminarily solidify the liquid metal; in the second stage of solidification, heat up to 180 - 200 °C under nitrogen protection and keep it warm for 30 minutes to generate a titanium tri-aluminum-aluminum nitride (Ti3Al-AlN) interfacial transition layer.

9. The encapsulation method of the semiconductor chip according to claim 1, wherein In the step S5, the heat dissipation cover is made of porous silicon carbide material with a pore diameter of 5 - 20 μm; micro-channels for lateral heat dissipation are etched on the surface of the heat dissipation cover.

10. A semiconductor chip packaging machine for implementing the semiconductor chip packaging method according to any one of claims 1 to 9, characterized in that, Including: A preparation module for preparing a composite substrate with an intermediate layer; wherein, the preparation module includes a forming unit, a filling unit, and a covering unit. The forming unit is used to form micro-columns distributed in a matrix on the surface of the first substrate, the filling unit is used to fill the gaps between the micro-columns with a thermally decomposable polymer, and the covering unit is used to cover the intermediate layer on the surface of the micro-columns; A lamination module for laminating the chip layer on the surface of the composite substrate to form a preliminary packaging structure; A heating and bonding module for performing gradient heating and bonding on the preliminary packaging structure, sequentially removing the thermally decomposable polymer and the intermediate layer, and forming a three-dimensional grid channel between the chip layer and the composite substrate; A three-dimensional heat dissipation network forming module for filling a high thermal conductivity medium into the three-dimensional grid channel and solidifying it to form a three-dimensional heat dissipation network; An assembly module for laminating a heat dissipation cover on the top of the chip layer and joining the heat dissipation cover to the edge of the composite substrate by laser welding to form a high heat dissipation semiconductor chip packaging structure.

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