Semiconductor device and method of making on-wafer chip underfill barrier

Abstract

Semiconductor devices and methods of making an on-wafer chip underfill barrier are disclosed. A semiconductor device has: a first semiconductor die; and a first insulating layer formed over the first semiconductor die. A trench is formed in the first insulating layer. A second insulating layer is formed over the first insulating layer. A recess is automatically formed in the second insulating layer over the trench as a portion of a formation process of the second insulating layer. A second semiconductor die is mounted over the second insulating layer. The recess completely surrounds the second semiconductor die in plan view. An underfill is dispensed between the first semiconductor die and the second semiconductor die.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly, to semiconductor devices and a method of fabricating a chip underfill barrier on a wafer. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, power conversion, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communication, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are constantly striving to fabricate smaller semiconductor devices to meet the needs of both electronic device manufacturers and consumers. When multiple semiconductor die are to be packaged together, one way to shrink the final device is to directly mount smaller die on a semiconductor wafer of a larger die. This is known as chip on wafer (CoW).

[0004] CoW requires underfill to be dispensed in a tight and narrow gap between the edge of the smaller die and solder bumps on the active surface of the larger die. At the same time, the reality of CoW devices means that 100% underfill coverage is required on all sides and corners of the smaller die. This requirement poses a challenge for underfill handling due to the risk of underfill overflowing the intended area and bridging surrounding solder bumps, which would result in reduced yield and reliability. Accordingly, there is a need for improved chip on wafer devices and manufacturing processes. Brief Description of the Drawings

[0005] Figures 1a to 1c Illustrates a semiconductor wafer having multiple semiconductor die separated by saw lines;

[0006] Figures 2a to 2m Illustrates forming a trench barrier in a first embodiment to prevent underfill diffusion on CoW;

[0007] Figures 3a to 3e Illustrates forming a trench barrier in a second embodiment to prevent underfill diffusion on CoW;

[0008] Figures 4a to 4f Illustrates forming a dam barrier in a third embodiment to prevent underfill diffusion on CoW; and

[0009] Figure 5a and Figure 5b Illustrates integrating a CoW device into a larger electronic device. Detailed Description

[0010] The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements throughout. Although the invention is described in terms of the best mode contemplated for attaining the present invention's objectives, those skilled in the art will appreciate that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents supported by the following disclosure and drawings. The features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numeral in the figures have similar functions to one another. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus, can refer to either a single semiconductor device or multiple semiconductor devices. The terms "semiconductor die" and "die" are synonymous. The terms "semiconductor wafer" and "wafer" are synonymous.

[0011] Generally, two complex manufacturing processes are used to fabricate semiconductor devices: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationships between voltage and current required to perform circuit functions.

[0012] Back-end manufacturing refers to dicing or singulating a finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scribed and broken along the non-functional regions of the wafer (referred to as saw streets or scribe lines). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are placed on a packaging substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads within the semiconductor package. The electrical connection can be made using conductive layers, bumps, columnar bumps, conductive solder paste, or wire bonding. An encapsulant or other molding material is deposited on the semiconductor package to provide physical support and electrical isolation. Then, the finished semiconductor package is inserted into an electrical system, and the functionality of the semiconductor device is made available to other system components.

[0013] Figure 1aA semiconductor wafer 100 is shown having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or electrical components 104 are formed on the wafer 100 and are separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide a cutting area to singulate the semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100 - 450 millimeters (mm).

[0014] Figure 1b A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a backside or non-active surface 108 and an active surface 110, and the active surface 110 includes analog or digital circuitry that is implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or on the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement an analog circuit or a digital circuit, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a memory, a power device, or other signal processing circuitry. The semiconductor die 104 may also include integrated passive devices (IPD) for RF signal processing, such as inductors, capacitors, and resistors.

[0015] A conductive layer 112 is formed on the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating processes, or other suitable metal deposition processes. The conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 operates as contact pads for the circuitry electrically connected to the active surface 110.

[0016] The conductive bump material is deposited on the conductive layer 112 using evaporation, electroplating, electroless plating, ball drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is joined to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form the bump 114. In one embodiment, the bump 114 is formed on a under bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The bump 114 can also be compression bonded or thermocompression bonded to the conductive layer 112.

[0017] In Figure 1c , a semiconductor wafer 100 is singulated into individual semiconductor die 104 by sawing through saw streets 106 using a saw blade or a laser cutting tool 118. The individual semiconductor die 104 can be inspected and electrically tested to identify known good die (KGD) or known good units (KGU) after singulation.

[0018] Figures 2a to 2m Illustrated is the formation of a chip on wafer (CoW) module using the semiconductor die 104. Figure 2a Shown is a partial cross-section of a semiconductor wafer 120 that will be the CoW wafer, and the semiconductor die 104 that will be the CoW chip. The semiconductor wafer 120 is similar to the semiconductor wafer 100, e.g., formed of similar materials, having active and passive electrical components formed within the semiconductor die 124, but is generally larger. The semiconductor die 124 includes contact pads 126 that are formed and function similar to the contact pads 112 of the semiconductor die 104.

[0019] A passivation layer 128 is formed over the active surface 130 of the semiconductor wafer 120. The passivation layer 128 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder mask, polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The passivation layer 128 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, thermal oxidation, or other suitable methods. The passivation layer 128 provides a protective coating for the active surface 130 and the contact pads 126 during the handling and processing of the semiconductor wafer 120 between the manufacturing steps for forming circuits in the active surface and the manufacturing steps illustrated and described below. Any of the insulating, dielectric, or passivation layers described above or below can be formed using any of the materials or methods described for the passivation layer 128.

[0020] An opening 132 is formed through the passivation layer 128 to expose the contact pad 126 and allow subsequent formation of an electrical connection through a conductive layer. The opening 132 is formed by laser ablation, chemical etching, mechanical drilling, photolithography, or other suitable methods.

[0021] From Figure 2b Continuing, only a single semiconductor die 124 is illustrated to provide more details of the processing performed. However, all of the illustrated steps occur at the wafer level before singulation by the saw street 134 to separate the dies 124 from each other. The semiconductor wafer 120 can include dozens, hundreds, or even thousands of semiconductor dies 124 that are all processed at once using the following steps shown only for a single semiconductor die in a batch process.

[0022] In Figure 2b , a dielectric layer 140 is formed over the active surface 130 and the passivation layer 128. The dielectric layer 140 is deposited to extend into the opening 132 of the passivation layer 128 and completely fill the opening 132, and cover completely up to the top surface of the passivation layer. The dielectric layer 140 completely covers the entire footprint of the wafer 120. The dielectric layer 140 is formed using a similar process and similar materials as described above for the passivation layer 128.

[0023] Figure 2c A mask 146 is shown deployed over the dielectric layer 140. In the illustrated embodiment, the dielectric layer 140 is a photolithography layer, so the light 148 passing through the opening 147 of the mask 146 modifies the molecular structure of the dielectric layer. When the dielectric layer 140 is in Figure 2dWhen developed and washed away in the [description], the openings 142 and the trenches 144 are formed to pass through the dielectric layer. In some embodiments, both the openings 142 and the trenches 144 are formed to pass completely through the dielectric layer 140 without extending into the contact pads 126 or the passivation layer 128.

[0024] The openings 142 are formed to pass through the dielectric layer to expose the contact pads 126 without exposing the passivation layer 128. The openings 142 are approximately concentric with the openings 132 of the passivation layer 128 such that each of the openings 142 extends through a corresponding one of the openings 132. In other embodiments, the openings 132 are not previously formed and the openings 142 are formed to pass through both the dielectric layer 140 and the passivation layer 128 in a single processing step. The openings 142 may be formed as described above for the openings 132.

[0025] The trenches 144 follow a continuous path that completely surrounds the area in which the semiconductor die 104 will be mounted, as shown below in Figure 2m for the recesses 162. In other embodiments, the trenches 144 are only formed in areas where there may be concern for underfill oozing to the solder bumps. The trenches 144 may be formed as described above for the openings 132, for example, by chemical etching, mechanical etching, or laser ablation. In one embodiment, the passivation layer 128 operates as an etch stop layer for an etch process for simultaneously forming both the openings 142 and the trenches 144. The material of the passivation layer 128 stops the etch process from extending below the dielectric layer 140 for the trenches 144 while the openings 142 are etched all the way down to the contact pads 126. In a laser ablation embodiment, the openings 142 may be formed with a higher laser output power or duration compared to the trenches 144 to extend deeper. In other embodiments, the trenches 144 extend into the passivation layer 128 or completely through the passivation layer 128.

[0026] In Figure 2eIn [the figure], the conductive layer 150 is formed above the dielectric layer 140. The conductive layer 150 is formed of the materials described above for the conductive layer 112 and is formed using the methods described above for the conductive layer 112. The conductive layer 150 is formed to completely cover the exposed top surfaces of the contact pads 126, the passivation layer 128, and the dielectric layer 140, and is then patterned, as illustrated. The conductive layer 150 is patterned to include conductive vias extending downward into the openings 142 to physically and electrically connect to the contact pads 126. The conductive layer 150 can be a conformal layer as illustrated, or completely fill the space of the openings 142. The conductive layer 150 is also patterned to include conductive traces fanning out from the contact pads 126 across the active surface 130. The conductive layer 150 optionally includes contact pads to which an overlying conductive layer will be connected.

[0027] In some embodiments, the circuitry of the semiconductor die 124 is arranged such that the contact pads of the conductive layer 126 to be connected to the semiconductor die 104 are all located within the boundaries formed by the trenches 144, and all contact pads for external interconnection are located outside the trenches. This allows the conductive layer 150 to be patterned without requiring conductive traces to cross the trenches 144. In other embodiments, the conductive traces of the conductive layer 150 are formed across the trenches 144. The conductive layer 150 is thin enough to be formed within the trenches 144 without severely affecting the intended functionality of the trenches.

[0028] In Figure 2f [the figure], an insulating layer 160 is formed above the conductive layer 150 and into the trenches 144, including completely filling the trenches. The insulating layer 150 is formed of the materials described above for the passivation layer 128 and is formed using the methods described above for the passivation layer 128. The insulating layer 160 completely covers the entire footprint of the wafer 120. The insulating layer 160 is a conformal layer that follows the contours of the underlying layers (e.g., the trenches 144 and the conductive vias of the conductive layer 150). The insulating layer 160 is formed to be thinner than the insulating layer 140 in some embodiments to ensure that the top surface of the insulating layer 160 conforms to the underlying contours. In one embodiment, the insulating layer 140 is 20 μm thick, while the insulating layer 150 is 10 μm thick.

[0029] The top surface of the insulating layer 160 above the trenches forms recesses 162 in the insulating layer 160. The recesses 162 are caused as a result of the insulating layer 160 being formed on the trenches 144, and thus follow the same path as the trenches and form a continuous circuit around the intended location for mounting the semiconductor die 104. When initially formed, the insulating layer 160 follows the topology of the trenches 144, thus automatically creating the recesses 162 during the formation or deposition process of the insulating layer.

[0030] In Figure 2gIn [the figure], the opening 164 is formed through the insulating layer 160 to expose the underlying contact pad of the conductive layer 150. The opening 164 is formed as described above for the opening 132, for example, by chemical etching or laser ablation.

[0031] In Figure 2h In [the figure], the conductive layers 170-172 are formed over the insulating layer 160 and into the opening 164. In one embodiment, the opening 164 outside the recess 162 has an under bump metallization (UBM) 170, and the UBM 170 is formed as a contact pad for large solder bumps to be deployed in a later step, while the opening 164 surrounded by the recess 162 is smaller and is configured to mount the die 104. If different material compositions or end products are desired, the UBM 170 can be formed in a manufacturing step separate from the contact pad 172. In another embodiment, the conductive material for both the UBM 170 and the contact pad 172 is deposited over the entire footprint of the wafer 120 and then patterned as illustrated. Both the UBM 170 and the contact pad 172 can include a wetting layer, a barrier layer, and an adhesion layer. If redistribution is needed to fan out or fan in from the contact pads of the conductive layer 150 to the final positions desired for connection to the semiconductor die 104, conductive traces can be formed. The conductive layers 170-172 follow the contour of the insulating layer 160. Thus, the UBM 170 and the contact pad 172 may more desirably be formed outside the footprint of the contact pad 126.

[0032] In Figure 2i In [the figure], the solder bumps 180 are formed on the UBM 170 as described above for the bumps 114 on the conductive layer 112 of the semiconductor die 104. The bumps 180 are larger than the bumps 114 and should be made at least tall enough to extend above the backside surface of the semiconductor die 104 once the smaller semiconductor die is mounted on the contact pad 172. In some embodiments, the layout of the wafer 120 is such that the recess 162 is deployed within 30-50 μm of the bumps 180.

[0033] The semiconductor die 104 is mounted to the contact pad 172 in Figure 2j by picking up the smaller semiconductor die and placing it over the semiconductor die 124 and lowering the semiconductor die 104 such that the bumps 114 rest on the contact pads. The bumps 114 are reflowed to mechanically attach and electrically connect the semiconductor die 104 to the semiconductor die 124. The semiconductor die 104 is electrically connected to the semiconductor die 124 through the bumps 114, the contact pad 172, and the conductive layer 150.

[0034] In Figure 2kIn , after installing the smaller semiconductor die, underfill 182 is dispensed into the gap remaining between semiconductor die 104 and semiconductor die 124. The underfill 182 can be an epoxy resin, an epoxy acrylate, any of the materials described above for the passivation layer 128, a polymer composite, or another suitable polymer. The underfill 182 is deposited as a liquid using a nozzle 184 located at a point along the perimeter of the semiconductor die 104. Capillary action distributes the underfill 182 from the nozzle 184 to fill the footprint of the semiconductor die 104.

[0035] Due to the small size of the semiconductor die 104 and the close lateral spacing between the semiconductor die 104 and the solder bumps 180, accurately dispensing the underfill 182 can be challenging. The underfill 182 may easily inadvertently spread out beyond the footprint of the semiconductor die 104, as shown in the detailed view of Figure 2l When some of the underfill 182 leaks out from under the semiconductor die 104, the underfill flows into the recess 162 and flows along the length of the recess parallel to the edge of the semiconductor die. The recess 162 blocks the underfill 182 from continuing to flow perpendicular to the edge of the semiconductor die 104 to reach the solder bumps 180 (which would have the potential to cause a failure in the final device). The underfill 182 flows along the recess 162 instead of flowing up to the opposite edge of the recess to reach the bumps 182. The recess 162 is formed continuously around a single semiconductor die to prevent the underfill from flowing from the semiconductor die to adjacent solder bumps. The recess 162 protects the bumps 180.

[0036] Figure 2m A plan view is shown to illustrate how the recess 162 extends completely around the semiconductor die 104 so that the underfill 182 is trapped by the recess, regardless of the direction in which the underfill inadvertently flows away from the smaller semiconductor die. In other embodiments, the trench 144 and thus the recess 162 are only formed in selected positions between the die 104 and the bumps 180 without completely surrounding the die 104. The underfill 182 reaches the recess 162 and then flows laterally within the recess instead of continuing to flow towards the bumps 180. The addition of the recess 162 formed using the trench 144 in the underlying insulating layer provides a wider process margin for underfill handling in CoW applications. The likelihood that the underfill 182 touches the solder bumps 180 or even bridges the two solder bumps 180 together is greatly reduced, thus increasing yield and reducing failures in the final devices formed.

[0037] Figures 3a to 3eAn alternative embodiment is illustrated, in which the trench is formed directly in the top insulating layer, rather than in the dielectric layer 140 that creates the recess in the top insulating layer. Except that the trench 144 has not been formed in the dielectric layer 140, Figure 3a From Figure 2e Continue. An insulating layer 200 is formed over the dielectric layer 140 and the conductive layer 150. The insulating layer 200 is substantially the same as the insulating layer 160, except that in the absence of the trench 144, the recess is not formed in the top surface of the insulating layer 200 as in the case of the recess 162. The insulating layer 200 has a flat top surface across the entire footprint of the wafer 120.

[0038] At Figure 3b In, trenches 202 and openings 204 are formed in or through the insulating layer 200. The trenches 202 are formed in a manner similar to the trenches 144, and like the trenches 144, the trenches 202 follow a path that surrounds the intended mounting location for the semiconductor die 104. The openings 204 are formed through the insulating layer 200 to expose the contact pads of the conductive layer 150 for subsequent electrical connection. The openings 204 and 202 are formed in a single etch step in some embodiments, similar to the method shown in Figure 2c above using the mask 146. At Figure 3c In, the UBM 170 and the contact pads 172 are formed as described above. The contact pads 172 for mounting the semiconductor die 104 are located within the trenches 202 and are completely surrounded by the trenches 202 in a plan view.

[0039] Figure 3d Illustrates the semiconductor die 104 mounted on the contact pads 172 and the underfill 182 applied between the semiconductor die 104 and 124. Figure 3e A detailed view of

[0040] Figures 4a to 4f illustrates how the trenches 202 capture the underfill 182 that overflows from the semiconductor die 104 before the underfill can reach and potentially bridge the conductive bumps 180. The underfill 182 flows laterally in the trenches 202 parallel to the edge of the semiconductor die 104 instead of continuing towards the bumps 180. The trenches 202 are formed continuously around a single semiconductor die to prevent the underfill from flowing from the semiconductor die to adjacent solder bumps. The trenches 202 protect the bumps 180.

[0040] Figures 4a to 4f Another embodiment is illustrated that has dams instead of trenches for blocking the flow of the underfill. Figure 4a Shows the insulating layer 200 formed over the dielectric layer 140 and the conductive layer 150 as in Figure 3a In. At Figure 4bAmong them, the UBM 170 and the contact pad 172 are formed as described above. In Figure 4c Among them, the bump 180 is formed on the UBM 170. The dam 210 is formed on the insulating layer 200 around the mounting position for the semiconductor die 104. The dam 210 is formed directly on the insulating layer of the substrate without requiring, for example, contact pads or other processing on the surface of the substrate before forming the dam. The dam 210 can thus be formed in any substrate design without requiring a predefined allocation area.

[0041] The dam 210 can be formed before or after the formation of the bump 180. The dam 210 follows the same or a similar path as the trenches 144 and 202 in a plan view to surround the intended mounting position of the semiconductor die 104. The dam 210 is formed of a mass top material or a liquid epoxy resin dispensed by a nozzle similar to the nozzle 184 that has no resin discharge and moves in the desired path for the dam while dispensing the insulating material. In some embodiments, a non-conductive material without resin is used.

[0042] In Figure 4d Among them, the semiconductor die 104 is mounted on the contact pad 172. The dam 210 completely surrounds the semiconductor die 104 in a plan view. The dam 210 is formed to be 30 to 50 micrometers (μm) away from the edge of the solder bump 180. In some embodiments, the dam 210 is formed after the flip-chip attachment of the semiconductor die 104. The height of the dam 210 is lower than the height of the semiconductor die 104 above the wafer 120.

[0043] As described above in Figure 4e Among them, the underfill 182 is dispensed. Figure 4f A detailed view showing some of the underfill 182 leaking out towards the bump 180 is shown. The underfill 182 flows to the dam 210 and is contained by the dam. The dam 210 stops the flow of the underfill 182 before the underfill reaches the bump 180 (which would potentially bridge two bumps and increase the likelihood of failure). The dam 210 is formed continuously around a single semiconductor die to prevent the underfill from flowing from the semiconductor die to adjacent solder bumps. The dam 210 protects the bump 180.

[0044] Figure 5a And Figure 5b Illustrates the integration of the CoW module (e.g., CoW module 220) described above into a larger electronic device 300. After completing one of the processes shown or described above, the wafer 120 is singulated through the saw street 134 to form Figure 5aThe CoW module 220 in. Monolithization can be accomplished by a saw blade, a laser cutting tool, or other suitable tool. A protective molding, encapsulant, insulating material, or insulating layer is optionally deposited over the top and side surfaces of the semiconductor die 124.

[0045] Figure 5a FIG. illustrates a partial cross-section of the CoW module 220 mounted to a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300. The bumps 180 are reflowed onto the conductive layer 304 of the PCB 302 to physically attach and electrically connect the CoW module 220 to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the CoW module 220 and the PCB 302. The semiconductor die 104 is electrically coupled to the semiconductor die 124 through the bumps 114, contact pads 172, and conductive layer 150. The semiconductor die 124 is electrically coupled to the conductive layer 304 through the conductive layer 150, UBM 170, and bumps 180. The semiconductor die 104 is indirectly coupled to the conductive layer 304 through the semiconductor die 124. In other embodiments, where the conductive layer 150 optionally bridges the trench 144, the semiconductor die 104 can be directly coupled to the conductive layer 304 through the conductive layer 150. The semiconductor die 104 may physically contact the PCB 302, or a gap may exist.

[0046] Figure 5b FIG. illustrates an electronic device 300 including a chip carrier substrate or PCB 302 having a CoW module 220 with multiple semiconductor packages deployed on the surface of the PCB 302. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0047] The electronic device 300 can be an independent system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 300 can be a sub-component of a larger system. For example, the electronic device 300 can be part of a tablet, cellular phone, digital camera, communication system, or other electronic device. Alternatively, the electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are crucial for the product to be accepted in the market. The distance between semiconductor devices can be reduced to achieve higher density. The PCB 302 can have a more irregular shape to conveniently fit into a more ergonomic and smaller device enclosure.

[0048] In Figure 5bIn [the figure], the PCB 302 provides a common substrate for the structural support and electrical interconnection of semiconductor packages deployed on the PCB. Conductive signal traces 304 are formed on the surface or within the layers of the PCB 302 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 304 provide electrical connectivity between each of the semiconductor packages, mounted components, and other external system components. The traces 304 also provide power and ground connections for each of the semiconductor packages.

[0049] In some embodiments, the semiconductor device has two levels of packaging. The first-level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, the semiconductor device may have only the first-level packaging, where the die is directly mechanically and electrically deployed on the PCB.

[0050] For illustrative purposes, several types of first-level packaging are shown on the PCB 302, including wirebond packaging 346 and flip chip 348. Additionally, several types of second-level packaging, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, quad flat no-lead package (QFN) 360, quad flat package 362, and embedded wafer-level ball grid array (eWLB) 364, are shown as being deployed on the PCB 302. In one embodiment, the eWLB 364 is a fan-out wafer-level package (Fo-WLP) or a fan-in wafer-level package (Fi-WLP).

[0051] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first- and second-level packaging types, as well as other electrical components, can be connected to the PCB 302. In some embodiments, the electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Since semiconductor packages include complex functionality, less expensive components and streamlined manufacturing processes can be used to manufacture the electronic devices. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0052] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method of fabricating a semiconductor device, comprising: Providing a first semiconductor die; Forming a first insulating layer over the first semiconductor die; Forming a trench in the first insulating layer; Forming a second insulating layer over the first insulating layer, wherein a recess is automatically formed in the second insulating layer over the trench as part of the process of forming the second insulating layer; Mounting a second semiconductor die over the second insulating layer, wherein the recess completely surrounds the second semiconductor die in a plan view; And Dispensing an underfill between the first semiconductor die and the second semiconductor die.

2. The method according to claim 1, wherein a portion of the underfill flows into the recess.

3. The method according to claim 1, further comprising: Dispensing the underfill to completely fill the footprint of the second semiconductor die.

4. The method according to claim 1, further comprising: Forming a first conductive layer between the first insulating layer and the second insulating layer.

5. The method according to claim 4, further comprising: Forming a second conductive layer over the second insulating layer, wherein the first semiconductor die is electrically coupled to the second semiconductor die through the first conductive layer and the second conductive layer.

6. The method according to claim 5, further comprising: Forming solder bumps on the second conductive layer outside the boundary formed by the recess.

7. A method of fabricating a semiconductor device, comprising: Providing a first semiconductor die; Forming a barrier over the first semiconductor die; Deploying a second semiconductor die over the first semiconductor die, wherein the barrier extends completely around the second semiconductor die; And Dispensing an underfill between the first semiconductor die and the second semiconductor die.

8. The method according to claim 7, further comprising: Forming the barrier by: Forming a first insulating layer over the first semiconductor die; And Forming a trench in the first insulating layer.

9. The method according to claim 8, further comprising: Forming the barrier by forming a second insulating layer over the first insulating layer, wherein a recess is automatically formed in the second insulating layer over the trench as part of the process of forming the second insulating layer.

10. The method according to claim 7, further comprising: Forming the barrier by dispensing an insulating material to form a dam.

11. A semiconductor device, comprising: A first semiconductor die; A barrier formed over the first semiconductor die; A second semiconductor die deployed over the first semiconductor die, wherein the barrier extends completely around the second semiconductor die; And An underfill dispensed between the first semiconductor die and the second semiconductor die.

12. The semiconductor device according to claim 11, further comprising: A first insulating layer formed over the first semiconductor die; And A trench formed in the first insulating layer.

13. The semiconductor device according to claim 12, further comprising: A second insulating layer formed over the first insulating layer, having a recess in the second insulating layer over the trench.

14. The semiconductor device according to claim 11, wherein the barrier includes a dam formed of an insulating material.

15. The semiconductor device according to claim 11, further comprising: A conductive layer formed over the first semiconductor die; And Contact pads formed over the conductive layer, wherein the second semiconductor die is mounted to the contact pads.

Images