Overcurrent protection circuit suitable for Class-AB operational amplifier output stage
By using up and down symmetrically distributed sinking and pumping current overcurrent protection circuits in the Class-AB op amp output stage, the damage problem of operation is solved during short circuit or current overload, and accurate current limiting is achieved without affecting the op amp gain, which is suitable for analog integrated circuits.
Patent Information
- Application Number
- CN202411923674.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-07-04
AI Technical Summary
The existing Class-AB op amp output stage is easily damaged when short circuit or current overload, and the existing current limiting method will cause the first-stage output impedance of the op amp to be reduced or the current cannot be accurately limited.
The overcurrent protection circuit of sinking and pumping current with symmetrical distribution of up and down is adopted to limit the current of PMOS and NMOS tubes respectively, and the accurate current limit is achieved using negative feedback. The circuit structure is simple and easy to layout.
Accurate copying and limiting of power tube current is achieved, reducing the impact on the output impedance and gain of the op amp, and is suitable for existing analog integrated circuits.
Smart Images
Figure CN120263119A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an overcurrent protection circuit, and particularly to an overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier. Background Art
[0002] In view of existing analog integrated circuits, some output voltages such as reference voltages have weak driving capabilities and cannot directly drive large loads. An additional operational amplifier is required as a buffer to provide driving capabilities and amplify the output voltage.
[0003] Currently, the Class-A amplifiers adopted can provide very good output linearity, but their efficiency is very low. The Class-B amplifiers adopted have high efficiency but serious distortion. Therefore, operational amplifiers designed with a Class-AB output stage can achieve rail-to-rail output at a lower quiescent current, enabling the current during large-signal establishment to be unrestricted by the quiescent current and providing a larger current to drive the load capacitance.
[0004] Taking the conventional folded cascode structure with a PMOS input for the first stage of an operational amplifier as an example. It adopts a PMOS folded input and folded cascode structure, and the output stage of the operational amplifier adopts a Class-AB structure. At the same time, the buffer is output through the chip pins to facilitate other peripheral devices to use the same reference voltage. When a short circuit occurs at the output terminal, directly grounded or connected to the power supply, a large current will be generated in the power transistor. As a result, the operational amplifier will be damaged due to excessive output power consumption. Therefore, there are short circuit and current overload problems at the output terminal of the Class-AB amplifier.
[0005] Currently, there are two common methods for limiting the short-circuit current of operational amplifiers. One is to add a clamping circuit to the main circuit. The other is to use it in conjunction with a clamping circuit, detect the gate potential of the output power transistor and compare it with a given voltage, and then control the gate potential of the power transistor through a feedback network.
[0006] However, if the first method is applied to traditional amplifiers, it will cause the output impedance of the first stage of the operational amplifier to decrease during current limiting, and the open-loop gain will decrease significantly. If the second method is adopted, although the problems of the decrease in the output impedance of the first stage and the significant decrease in the open-loop gain are avoided, the magnitude of the limiting current cannot be determined and accurate current limiting cannot be achieved.
[0007] In view of the above defects, the present inventor has actively carried out research and innovation in order to create an overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier, making it more valuable in the industry. Summary of the Invention
[0008] To solve the above technical problems, the object of the present invention is to provide an overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier.
[0009] The overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier according to the present invention, wherein: it is composed of a sinking overcurrent protection circuit and a sourcing overcurrent protection circuit which are symmetrically distributed up and down.
[0010] The sinking overcurrent protection circuit is used to limit the current of the output PMOS transistor M P10 The sourcing overcurrent protection circuit is used to limit the current of the output NMOS transistor M N7 Between the output PMOS transistor M P10 and the output NMOS transistor M N7 , a buffer output port V out is provided.
[0011] The sinking overcurrent protection circuit includes two resistors R1 and R2 with the same resistance value. One end of the resistor R1 is connected to the source of the PMOS transistor M P12 The drain of the PMOS transistor M P12 is connected to the drain of the NMOS transistor M N9 The drain of the NMOS transistor M N9 is connected to the source of the NMOS transistor M N8 The other end of the resistor R1 is connected to the drain of the PMOS transistor M P11 The source of the PMOS transistor M P11 is connected to a first positive voltage terminal V DD The source of the PMOS transistor M P11 is also connected to the source of the PMOS transistor M P15 The source of the PMOS transistor M P17 The source of the PMOS transistor M P18 is connected.
[0012] One end of the resistor R2 is connected to the source of the PMOS transistor M P13 The drain of the PMOS transistor M P13 is connected to the drain of the NMOS transistor M N11 The drain of the NMOS transistor M N11 is connected to the source of the NMOS transistor M N10 The upper drain of the PMOS transistor M P13 is connected to the gate of the PMOS transistor M P14 The drain of the PMOS transistor M P14 is connected to the gates of the NMOS transistor M N13 and the NMOS transistor M N14 is connected.
[0013] The source of the NMOS transistor M N13 is connected to the source of the output NMOS transistor M N7 The drain is connected to the drain of the PMOS transistor M P16 The drain of the PMOS transistor MP17 The drain and the gate, PMOS transistor M P18 The gate, the PMOS transistor M P16 The source is connected to PMOS transistor M P15 The drain, the NMOS transistor M N13 The source, NMOS transistor M N12 The source, NMOS transistor M N10 The source, NMOS transistor M N8 The source is connected to the first ground terminal.
[0014] The current-drawing overcurrent protection circuit includes two resistors R3 and R4 with the same resistance value. One end of the resistor R3 is connected to NMOS transistor M N15 The source, NMOS transistor M N15 The drain is connected to PMOS transistor M P20 The drain, PMOS transistor M P20 The source is connected to PMOS transistor M P19 The drain.
[0015] The other end of the resistor R3 is connected to NMOS transistor M N14 The drain, NMOS transistor M N14 The source is connected to the second ground terminal, the NMOS transistor M N14 , and its source is also connected to NMOS transistor M N18 The source, NMOS transistor M N20 The source, NMOS transistor M N21 The source.
[0016] One end of the resistor R4 is connected to the resistor R2. The other end of the resistor R4 is connected to NMOS transistor M N16 The source, NMOS transistor M N16 The drain is connected to PMOS transistor M P22 The drain, PMOS transistor M P22 The source is connected to PMOS transistor M P21 The drain.
[0017] The NMOS transistor M N16 The upper drain is connected to NMOS transistor M N17 The gate, the NMOS transistor M N17 The drain is connected to PMOS transistor M P23 The gate, PMOS transistor M P24 The gate.
[0018] The PMOS transistor M P21 The source is connected to the second positive voltage terminal V DD , the second positive voltage terminal V DD is also connected to PMOS transistor M P23 The source, PMOS transistor M P24Source electrode.
[0019] The PMOS transistor M P24 A NMOS transistor M is further connected to the drain N19 Drain, NMOS transistor M N20 Drain and gate, NMOS transistor M N21 Gate, NMOS transistor M N19 The source electrode is connected to the NMOS transistor M N18 Drain. The NMOS transistor M N21 Drain and NMOS transistor M N14 Gate, NMOS transistor M N7 The gate is connected; the PMOS transistor M P18 Drain and PMOS transistor M P11 Gate, PMOS transistor M P10 The gate is connected.
[0020] Further, the above overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier, wherein the PMOS transistor M P12 and the PMOS transistor M P13 have the same aspect ratio, the NMOS transistor M N8 and the NMOS transistor M N10 have the same aspect ratio, the NMOS transistor M N9 and the NMOS transistor M N11 have the same aspect ratio, the drain voltage V P11 of the PMOS transistor M D,P11 is equal to the buffer output V out
[0021] By means of the above solution, the present invention has at least the following advantages:
[0022] 1. It can effectively utilize negative feedback in the circuit to accurately copy the current of the power transistor, thereby effectively setting the magnitude of the limiting current.
[0023] 2. The current limiting circuit has a relatively small impact on the output impedance of the operational amplifier that may be generated, and the impact on the gain of the operational amplifier during operation can be ignored, meeting the ultimate accurate current limiting requirements.
[0024] 3. The overall constructed circuit is simple, easy to layout, and can be applied to existing analog integrated circuits.
[0025] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and implement it in accordance with the content of the specification, the following is a detailed description of the preferred embodiment of the present invention in conjunction with the drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a schematic structural diagram of an overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier according to the present invention. Specific Embodiments
[0027] The following combines the accompanying drawings and embodiments to further describe in detail the specific embodiments of the present invention. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.
[0028] As Figure 1 The overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier is characterized in that it is composed of a sink current overcurrent protection circuit and a source current overcurrent protection circuit distributed symmetrically up and down. Specifically, the sink current overcurrent protection circuit is used to limit the current of the output PMOS transistor M P10 and the source current overcurrent protection circuit is used to limit the current of the output NMOS transistor M N7 . Between the output PMOS transistor M P10 and the output NMOS transistor M N7 , a buffer output port V out is provided. During implementation, the sink current overcurrent protection circuit includes two resistors R1 and R2 with the same resistance value.
[0029] During implementation, one end of the resistor R1 is connected to the source of the PMOS transistor M P12 , the drain of the PMOS transistor M P12 is connected to the drain of the NMOS transistor M N9 , and the source of the NMOS transistor M N9 is connected to the drain of the NMOS transistor M N8 . At the same time, the other end of the resistor R1 is connected to the drain of the PMOS transistor M P11 , and the source of the PMOS transistor M P11 is connected to a first positive voltage terminal V DD .
[0030] The PMOS transistor M P11 adopted in the present invention has its source also connected to the sources of the PMOS transistors M P15 , M P17 , M P18 . At the same time, one end of the resistor R2 is connected to the source of the PMOS transistor M P13 , the drain of the PMOS transistor M P13 is connected to the drain of the NMOS transistor M N11 , and the source of the NMOS transistor M N11 is connected to the drain of the NMOS transistor M N10 .
[0031] At the same time, the upper drain of the adopted PMOS transistor M P13 is connected to the gate of the PMOS transistor M P14 , PMOS transistor MP14 The drain is connected to NMOS transistor M N13 The gate, NMOS transistor M N14 The gate. NMOS transistor M N13 The source is connected to output NMOS transistor M N7 The source and drain are connected to PMOS transistor M P16 The drain, PMOS transistor M P17 The drain and gate, PMOS transistor M P18 The gate. And, PMOS transistor M P16 The source is connected to PMOS transistor M P15 The drain, NMOS transistor M N13 The source, NMOS transistor M N12 The source, NMOS transistor M N10 The source, NMOS transistor M N8 The source is connected to the first ground terminal.
[0032] Correspondingly, the current-drawing overcurrent protection circuit adopted by the present invention includes two resistors R3 and R4 with the same resistance value. One end of resistor R3 is connected to NMOS transistor M N15 The source, NMOS transistor M N15 The drain is connected to PMOS transistor M P20 The drain, PMOS transistor M P20 The source is connected to PMOS transistor M P19 The drain. At the same time, the other end of resistor R3 is connected to NMOS transistor M N14 The drain, NMOS transistor M N14 The source is connected to the second ground terminal.
[0033] The NMOS transistor M adopted by the present invention N14 , and its source is also connected to NMOS transistor M N18 The source, NMOS transistor M N20 The source, NMOS transistor M N21 The source.
[0034] During implementation, one end of resistor R4 is connected to resistor R2. The other end of resistor R4 is connected to NMOS transistor M N16 The source, NMOS transistor M N16 The drain is connected to PMOS transistor M P22 The drain, PMOS transistor M P22 The source is connected to PMOS transistor M P21 The drain.
[0035] At the same time, NMOS transistor M N16 The upper drain is connected to NMOS transistor M N17 The gate, NMOS transistor M N17 The drain is connected to PMOS transistor M P23 The gate, PMOS transistor MP24 Gate, PMOS transistor M P21 The source is connected to the second positive voltage terminal V DD .
[0036] During the circuit layout process, the second positive voltage terminal V DD is also connected to the source of PMOS transistor M P23 the source of PMOS transistor M P24 the source of PMOS transistor M P24 The drain is also connected to the NMOS transistor M N19 the drain of NMOS transistor M N20 the drain and gate of NMOS transistor M N21 the gate of NMOS transistor M N19 The source is connected to the drain of NMOS transistor M N18 the drain.
[0037] Furthermore, the drain of NMOS transistor M N21 and the gate of NMOS transistor M N14 the gate of NMOS transistor M N7 are connected; the drain of PMOS transistor M P18 and the gate of PMOS transistor M P11 the gate of PMOS transistor M P10 are connected.
[0038] In combination with a preferred embodiment of the present invention, the aspect ratios of PMOS transistor M P12 and PMOS transistor M P13 are the same, the aspect ratios of NMOS transistor M N8 and NMOS transistor M N10 are the same, and the aspect ratios of NMOS transistor M N9 and NMOS transistor M N11 are the same. During implementation, through the negative feedback effect of PMOS transistor M P14 , the drain voltage V P11 of PMOS transistor M D,P11 can be made equal to the buffer output V out .
[0039] The working principle of the present invention is as follows:
[0040] Through the circuit layout of the present invention, the power transistor PMOS transistor M P10 that provides a large output current in the operational amplifier P11 and PMOS transistor M
[0041] adopt unit transistors of the same size, and the ratio of the number of their parallel connections is set to m, where m is much greater than 1. P10 At the same time, PMOS transistor M P11The gate voltages are the same, and the drain-source voltages of both are almost exactly equal. The PMOS transistor M P11 The drain-source current can be expressed as I out / m. Among them, I out is the buffer output current provided by the power transistor PMOS transistor M P10 .
[0042] During implementation, the current of the NMOS transistor M N8 is provided by the bias circuit and is set as I b1 . Thus, the currents of the PMOS transistor M P14 and the NMOS transistor M N12 can be expressed as I out / m - I b1 .
[0043] Similarly, the NMOS transistor M N12 and the NMOS transistor M N13 adopt unit transistors of the same size, and the ratio of the number of their parallel connections is set as n. If the NMOS transistor M N13 works in the saturation region, it means its current is n·(I out / m - I b1 ). Compare this current with the preset comparison current I P15 of the PMOS transistor M b2 , and there are the following two cases:
[0044] If this current is less than I b2 , then no current will flow through the PMOS transistor M P17 , the PMOS transistor M P18 . Thus, no current is injected into the main operational amplifier, causing the current limiting loop not to work.
[0045] If this current is greater than I b2 , then the excess current will flow through the PMOS transistor M P17 . After that, the excess current copies and flows into the high-impedance point V P18 of the main operational amplifier through the PMOS transistor M x . Thus, the current limiting loop starts to work, forming feedback to suppress the growth of the output current.
[0046] Thus, when the gain of the current limiting loop is much greater than the gain of the main operational amplifier loop, the feedback loop of the main operational amplifier no longer works, and the output current is controlled by the current limiting loop and restricted within a certain current range. During implementation, by setting I b1 , I b2 and the values of m and n, the current limiting magnitude of the overcurrent protection circuit can be determined, and its current limiting magnitude is I out = m·(I b2 / n + I b1 ), which can be set according to needs.
[0047] Moreover, during the implementation of the present invention, the overcurrent protection principles for the sink current and the source current are the same. Since the same circuit structure and principle are adopted, the overcurrent protection circuit for the source current will not be elaborated here. Because the current limiting loop and the main op-amp of the buffer share the output high-impedance node and the Miller compensation of the first stage. Therefore, the two-stage loop stability of the current limiting loop can still be ensured.
[0048] As can be seen from the above textual description and in combination with the accompanying drawings, after adopting the present invention, the following advantages are achieved:
[0049] 1. It can effectively utilize the negative feedback in the circuit to accurately replicate the current of the power transistor, thereby effectively setting the magnitude of the limiting current.
[0050] 2. The current limiting circuit has little impact on the output impedance of the op-amp that may be affected, and the impact on the gain of the op-amp during operation can be ignored, meeting the final accurate current limiting requirements.
[0051] 3. The overall constructed circuit is simple, easy to layout, and can be applied to existing analog integrated circuits.
[0052] In addition, the orientation or positional relationship described in the present invention is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or structure referred to must have a specific orientation, or be operated in a specific orientation structure. Therefore, it should not be construed as a limitation of the present invention.
[0053] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the technical principle of the present invention, several improvements and modifications can still be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. An overcurrent protection circuit applicable to the output stage of a Class-AB operational amplifier, characterized in that: It is composed of a sink current overcurrent protection circuit and a source current overcurrent protection circuit which are symmetrically distributed up and down. The sink current overcurrent protection circuit is used to limit the current of the output PMOS transistor M P10 ; the source current overcurrent protection circuit is used to limit the current of the output NMOS transistor M N7 ; between the output PMOS transistor M P10 and the output NMOS transistor M N7 , a buffer output port V out is provided. The sink current overcurrent protection circuit includes two resistors R1 and R2 with the same resistance value. One end of the resistor R1 is connected to the source electrode of the PMOS transistor M P12 and the drain electrode of the PMOS transistor M is connected to the drain electrode of the NMOS transistor M P12 One end of the resistor R1 is connected to the source electrode of the PMOS transistor M N9 and the drain electrode of the PMOS transistor M is connected to the drain electrode of the NMOS transistor M N9 One end of the resistor R1 is connected to the source electrode of the PMOS transistor M N8 and the drain electrode of the NMOS transistor M The other end of the resistor R1 is connected to the PMOS transistor M P11 through its drain. The source of the PMOS transistor M P11 is connected to a first positive voltage terminal V DD , The PMOS transistor M P11 , and its source is also connected to the source of the PMOS transistor M P15 source, the source of the PMOS transistor M P17 source, the source of the PMOS transistor M P18 source. One end of the resistor R2 is connected to the source electrode of the PMOS transistor M P13 and the drain electrode of the PMOS transistor M is connected to the drain electrode of the NMOS transistor M P13 One end of the resistor R2 is connected to the source electrode of the PMOS transistor M N11 and the drain electrode of the PMOS transistor M is connected to the drain electrode of the NMOS transistor M N11 One end of the resistor R2 is connected to the source electrode of the PMOS transistor M N10 and the drain electrode of the PMOS transistor M is connected to the drain electrode of the NMOS transistor M The PMOS transistor M P13 has its upper drain connected to the PMOS transistor M P14 and its gate. The PMOS transistor M P14 has its drain connected to the NMOS transistor M N13 and its gate, and the NMOS transistor M N14 and its gate. The NMOS transistor M N13 The source is connected to the output NMOS transistor M N7 The source and drain are connected to the PMOS transistor M P16 The drain, PMOS transistor M P17 The drain and gate, PMOS transistor M P18 The gate, The PMOS transistor M P16 has its source connected to the PMOS transistor M P15 and its drain The NMOS transistor M N13 The source electrode, the NMOS transistor M N12 The source electrode, the NMOS transistor M N10 The source electrode, the NMOS transistor M N8 The source electrode is connected to the first ground terminal; The source current overcurrent protection circuit includes two resistors R3 and R4 with the same resistance value. One end of the resistor R3 is connected to the NMOS transistor M N15 source, and the NMOS transistor M N15 drain is connected to the PMOS transistor M P20 drain, and the PMOS transistor M P20 source is connected to the PMOS transistor M P19 drain, The other end of the resistor R3 is connected to the drain of the NMOS transistor M N14 and the source of the NMOS transistor M N14 is connected to the second ground terminal The NMOS transistor M N14 , whose source is also connected to the source of the NMOS transistor M N18 , the source of the NMOS transistor M N20 , the source of the NMOS transistor M N21 , the source One end of the resistor R4 is connected to the resistor R2. The other end of the resistor R4 is connected to the source of the NMOS transistor M N16 and the drain of the NMOS transistor M is connected to the drain of the PMOS transistor M N16 and the source of the PMOS transistor M is connected to the drain of the PMOS transistor M P22 P22 P21 The NMOS transistor M N16 has its upper drain connected to the NMOS transistor M N17 gate, and the NMOS transistor M N17 has its drain connected to the PMOS transistor M P23 gate, the PMOS transistor M P24 gate, The PMOS transistor M P21 has its source connected to a second positive voltage terminal V DD , The second positive voltage terminal V DD is also connected to a PMOS transistor M P23 source, the PMOS transistor M P24 source The PMOS transistor M P24 The drain of which is also connected to the NMOS transistor M N19 The drain of the NMOS transistor M N20 The drain and the gate of the NMOS transistor M N21 The gate of the NMOS transistor M N19 The source is connected to the drain of the NMOS transistor M N18 The drain, The NMOS transistor M N21 The drain and the NMOS transistor M N14 The gate, the NMOS transistor M N7 The gates are connected; the PMOS transistor M P18 The drain and the PMOS transistor M P11 The gate, the PMOS transistor M P10 The gates are connected.
2. The overcurrent protection circuit applicable to the Class-AB operational amplifier output stage according to claim 1, wherein: The PMOS transistor M P12 and the PMOS transistor M P13 have the same width-to-length ratio. The NMOS transistor M N8 and the NMOS transistor M N10 have the same width-to-length ratio. The NMOS transistor M N9 and the NMOS transistor M N11 have the same width-to-length ratio. The drain voltage V P11 of the PMOS transistor M D,P11 is equal to the buffer output V out .