High-voltage high-power distributed power amplifier and design method thereof

Abstract

The invention discloses a high-voltage high-power distributed power amplifier and a design method thereof, and belongs to the field of microelectronics. According to the power amplifier, a two-stage cascade distributed amplification structure is constructed based on a specific GaN high electron mobility transistor process. The key technical points comprise an innovative transistor drain electrode gradient type source-drain spacing design, so that the breakdown voltage is effectively improved; the second-stage part adopts a two-cell parallel transistor, so that the output capability and the heat dissipation area are increased; designing a matching network by using a load traction technology, and matching the optimal output impedance of the transistor to a target load; layout layout is elaborately planned, thermal stability design is carried out, and long-term reliable operation is guaranteed. Through test verification, the power amplifier realizes ultra-wideband high-power output under high voltage within a set frequency band, and has the characteristics of high power gain and high efficiency.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics, and particularly to a high-voltage high-power distributed power amplifier and its design method. Background Art

[0002] The research and application of the third-generation wide bandgap semiconductor materials represented by GaN are currently at the forefront and hotspots of global semiconductor research. GaN materials have the characteristics of wide bandgap width and high breakdown electric field, enabling them to obtain high output power in a relatively high frequency range. At the same time, the characteristics of high electron mobility and high thermal conductivity of GaN materials are also very suitable for high-efficiency broadband power devices. GaN-based materials are currently the mainstream semiconductor materials for the development of high-frequency, broadband, high-efficiency, and high-power electronic devices.

[0003] MMIC has high integration and is very suitable for the current miniaturization requirements. It is of great significance to develop a power amplifier that can output sufficient high power on a small single chip. The distributed power amplifier can achieve bandwidths of multiple octaves. This structure uses the input capacitance, output capacitance, and inductance elements of transistors to form artificial transmission lines for the gate and drain. When the transmission line load matches the characteristic impedance of the transmission line, it is equivalent to a lossy uniform transmission line without frequency limitation, enabling the radio frequency signal to be transmitted in the transmission line in a traveling wave manner, which is a common structure for ultra-wideband power amplifiers. Limited by problems such as the output capacity of the die, heat dissipation, and signal phase synchronization, the output power of the distributed power amplifier is limited. Summary of the Invention

[0004] The purpose of the present invention is to overcome one or more deficiencies of the prior art and provide a high-voltage high-power distributed power amplifier and its design method.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A high-voltage high-power distributed power amplifier, characterized in that it includes two cascaded distributed amplification structures, based on 0.25μm GaN high electron mobility transistor process, with a working frequency of 0.3 - 6.3 GHz; the first stage uses three sections of transistors, and the gate widths are distributed as 10×80μm, 8×65μm, 8×50μm; the second stage uses five sections of transistors, the first four sections are each two-cell parallel transistors, and the gate widths of a single cell are 10×110μm, 10×55μm, 8×100μm, 8×95μm respectively, and the fifth section is a single-cell transistor with a gate width of 8×80μm; the drain of the transistor uses a gradient source-drain spacing structure, and the source-drain spacing decreases from the middle to both ends, with the minimum spacing increased by 0.4μm, and the first four sections of the second stage increase the output capacity and heat dissipation area through two-cell parallel connection;

[0007] The bias network, the inter-stage matching network, and the output matching network are integrated into the distributed amplification structure; the second stage serves as the output stage, and its structure includes a non-uniform transistor arrangement and a drain feeding design;

[0008] The output matching network includes an in-die drain bias inductor, a drain transmission line, and an LC structure to achieve the matching of the optimal output impedance to a 50-ohm load.

[0009] Furthermore, in the drain structure of the transistor, the source-drain spacing of the source strip and the drain strip is distributed in a gradient, satisfying d1 > d2 > d3, and d1 - d = 0.8 μm, d2 - d = 0.4 μm, d3 = d, (where d is the minimum source-drain spacing, corresponding to the source-drain spacing at both ends; d2 is the adjacent source-drain spacing in the middle region; d1 is the maximum source-drain spacing in the middle position). Through the gradient design, the source-drain spacing decreases by 0.4 μm from the middle to both ends in turn, that is, the difference between adjacent spacings is 0.4 μm, and the difference between the maximum spacing and the minimum spacing is 0.8 μm. Here, d is the minimum source-drain spacing, and d1, d2, and d3 are the source strip and drain strip spacings in the transistor drain structure from the middle to both ends, respectively. Specifically, d1 is the source strip and drain strip spacing in the middle position of the transistor drain structure, d2 is the source strip and drain strip spacing near the middle region, and d3 is the source strip and drain strip spacing at both ends (i.e., the minimum spacing d). By increasing the source-drain spacing, the breakdown voltage of the device is increased by more than 80 V to adapt to a 48 V drain voltage.

[0010] Furthermore, a capacitor is connected in parallel with a resistor in series in the transistor gate to form a stable circuit. The capacitor is used to reduce the input capacitance and increase the cut-off frequency, and the resistor is used to suppress the low-frequency gain and enhance the circuit stability to prevent low-frequency self-oscillation.

[0011] Furthermore, the bias network includes in-die drain and gate bias inductors. The drain bias capacitor is placed outside the die, and the gate bias capacitor is placed inside the die; a resistor is connected in series in the gate bias network to eliminate gate oscillation and enhance stability.

[0012] Furthermore, the inter-stage matching network includes a first-stage drain non-uniform transmission line, a second-stage gate transmission line, an RC stable circuit, and a 50-ohm impedance connection line; the input matching network includes an RC stable circuit, a gate transmission line, a gate bias circuit, and a parallel capacitance matching stub. A DC-blocking capacitor is connected in series at the input end to prevent DC from flowing into the RF signal source.

[0013] Furthermore, the second-stage output stage adopts a non-uniform structure, and the output impedances of each section of transistors are different. The characteristic impedance of the drain transmission line is designed according to the die size; the drain feeding position is set between the third and fourth transistors to reduce the voltage difference between the die cores of each section; the output end realizes impedance transformation through a parallel matching capacitor, a series DC-blocking capacitor, and a drain bias inductor and a microstrip line together.

[0014] Furthermore, the layout adopts a vertical layout. The active area transistors adopt a source cross-gate grounded method, and the vias are far away from the gate bars to reduce the thermal resistance. The distance between the second and third transistors with the largest overcurrent in the second stage is increased, and sufficient layout area is reserved for the drain bias inductor to optimize the thermal stability.

[0015] A design method for a high-voltage high-power distributed power amplifier includes the following steps:

[0016] (1) Die selection: According to the gain and power requirements, determine the gate width distribution of the three-stage transistors in the first stage and the five-stage transistors in the second stage. The first four stages in the second stage adopt a two-cell parallel structure;

[0017] (2) Stable circuit design: Connect a capacitor in series with the resistor at the gate to increase the cut-off frequency and suppress low-frequency self-oscillation;

[0018] (3) Bias network design: Use on-chip bias inductors, with the drain bias capacitor external and the gate bias capacitor internal, and a resistor in series with the gate to enhance stability;

[0019] (4) Matching network design: The input and inter-stage matching adopt non-uniform transmission lines, 50-ohm impedance lines, and LC structures, and the output matching is achieved through non-uniform drain transmission lines, optimized feed positions, and LC networks to achieve broadband matching;

[0020] (5) Layout: Vertical layout, increase the distance between transistors in the high-heat area, source cross-gate grounded and optimize the via positions to reduce the thermal resistance.

[0021] The beneficial effects of the present invention are:

[0022] (1) The two-stage cascaded distributed amplification structure, specific transistor selection and layout, combined with the optimized output matching network, achieve high-voltage ultra-wideband high-power output, meeting the power requirements of various application scenarios;

[0023] (2) The stable circuit design of the transistor gate, bias network optimization, combined with the unique drain structure and reasonable feed position, suppress self-oscillation and oscillation, reduce the voltage difference, and ensure the stable operation of the circuit within a wide frequency band;

[0024] (3) Thermal stability designs such as vertical layout, source cross-gate grounded method, and increasing the distance between transistors in the high-heat area reduce the thermal resistance, improve the heat dissipation capacity, and enhance the long-term reliability of the chip. Description of the Drawings

[0025] Figure 1 It is a schematic diagram of the drain gradient source-drain spacing structure of the power amplifier transistor;

[0026] Figure 2 It is a diagram of the overall circuit architecture of the power amplifier and the connection relationship of each stage;

[0027] Figure 3 Schematic diagram of signal transmission and bias circuit for key nodes of power amplifier;

[0028] Figure 4 Schematic diagram of layout and thermal stability design of power amplifier layout. Specific implementation manners

[0029] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

[0030] Parameter interpretations in the figure:

[0031] D is the drain, the drain electrode of the transistor, connecting the drain bias circuit and the output matching network; S is the source, the source electrode of the transistor, usually grounded to form a current loop; VD1 is the first-stage drain bias voltage, providing a DC bias voltage for the first-stage transistor, and the voltage value needs to match the device operating conditions; VD2 is the second-stage drain bias voltage, providing a DC bias voltage for the second-stage transistor, usually the same as VD1 to ensure the stability of multi-stage amplification; VG1 is the first-stage gate bias voltage, controlling the gate potential of the first-stage transistor and adjusting the operating point; RF in is the RF input port, accessing the RF signal source, the front-end interface of the input matching network; RF out is the RF output port, connecting to a 50Ω load, the back-end interface of the output matching network; off-chip means that components such as bias capacitors are located outside the chip and are connected to the on-chip inductor through bonding wires.

[0032] Embodiment 1: High-voltage high-power distributed power amplifier based on optimized source-drain spacing gradient:

[0033] 1. Die structure design:

[0034] Based on the 0.25μm GaN high electron mobility transistor process, the die is designed. The first stage selects three-section transistors with gate widths distributed as 10×80μm, 8×65μm, and 8×50μm; the second stage uses five-section transistors. The first four sections are two-cell parallel transistors per section, and the single-cell gate widths are 10×110μm, 10×55μm, 8×100μm, and 8×95μm respectively. The fifth section is a single-cell transistor with a gate width of 8×80μm.

[0035] The drain of the transistor adopts a gradient source-drain spacing structure as Figure 1As shown, the source-drain spacing decreases from the middle to both ends, and the minimum spacing increases by 0.4 μm, that is, d1 > d2 > d3 is satisfied, and d1 - d = 0.8 μm, d2 - d = 0.4 μm, d3 = d (d is the minimum source-drain spacing). This structure increases the channel area and makes the electric field distribution more uniform. Taking the middle source-drain spacing d1 as an example, it is set to 1.4 μm in actual manufacturing. Compared with the conventional structure, it effectively reduces the peak value of the electric field intensity in the channel. Through simulation analysis, it can be seen that in the conventional structure, when the high power is output, the electric field intensity in the channel is likely to concentrate in some areas, resulting in too high local electric field. However, the gradient structure of this embodiment effectively alleviates this situation, and the electric field intensity distribution is more uniform, thereby increasing the breakdown voltage of the device. After testing and verification, the breakdown voltage of the device using this structure has increased by 85 V and can stably adapt to a drain voltage of 48 V.

[0036] 2. Circuit design:

[0037] Refer to Figure 2 , a stable circuit is formed by connecting a capacitor in series with the transistor gate and a resistor in parallel (stable circuit part). A suitable capacitor is selected, such as a 0.8 pF capacitor, to reduce the input capacitance of the transistor, thereby increasing the cut-off frequency of the distributed power amplifier; at the same time, a 50 Ω resistor is connected in parallel to appropriately reduce the low-frequency gain without losing the high-frequency gain, enhance the circuit stability, and effectively prevent the circuit from self-oscillating at low frequencies. In actual testing, after adding this stable circuit, the low-frequency gain is effectively controlled, the stability of the circuit in the entire operating frequency band is significantly improved, and the self-oscillation phenomenon is effectively suppressed.

[0038] The bias network includes on-chip drain and gate bias inductors ( Figure 2 Ld1, Ld2, Lg1, Lg2 in

[0039] The inter-stage matching network includes the first-stage drain non-uniform transmission line, the second-stage gate transmission line, the RC stable circuit, and the 50-ohm impedance connection line ( Figure 2 the inter-stage matching network part in ). The first-stage drain transmission line adopts a non-uniform structure. According to the impedance requirements at different positions, the characteristic impedance of the transmission line is designed to gradually change from the starting end to the ending end to achieve better matching with the subsequent circuit. The input matching network includes the RC stable circuit, the gate transmission line, the gate bias circuit, and the parallel capacitor matching stub. A DC blocking capacitor is connected in series at the input end to prevent DC from flowing into the RF signal source.Figure 2 The input matching network part). By precisely calculating and optimizing the parameters of each component, the input matching network achieves good matching effects within the frequency band of 0.3 - 6.3 GHz, effectively reducing the input standing wave ratio.

[0040] The output matching network includes an in-drain bias inductor, a drain transmission line, and an LC structure ( Figure 2 the output matching network part in it). The drain transmission line adopts a non-uniform structure, and the output impedance of each transistor section is different. The characteristic impedance of the drain transmission line is designed according to the die size. The drain feeding position is set between the third and fourth transistors ( Figure 2 the drain feeding position in it), reducing the voltage difference between the die sections of each stage. The output end realizes impedance transformation through a parallel matching capacitor and a series DC blocking capacitor, together with the drain bias inductor and the microstrip line, matching the optimal output impedance of the transistor to a 50-ohm load impedance. During the actual debugging process, by adjusting the parameters of each component in the output matching network, the power amplifier can achieve efficient power output throughout the frequency band.

[0041] 3. Layout design:

[0042] Refer to Figure 4 , the layout adopts a vertical layout. The transistors in the active region adopt the source cross-gate grounding method, and the vias are far away from the gate bars to reduce the thermal resistance. Since the chip area is limited and there are many die in the active region, heat is concentrated, and the heat dissipation problem is crucial. In this embodiment, the distance between the second and third transistors with the largest overcurrent in the second stage is increased, leaving enough space for heat dissipation; enough layout areas are also reserved for the drain bias inductors to ensure their normal operation and not affect the performance of other components. At the same time, by utilizing the good thermal conductivity of the substrate SiC and optimizing the position and number of vias, the chip thermal resistance is further reduced. For example, the number of vias is increased in the high-heat region, enabling heat to be conducted to the substrate more quickly, thereby improving the long-term reliability of the chip.

[0043] Refer to Figure 3 , from which the key circuit connections and signal transmission paths of the power amplifier can be seen. From the overall layout, the association of the two-stage amplification structure and the position distribution of the bias circuit.

[0044] In the circuit connection part, the input matching network is located on the left side and includes the RC stabilization circuit of the first stage, the gate transmission line, and the gate bias circuit. Its input terminal is connected in series with a DC-blocking capacitor to prevent DC from flowing into the RF signal source. After the RF signal is input from the RFin terminal, it is processed by the input matching network to optimize the input characteristics of the signal. Then the signal enters the first-stage amplification unit, which is composed of three sections of transistors with gate widths of 10×80μm, 8×65μm, and 8×50μm respectively. The drain transmission line of the first stage adopts a non-uniform structure and is connected to the inter-stage matching network. The inter-stage matching network integrates the RC stabilization circuit of the second stage, the gate-level transmission line, the gate bias circuit, the drain inductance of the first stage, and one section of the LC matching network. A 50-ohm impedance line is selected to connect between the output port of the first stage and the input port of the second stage to reduce the port transmission loss and ensure the stable transmission of the signal to the second stage.

[0045] The second-stage amplification unit is composed of five sections of transistors. The first four sections are two-cell parallel transistors with single-cell gate widths of 10×110μm, 10×55μm, 8×100μm, and 8×95μm respectively. The fifth section is a single-cell transistor (8×80μm). The drain bias circuit is connected from the power supply VD2. The drain bias inductor Ld2 is placed on the chip, and the drain bias capacitor is placed outside the chip. The drain feeding position is between the third and fourth sections of transistors to reduce the voltage difference between the die cores of each section. The output matching network includes the in-chip bias inductor of the drain, the drain transmission line, and the LC structure. After the signal is processed, it is output from the RF out terminal to achieve the matching of the optimal output impedance to a 50-ohm load.

[0046] In this embodiment Figure 3 In the shown part, the function of the bias network is also reflected. The gate bias network is connected in series with a small resistor to enhance stability, ensure the stable transmission of the DC signal to the gates and drains of the transistors, and effectively prevent the RF signal from leaking to the DC power supply, providing guarantee for the stable operation of the power amplifier.

[0047] 4. Effect:

[0048] In the frequency band of 0.3 - 6.3 GHz, the power amplifier is comprehensively tested. When the drain voltage is 48V and the gate voltage is -2.6V, the saturated output power can reach 30.5W. The power fluctuation is small in the whole frequency band, and it can stably output high-power signals. The power gain is greater than 21dB, and the gain fluctuation at different frequency points is controlled within a small range, ensuring the stability of signal amplification. The power-added efficiency is greater than 30%, reaching a peak of 34% at about 2GHz, and the overall efficiency performs well, meeting the design requirements of high efficiency.

[0049] Due to the adoption of a gradient source-drain spacing structure, the breakdown voltage of the device is significantly improved, enabling it to operate stably at a high drain voltage of 48V, and the reliability is greatly enhanced. At the same time, the optimized layout and heat dissipation design effectively reduce the chip thermal resistance. Under the long-term high-power working condition, the chip temperature rises slowly, ensuring long-term reliability. In actual application scenarios, such as the radio frequency transmission module of a communication base station, this power amplifier can stably amplify signals, improving the distance and quality of signal transmission, demonstrating good performance and application value.

[0050] Embodiment 2: High-voltage high-power distributed power amplifier based on two-cell parallel structure and feed optimization:

[0051] 1. Die structure design:

[0052] Also based on the 0.25μm GaN high electron mobility transistor process, the selection of the first-stage and second-stage transistors is the same as that in Embodiment 1. The key lies in using the two-cell parallel transistor structure of the first four sections in the second stage ( Figure 2 the second-stage transistor part in ), increasing the output capacity and heat dissipation area. Each section of the two-cell transistors is connected in parallel through the source metal strip, greatly enhancing the current-carrying capacity; the drains are independently connected to the drain transmission line to ensure the independence and stability of signal transmission. Taking a single cell of 10×110μm as an example, after the two cells are connected in parallel, the output current is nearly doubled compared with the single-transistor structure, effectively enhancing the power output capacity. At the same time, the two-cell structure increases the heat dissipation area of the active region, and can dissipate heat faster during high-power operation, reducing the die temperature.

[0053] 2. Circuit design:

[0054] The design principles of the stability circuit, bias network, input matching network, and inter-stage matching network are similar to those in Embodiment 1, but the specific component parameters are optimized according to the characteristics of this embodiment.

[0055] In the output network design, the drain feed position and non-uniform structure ( Figure 2 the output matching network part in ) are further optimized. The drain feed position is precisely set between the third and fourth transistors. Through precise circuit simulation and actual debugging, the voltage difference between each die is reduced to a minimum value, effectively improving the consistency of the operation of each die. The output stage adopts a non-uniform structure. According to the output impedance of different sections of transistors, the characteristic impedance of the drain transmission line is finely designed to achieve ultra-wideband power matching. For example, for the first section of two-cell transistors with an output impedance of 12Ω, the characteristic impedance of its drain transmission line is designed to be 40Ω. Through this precise matching, the power transmission efficiency is improved.

[0056] 3. Layout design:

[0057] The layout is also arranged vertically as Figure 4 shown. The transistors in the active region adopt the source cross-gate grounded method, and the via positions are optimized to reduce the thermal resistance. In this embodiment, the layout is particularly optimized for the two-cell parallel structure and the feeding position. Since the two-cell parallel structure increases the number of die and the current density, more attention is paid to the electrical connection and heat dissipation layout between the die in the layout. The distance between the second and third transistors is increased, which is not only beneficial to heat dissipation but also reduces the electromagnetic interference between the two die. At the same time, the position and shape of the drain bias inductor are reasonably planned to ensure good electromagnetic compatibility with other components.

[0058] 4. Effects:

[0059] Testing is carried out in the frequency band of 0.3 - 6.3 GHz. When the drain voltage is 48 V and the gate voltage is -2.6 V, the saturated output power reaches 31 W, showing a certain improvement compared with Embodiment 1. The output power remains stable in the high-frequency band (such as 6 GHz), demonstrating good broadband performance. The power gain is greater than 21 dB, and the in-band gain flatness is good, which can provide a stable amplification factor for the signal. The power added efficiency is greater than 31%, reaching a peak of 35% around 3 GHz, and the overall efficiency is relatively high.

[0060] The two-cell parallel structure significantly enhances the power output ability and performs well in scenarios with high power requirements. The optimized feeding position and non-uniform output network structure improve the power matching effect, enabling the power amplifier to efficiently transmit power to the load throughout the operating frequency band. In practical applications in radar transmission systems, this power amplifier can meet the signal transmission requirements of ultra-wideband and high power, improve the detection range and accuracy of the radar, and demonstrate good application prospects. At the same time, the optimized layout further improves the heat dissipation performance and electromagnetic compatibility of the chip, ensuring the stable operation of the power amplifier in a complex electromagnetic environment.

[0061] The effects that can be achieved by the distributed structure power amplifier provided by the embodiment include:

[0062] Improve power performance: The two-stage cascaded distributed amplification structure, specific transistor selection and layout, combined with the optimized output matching network, achieve high-voltage ultra-wideband high-power output, meeting the power requirements of various application scenarios;

[0063] Enhance stability: The stable circuit design of the transistor gate, the optimized bias network, combined with the unique drain structure and reasonable feeding position, suppress self-excitation and oscillation, reduce the voltage difference, and ensure the stable operation of the circuit in a wide frequency band;

[0064] Optimize heat dissipation and reliability: The vertical layout, the source cross-gate grounded method, and thermal stability designs such as increasing the distance between transistors in the high-heat area reduce the thermal resistance, improve the heat dissipation ability, and enhance the long-term reliability of the chip.

[0065] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in the relevant field. And the changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A high-voltage high-power distributed power amplifier, characterized in that It includes a two-stage cascaded distributed amplification structure, based on the 0.25μm GaN high electron mobility transistor process, with a working frequency of 0.3 - 6.3 GHz; the first stage uses three transistors, and the gate widths are distributed as 10×80μm, 8×65μm, and 8×50μm; the second stage uses five transistors, and the first four stages are each two-cell parallel transistors, with the single-cell gate widths being 10×110μm, 10×55μm, 8×100μm, and 8×95μm respectively, and the fifth stage is a single-cell transistor with a gate width of 8×80μm; The drain of the transistor adopts a gradient source-drain spacing structure, where the source-drain spacing decreases from the middle to both ends, the minimum spacing increases by 0.4μm, and the first four stages of the second stage increase the output capacity and heat dissipation area through two-cell parallel connection; The bias network, inter-stage matching network, and output matching network are integrated into the distributed amplification structure; The second stage serves as the output stage, and its structure includes a non-uniform transistor arrangement and a drain feeding design; The output matching network includes an in-die drain bias inductor, a drain transmission line, and an LC structure to achieve the matching of the optimal output impedance to a 50-ohm load.

2. The high-voltage high-power distributed power amplifier according to claim 1, characterized in that, In the drain structure of the transistor, the spacing between the source strip and the drain strip shows a gradient distribution, satisfying d1 > d2 > d3, and d1 - d = 0.8μm, d2 - d = 0.4μm, d3 = d, where d1 is the spacing between the source strip and the drain strip at the middle position in the drain structure of the transistor, d2 is the spacing between the source strip and the drain strip in the area close to the middle, d3 is the spacing between the source strip and the drain strip at both ends, and d is the minimum source-drain spacing. By increasing the source-drain spacing, the breakdown voltage of the device is increased by more than 80V to adapt to a 48V drain voltage.

3. A high-voltage high-power distributed power amplifier according to claim 1, characterized in that, A capacitor is connected in series with the transistor gate and a resistor in parallel to form a stable circuit. The capacitor is used to reduce the input capacitance and increase the cut-off frequency, and the resistor is used to suppress the low-frequency gain and enhance the circuit stability to prevent low-frequency self-oscillation.

4. A high-voltage high-power distributed power amplifier according to claim 1, characterized in that The bias network includes in-die drain and gate bias inductors. The drain bias capacitor is placed outside the die, and the gate bias capacitor is placed inside the die; A resistor is connected in series with the gate bias network to eliminate gate oscillation and enhance stability.

5. A high-voltage high-power distributed power amplifier according to claim 1, characterized in that The inter-stage matching network includes a non-uniform drain transmission line of the first stage, a gate transmission line of the second stage, an RC stable circuit, and a 50-ohm impedance connection line; the input matching network includes an RC stable circuit, a gate transmission line, a gate bias circuit, and a parallel capacitor matching stub. A DC blocking capacitor is connected in series at the input end to prevent DC from flowing into the RF signal source.

6. A high-voltage high-power distributed power amplifier according to claim 1, characterized in that, The second-stage output stage adopts a non-uniform structure, where the output impedances of each transistor are different, and the characteristic impedance of the drain transmission line is designed according to the die size; the drain feeding position is set between the third and fourth transistors to reduce the voltage difference between the die cores of each stage; at the output end, impedance transformation is jointly achieved with the drain bias inductor and the microstrip line through a parallel matching capacitor and a series DC blocking capacitor.

7. A high-voltage high-power distributed power amplifier according to claim 1, characterized in that The layout adopts a vertical layout. The transistors in the active area adopt the source-over-gate grounding method, and the vias are far from the gate strips to reduce the thermal resistance; the distance between the second and third transistors with the largest over-current in the second stage is increased, and enough layout area is reserved for the drain bias inductor to optimize the thermal stability.

8. A design method of a high-voltage high-power distributed power amplifier according to any one of claims 1-7, characterized in that, It includes the following steps: (1)Die selection: According to the gain and power requirements, determine the gate width distribution of the three-stage transistors in the first stage and the five-stage transistors in the second stage. The first four stages of the second stage adopt a two-cell parallel structure; (2)Stable circuit design: Connect a capacitor in series with the gate and a resistor in parallel to increase the cut-off frequency and suppress low-frequency self-oscillation; (3)Bias network design: Use on-chip bias inductors, place the drain bias capacitor outside the chip and the gate bias capacitor inside the chip, and add a series resistor to the gate to enhance stability; (4)Matching network design: The input and inter-stage matching adopt non-uniform transmission lines, 50-ohm impedance lines and LC structures. The output matching is achieved through non-uniform drain transmission lines, optimized feeding positions and LC networks to achieve broadband matching; (5)Layout: Arrange vertically, increase the distance between transistors in the high-heat area, connect the source across the gate to the ground and optimize the via positions to reduce the thermal resistance.

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