Rail-to-rail operational amplifier with high open-loop gain

Abstract

The invention discloses a rail-to-rail operational amplifier with high open-loop gain. The rail-to-rail operational amplifier comprises a biasing circuit, an input stage circuit and an output stage circuit, nMOS and PMOS input geminate transistors are adopted in the input stage circuit to realize rail-to-rail input; and a Gain-boost circuit and a class AB circuit are adopted in the output stage circuit to realize high open-loop gain and rail-to-rail output.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a rail-to-rail operational amplifier with high open-loop gain. Background Art

[0002] Integrated circuits have been developing towards low voltage and low power consumption. With the progress of the process technology, the power supply voltage has gradually decreased, while the characteristics of integrated circuit devices have not changed significantly. Therefore, for operational amplifier circuits, the common-mode input and output ranges are becoming narrower and narrower, which poses challenges to achieving high open-loop gain and rail-to-rail characteristics.

[0003] In existing operational amplifiers, while achieving rail-to-rail input, there is generally no additional gain improvement technology in the output circuit, resulting in a low open-loop gain and large signal errors during application. Summary of the Invention

[0004] To solve the defects of the prior art, the present invention provides a rail-to-rail operational amplifier with high open-loop gain, including a bias circuit, an input stage circuit, and an output stage circuit; NMOS and PMOS input pair transistors are used in the input stage circuit to achieve rail-to-rail input; a Gain-boost circuit and a class AB circuit are used in the output stage circuit to achieve high open-loop gain and rail-to-rail output.

[0005] The specific content of the present invention is described in detail in the detailed implementation manner.

[0006] Reference Figure 2 , there are two input reference voltage signals HV and LV in the bias circuit, which further generate bias voltages B0, B1, B2, B3, and B4 for providing bias to the input stage circuit and the output stage circuit; the bias circuit adopts a structure of multiple current mirrors.

[0007] Reference Figure 3 , NMOS and PMOS input pair transistors are adopted in the input stage circuit to achieve rail-to-rail input; M205 and M208 are NMOS, which can achieve the input voltage to the positive rail; M206 and M207 are PMOS, which can achieve the input voltage to the positive rail.

[0008] Reference Figure 4, a Gain-boost circuit is adopted in the output stage circuit to increase the open-loop gain; the Gain-boost circuit composed of M310, M311, M312, and M313 is used to increase the open-loop gain of the NMOS input pair transistor side; the Gain-boost circuit composed of M314, M315, M316, M317, M318, M319, M320, and M321 is used to increase the open-loop gain of the PMOS input pair transistor side; M325, M327, and M332 assist in realizing the Class AB output on the PMOS side; M328, M329, and M334 assist in realizing the Class AB output on the NMOS side, thereby realizing the rail-to-rail output function.

[0009] The advantages and beneficial effects of the present invention are as follows: providing a rail-to-rail operational amplifier with a high open-loop gain, while realizing rail-to-rail input, circuits for increasing the open-loop gain are added respectively for two types of input MOS pair transistors, and Class AB circuits are also added respectively on the output side to realize rail-to-rail output.

[0010] The present invention also has the following characteristics: 1. The core circuit of the operational amplifier of the present invention is designed using a low-voltage and low-power CMOS process instead of the traditional BJT process.

[0011] 2. The present invention uses the method of input NMOS and PMOS pair transistors in combination with the Gain-boost circuit and the Class AB circuit to realize the rail-to-rail input and output function with a high open-loop gain.

[0012] 3. The input HV and LV of the bias circuit of the present invention can be adjusted according to different selected processes to adapt to the voltage value suitable for the process. Brief Description of the Drawings

[0013] Figure 1 is a schematic diagram of the rail-to-rail operational amplifier of the present invention; Figure 2 is a schematic diagram of the bias circuit; Figure 3 is a schematic diagram of the input stage circuit; Figure 4 is a schematic diagram of the output stage circuit. Detailed Embodiments

[0014] The following combines the drawings and embodiments to further describe the detailed embodiments of the present invention. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and cannot be used to limit the protection scope of the present invention.

[0015] The technical solutions of the specific implementation of the present invention are as follows: Refer to Figures 1 to 4, the present invention provides a rail-to-rail operational amplifier with high open-loop gain, comprising a bias circuit, an input stage circuit, and an output stage circuit; Reference Figure 2, the bias circuit includes: PMOS transistors M101, M102, M103, M104, M105, M107, M108, M109, M110, M113, M115, M116, M117, M119 and M120, NMOS transistors M106, M111, M112, M114, M118, M121, M122, M123, M124, M125 and M126, resistors R101, R102, R103, R104, R105, R106, R107, R108, R109 and R110, reference voltage terminals HV and LV, and bias voltage terminals B0, B1, B2, B3 and B4; the gate of PMOS transistor M101 is electrically connected to the drain of PMOS transistor M101, the gate of PMOS transistor M102, and the source of PMOS transistor M103. The source of PMOS transistor M101 is electrically connected to one end of resistor R102, the source of PMOS transistor M107, the source of PMOS transistor M109, the source of PMOS transistor M115, the source of PMOS transistor M119, and power supply VDD. The source of PMOS transistor M102 is electrically connected to the other end of resistor R102 and the source of PMOS transistor M104. The drain of PMOS transistor M102 is electrically connected to one end of resistor R105, the drain of PMOS transistor M104, the source of PMOS transistor M105, the gate of NMOS transistor M111, the gate of NMOS transistor M112, the source of PMOS transistor M113, the gate of NMOS transistor M121, the gate of NMOS transistor M123, the gate of NMOS transistor M125, and reference voltage input terminal LV. The gate of PMOS transistor M103 is electrically connected to the drain of PMOS transistor M103 and reference voltage input terminal HV. The drain of PMOS transistor M103 is also grounded through resistor R101. The gate of PMOS transistor M104 is electrically connected to the drain of PMOS transistor M108 and the drain of NMOS transistor M111. The gate of PMOS transistor M105 is electrically connected to the gate of NMOS transistor M106, the gate of PMOS transistor M113, the drain of PMOS transistor M113, the gate of NMOS transistor M114, the drain of NMOS transistor M114, the gate of PMOS transistor M117, the gate of NMOS transistor M118, the gate of NMOS transistor M122, the gate of NMOS transistor M124, and the gate of NMOS transistor M126. The drain of PMOS transistor M105 is electrically connected to the drain of NMOS transistor M106 and the source of NMOS transistor M111. The source of NMOS transistor M106 is grounded through resistor R103. The gate of PMOS transistor M107 is electrically connected to one end of resistor R104, the gate of PMOS transistor M109, the drain of PMOS transistor M110, the gate of PMOS transistor M115, and the gate of PMOS transistor M119. The drain of PMOS transistor M107 is electrically connected to the source of PMOS transistor M108,The gate of PMOS transistor M108 is electrically connected to the other end of resistor R104, the gate of PMOS transistor M110, the drain of NMOS transistor M112, the gate of PMOS transistor M116, and the gate of PMOS transistor M120. The drain of PMOS transistor M109 is electrically connected to the source of PMOS transistor M110. The source of NMOS transistor M112 is electrically connected to the drain of PMOS transistor M117 and the drain of NMOS transistor M118. The source of NMOS transistor M114 is grounded through resistor R106. The drain of PMOS transistor M115 is electrically connected to the source of PMOS transistor M116. The drain of PMOS transistor M116 is electrically connected to bias voltage terminal B2. The source of PMOS transistor M117 is electrically connected to the other end of resistor R105. The source of NMOS transistor M118 is grounded through resistor R107. The drain of PMOS transistor M119 is electrically connected to the source of PMOS transistor M120. The drain of PMOS transistor M120 is electrically connected to bias voltage terminal B1. The source of NMOS transistor M121 is electrically connected to the drain of NMOS transistor M122. The drain of NMOS transistor M121 is electrically connected to bias voltage terminal B3. The source of NMOS transistor M122 is grounded through resistor R108. The source of NMOS transistor M123 is electrically connected to the drain of NMOS transistor M124. The drain of NMOS transistor M123 is electrically connected to bias voltage terminal B4. The source of NMOS transistor M124 is grounded through resistor R109. The source of NMOS transistor M125 is electrically connected to the drain of NMOS transistor M126. The drain of NMOS transistor M125 is electrically connected to bias voltage terminal B0. The source of NMOS transistor M126 is grounded through resistor R110; Reference Figure 2 , There are two input reference voltage signals HV and LV in the bias circuit, which further generate bias voltages B0, B1, B2, B3, and B4 for the input stage circuit and the output stage circuit; The bias circuit adopts the architecture of multiple current mirrors; Reference Figure 3, the input stage circuit includes: PMOS transistors M201, M202, M203, M204, M206, M207, M211, NMOS transistors M205, M208, M209, M210, resistor R201, the input terminals INN and INP of a rail-to-rail operational amplifier, bias voltage terminal B0, and signal terminals NN, NP, PN, and PP; the gate of PMOS transistor M201 is electrically connected to the drain of PMOS transistor M202 and the gate of PMOS transistor M203, the source of PMOS transistor M201 is electrically connected to the source of PMOS transistor M203 and power supply VDD, the drain of PMOS transistor M201 is electrically connected to the source of PMOS transistor M202, the gate of PMOS transistor M202 is electrically connected to the gate of PMOS transistor M204, the gate of PMOS transistor M211, and bias voltage terminal B0, the drain of PMOS transistor M202 is also electrically connected to bias voltage terminal B0 through resistor R201, the drain of PMOS transistor M203 is electrically connected to the source of PMOS transistor M204, the drain of PMOS transistor M204 is electrically connected to the source of PMOS transistor M206, the source of PMOS transistor M207, and the source of PMOS transistor M211, the gate of NMOS transistor M205 is electrically connected to the gate of PMOS transistor M206 and the input terminal INN of the rail-to-rail operational amplifier, the source of NMOS transistor M205 is electrically connected to the source of NMOS transistor M208 and the drain of NMOS transistor M209, the drain of NMOS transistor M205 is electrically connected to signal terminal NP, the drain of PMOS transistor M206 is electrically connected to signal terminal PP, the gate of PMOS transistor M207 is electrically connected to the gate of NMOS transistor M208 and the input terminal INP of the rail-to-rail operational amplifier, the drain of PMOS transistor M207 is electrically connected to signal terminal PN, the drain of NMOS transistor M208 is electrically connected to signal terminal NN, the gate of NMOS transistor M209 is electrically connected to the gate G of NMOS transistor M210, the drain of NMOS transistor M210, and the drain of PMOS transistor M211, the source of NMOS transistor M209 and the source of NMOS transistor M210 are both grounded; Reference Figure 3 , in the input stage circuit, NMOS and PMOS input pair transistors are adopted to achieve rail-to-rail input; M205 and M208 are NMOS, which can achieve input voltage to the positive rail; M206 and M207 are PMOS, which can achieve input voltage to the positive rail; Reference Figure 4, the output stage circuit includes: PMOS transistors M302, M303, M306, M307, M310, M311, M314, M315, M316, M317, M322, M323, M324, M325, M326, M327, M332 and M333, NMOS transistors M301, M304, M305, M308, M309, M312, M313, M318, M319, M320, M321, M328, M329, M330, M331, M334 and M335, resistor R301, capacitors C301 and C302, reference voltage terminals HV and LV, bias voltage terminals B1, B2, B3 and B4, signal terminals NN, NP, PN and PP, and the output terminal VOUT of a rail-to-rail operational amplifier; the gate of NMOS transistor M301 is electrically connected to the gate of NMOS transistor M308, the drain of PMOS transistor M316, and the drain of NMOS transistor M318, the source of NMOS transistor M301 is electrically connected to the gate of PMOS transistor M302 and bias voltage terminal B4, the drain of NMOS transistor M301 is electrically connected to the gates of PMOS transistors M322, M323, the drain of PMOS transistor M323, and the gate of PMOS transistor M325, the source of PMOS transistor M302 is electrically connected to the sources of PMOS transistors M303 and B2, the drain of PMOS transistor M302 is electrically connected to the drain of NMOS transistor M304, the gate of NMOS transistor M309, and the gate of NMOS transistor M331, the gate of PMOS transistor M303 is electrically connected to the source of NMOS transistor M308, the drain of NMOS transistor M309, the gate of PMOS transistor M314, the gate of PMOS transistor M316, and signal terminal PN, the drain of PMOS transistor M303 is electrically connected to the gates of NMOS transistors M304, M305, and the drain of NMOS transistor M305, the sources of NMOS transistors M304, M305, M309, M320, M321, M330, M331, and M335 are all grounded, the gate of PMOS transistor M306 is electrically connected to the drain of PMOS transistor M307, the drain of NMOS transistor M308, and the gate of PMOS transistor M324, the source of PMOS transistor M306 is electrically connected to the sources of PMOS transistors M310, M311, M322, M323, M324, M333, and power supply VDD, the drain of PMOS transistor M306 is electrically connected to the source of PMOS transistor M307, the gate of NMOS transistor M312, and signal terminal PP,The gate of PMOS transistor M307 is electrically connected to the drain of PMOS transistor M310 and the drain of NMOS transistor M312. The gate of PMOS transistor M310 is electrically connected to the gate of PMOS transistor M311, the drain of PMOS transistor M311, and the drain of NMOS transistor M313. The source of NMOS transistor M312 is electrically connected to the source of NMOS transistor M313 and bias voltage terminal B3. The gate of NMOS transistor M313 is electrically connected to the drain of PMOS transistor M324, the source of PMOS transistor M325, the source of PMOS transistor M332, and signal terminal NP. The source of PMOS transistor M314 is electrically connected to the source of PMOS transistor M315 and bias voltage terminal B1. The drain of PMOS transistor M314 is electrically connected to the source of PMOS transistor M316. The gate of PMOS transistor M315 is electrically connected to the gate of PMOS transistor M317, the source of NMOS transistor M329, the drain of NMOS transistor M331, the source of NMOS transistor M334, one end of capacitor C302, and signal terminal NN. The drain of PMOS transistor M315 is electrically connected to the source of PMOS transistor M317. The drain of PMOS transistor M317 is electrically connected to the gate of NMOS transistor M318, the gate of NMOS transistor M319, the drain of NMOS transistor M319, the gate of NMOS transistor M320, and the gate of NMOS transistor M321. The source of NMOS transistor M318 is electrically connected to the drain of NMOS transistor M320. The source of NMOS transistor M319 is electrically connected to the drain of NMOS transistor M321. The drain of PMOS transistor M322 is electrically connected to the source of PMOS transistor M326. The drain of PMOS transistor M325 is electrically connected to the source of PMOS transistor M327. The gate of PMOS transistor M326 is electrically connected to the gate of PMOS transistor M327 and reference voltage terminal HV. The drain of PMOS transistor M326 is electrically connected to the gate of NMOS transistor M329, the gate of NMOS transistor M330, and the drain of NMOS transistor M330. The drain of PMOS transistor M327 is electrically connected to the gate of NMOS transistor M334, the drain of NMOS transistor M334, and the gate of NMOS transistor M335. The gate of NMOS transistor M328 is electrically connected to reference voltage terminal LV. The source of NMOS transistor M328 is electrically connected to the drain of NMOS transistor M329. The drain of NMOS transistor M328 is electrically connected to the gate of PMOS transistor M332, the drain of PMOS transistor M332, the gate of PMOS transistor M333, and one end of capacitor C301. The drain of PMOS transistor M333 is electrically connected to one end of resistor R301, the drain of NMOS transistor M335, and the output terminal VOUT of the rail-to-rail operational amplifier. The other end of resistor R301 is electrically connected to the other end of capacitor C301 and the other end of capacitor C302; Reference Figure 4, a Gain-boost circuit is adopted in the output stage circuit to increase the open-loop gain; the Gain-boost circuit composed of M310, M311, M312, and M313 is used to increase the open-loop gain of the NMOS input pair transistor side; the Gain-boost circuit composed of M314, M315, M316, M317, M318, M319, M320, and M321 is used to increase the open-loop gain of the PMOS input pair transistor side; M325, M327, and M332 assist in realizing the Class AB output on the PMOS side; M328, M329, and M334 assist in realizing the Class AB output on the NMOS side, thereby realizing the rail-to-rail output function.

[0016] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A rail-to-rail operational amplifier with high open-loop gain, comprising a bias circuit, an input stage circuit and an output stage circuit; characterized in that: In the input stage circuit, NMOS and PMOS input pair transistors are used to achieve rail-to-rail input; in the output stage circuit, a Gain-boost circuit and a class AB circuit are used to achieve high open-loop gain and rail-to-rail output.

2. The rail-to-rail operational amplifier with high open-loop gain according to claim 1, characterized in that, The bias circuit includes: PMOS transistors M101, M102, M103, M104, M105, M107, M108, M109, M110, M113, M115, M116, M117, M119, and M120, NMOS transistors M106, M111, M112, M114, M118, M121, M122, M123, M124, M125, and M126, resistors R101, R102, R103, R104, R105, R106, R107, R108, R109, and R110, a reference voltage terminal HV and LV, and bias voltage terminals B0, B1, B2, B3, and B4; the gate of PMOS transistor M101 is electrically connected to the drain of PMOS transistor M101, the gate of PMOS transistor M102, and the source of PMOS transistor M103. The source of PMOS transistor M101 is electrically connected to one end of resistor R102, the source of PMOS transistor M107, the source of PMOS transistor M109, the source of PMOS transistor M115, the source of PMOS transistor M119, and the power supply VDD. The source of PMOS transistor M102 is electrically connected to the other end of resistor R102 and the source of PMOS transistor M104. The drain of PMOS transistor M102 is electrically connected to one end of resistor R105, the drain of PMOS transistor M104, the source of PMOS transistor M105, the gate of NMOS transistor M111, the gate of NMOS transistor M112, the source of PMOS transistor M113, the gate of NMOS transistor M121, the gate of NMOS transistor M123, the gate of NMOS transistor M125, and the reference voltage input terminal LV. The gate of PMOS transistor M103 is electrically connected to the drain of PMOS transistor M103 and the reference voltage input terminal HV. The drain of PMOS transistor M103 is also grounded through resistor R101. The gate of PMOS transistor M104 is electrically connected to the drain of PMOS transistor M108 and the drain of NMOS transistor M111. The gate of PMOS transistor M105 is electrically connected to the gate of NMOS transistor M106, the gate of PMOS transistor M113, the drain of PMOS transistor M113, the gate of NMOS transistor M114, the drain of NMOS transistor M114, the gate of PMOS transistor M117, the gate of NMOS transistor M118, the gate of NMOS transistor M122, the gate of NMOS transistor M124, and the gate of NMOS transistor M126. The drain of PMOS transistor M105 is electrically connected to the drain of NMOS transistor M106 and the source of NMOS transistor M111. The source of NMOS transistor M106 is grounded through resistor R103. The gate of PMOS transistor M107 is electrically connected to one end of resistor R104, the gate of PMOS transistor M109, the drain of PMOS transistor M110, the gate of PMOS transistor M115, and the gate of PMOS transistor M119. The drain of PMOS transistor M107 is electrically connected to the source of PMOS transistor M108.The gate of PMOS transistor M108 is electrically connected to the other end of resistor R104, the gate of PMOS transistor M110, the drain of NMOS transistor M112, the gate of PMOS transistor M116, and the gate of PMOS transistor M120. The drain of PMOS transistor M109 is electrically connected to the source of PMOS transistor M110. The source of NMOS transistor M112 is electrically connected to the drain of PMOS transistor M117 and the drain of NMOS transistor M118. The source of NMOS transistor M114 is grounded through resistor R106. The drain of PMOS transistor M115 is electrically connected to the source of PMOS transistor M116. The drain of PMOS transistor M116 is electrically connected to bias voltage terminal B2. The source of PMOS transistor M117 is electrically connected to the other end of resistor R105. The source of NMOS transistor M118 is grounded through resistor R107. The drain of PMOS transistor M119 is electrically connected to the source of PMOS transistor M120. The drain of PMOS transistor M120 is electrically connected to bias voltage terminal B1. The source of NMOS transistor M121 is electrically connected to the drain of NMOS transistor M122. The drain of NMOS transistor M121 is electrically connected to bias voltage terminal B3. The source of NMOS transistor M122 is grounded through resistor R108. The source of NMOS transistor M123 is electrically connected to the drain of NMOS transistor M124. The drain of NMOS transistor M123 is electrically connected to bias voltage terminal B4. The source of NMOS transistor M124 is grounded through resistor R109. The source of NMOS transistor M125 is electrically connected to the drain of NMOS transistor M126. The drain of NMOS transistor M125 is electrically connected to bias voltage terminal B0. The source of NMOS transistor M126 is grounded through resistor R110., 3. The rail-to-rail operational amplifier with high open-loop gain according to claim 2, wherein There are two input reference voltage signals HV and LV in the bias circuit, which further generate bias voltages B0, B1, B2, B3, and B4 for the input stage circuit and the output stage circuit; the bias circuit adopts the architecture of multiple current mirrors.

4. The rail-to-rail operational amplifier with high open-loop gain according to claim 2, wherein The input stage circuit includes: PMOS transistors M201, M202, M203, M204, M206, M207, M211, NMOS transistors M205, M208, M209, M210, resistor R201, the input terminals INN and INP of the rail-to-rail operational amplifier, the bias voltage terminal B0, and the signal terminals NN, NP, PN, and PP; the gate of PMOS transistor M201 is electrically connected to the drain of PMOS transistor M202 and the gate of PMOS transistor M203, the source of PMOS transistor M201 is electrically connected to the source of PMOS transistor M203 and the power supply VDD, the drain of PMOS transistor M201 is electrically connected to the source of PMOS transistor M202, the gate of PMOS transistor M202 is electrically connected to the gate of PMOS transistor M204, the gate of PMOS transistor M211, and the bias voltage terminal B0, the drain of PMOS transistor M202 is also electrically connected to the bias voltage terminal B0 through resistor R201, the drain of PMOS transistor M203 is electrically connected to the source of PMOS transistor M204, the drain of PMOS transistor M204 is electrically connected to the source of PMOS transistor M206, the source of PMOS transistor M207, and the source of PMOS transistor M211, the gate of NMOS transistor M205 is electrically connected to the gate of PMOS transistor M206 and the input terminal INN of the rail-to-rail operational amplifier, the source of NMOS transistor M205 is electrically connected to the source of NMOS transistor M208 and the drain of NMOS transistor M209, the drain of NMOS transistor M205 is electrically connected to the signal terminal NP, the drain of PMOS transistor M206 is electrically connected to the signal terminal PP, the gate of PMOS transistor M207 is electrically connected to the gate of NMOS transistor M208 and the input terminal INP of the rail-to-rail operational amplifier, the drain of PMOS transistor M207 is electrically connected to the signal terminal PN, the drain of NMOS transistor M208 is electrically connected to the signal terminal NN, the gate of NMOS transistor M209 is electrically connected to the gate G of NMOS transistor M210, the drain of NMOS transistor M210, and the drain of PMOS transistor M211, the source of NMOS transistor M209 and the source of NMOS transistor M210 are both grounded.

5. The rail-to-rail operational amplifier with high open-loop gain according to claim 4, wherein In the input stage circuit, NMOS and PMOS input pair transistors are adopted to achieve rail-to-rail input; M205 and M208 are NMOS, which can achieve the input voltage to the positive rail; M206 and M207 are PMOS, which can achieve the input voltage to the positive rail.

6. The rail-to-rail operational amplifier with high open-loop gain according to claim 4, wherein The output stage circuit includes: PMOS transistors M302, M303, M306, M307, M310, M311, M314, M315, M316, M317, M322, M323, M324, M325, M326, M327, M332 and M333, NMOS transistors M301, M304, M305, M308, M309, M312, M313, M318, M319, M320, M321, M328, M329, M330, M331, M334 and M335, resistor R301, capacitors C301 and C302, reference voltage terminals HV and LV, bias voltage terminals B1, B2, B3 and B4, signal terminals NN, NP, PN and PP, and the output terminal VOUT of a rail-to-rail operational amplifier; the gate of NMOS transistor M301 is electrically connected to the gate of NMOS transistor M308, the drain of PMOS transistor M316, and the drain of NMOS transistor M318, the source of NMOS transistor M301 is electrically connected to the gate of PMOS transistor M302 and bias voltage terminal B4, the drain of NMOS transistor M301 is electrically connected to the gates of PMOS transistors M322, M323, the drain of PMOS transistor M323, and the gate of PMOS transistor M325, the source of PMOS transistor M302 is electrically connected to the sources of PMOS transistors M303 and B2, the drain of PMOS transistor M302 is electrically connected to the drain of NMOS transistor M304, the gate of NMOS transistor M309, and the gate of NMOS transistor M331, the gate of PMOS transistor M303 is electrically connected to the source of NMOS transistor M308, the drain of NMOS transistor M309, the gate of PMOS transistor M314, the gate of PMOS transistor M316, and signal terminal PN, the drain of PMOS transistor M303 is electrically connected to the gates of NMOS transistors M304, M305, and the drain of NMOS transistor M305, the sources of NMOS transistors M304, M305, M309, M320, M321, M330, M331, and M335 are all grounded, the gate of PMOS transistor M306 is electrically connected to the drain of PMOS transistor M307, the drain of NMOS transistor M308, and the gate of PMOS transistor M324, the source of PMOS transistor M306 is electrically connected to the sources of PMOS transistors M310, M311, M322, M323, M324, M333, and power supply VDD, the drain of PMOS transistor M306 is electrically connected to the source of PMOS transistor M307, the gate of NMOS transistor M312, and signal terminal PP,The gate of PMOS transistor M307 is electrically connected to the drain of PMOS transistor M310 and the drain of NMOS transistor M312. The gate of PMOS transistor M310 is electrically connected to the gate of PMOS transistor M311, the drain of PMOS transistor M311, and the drain of NMOS transistor M313. The source of NMOS transistor M312 is electrically connected to the source of NMOS transistor M313 and bias voltage terminal B3. The gate of NMOS transistor M313 is electrically connected to the drain of PMOS transistor M324, the source of PMOS transistor M325, the source of PMOS transistor M332, and signal terminal NP. The source of PMOS transistor M314 is electrically connected to the source of PMOS transistor M315 and bias voltage terminal B1. The drain of PMOS transistor M314 is electrically connected to the source of PMOS transistor M316. The gate of PMOS transistor M315 is electrically connected to the gate of PMOS transistor M317, the source of NMOS transistor M329, the drain of NMOS transistor M331, the source of NMOS transistor M334, one end of capacitor C302, and signal terminal NN. The drain of PMOS transistor M315 is electrically connected to the source of PMOS transistor M317. The drain of PMOS transistor M317 is electrically connected to the gate of NMOS transistor M318, the gate of NMOS transistor M319, the drain of NMOS transistor M319, the gate of NMOS transistor M320, and the gate of NMOS transistor M321. The source of NMOS transistor M318 is electrically connected to the drain of NMOS transistor M320. The source of NMOS transistor M319 is electrically connected to the drain of NMOS transistor M321. The drain of PMOS transistor M322 is electrically connected to the source of PMOS transistor M326. The drain of PMOS transistor M325 is electrically connected to the source of PMOS transistor M327. The gate of PMOS transistor M326 is electrically connected to the gate of PMOS transistor M327 and reference voltage terminal HV. The drain of PMOS transistor M326 is electrically connected to the gate of NMOS transistor M329, the gate of NMOS transistor M330, and the drain of NMOS transistor M330. The drain of PMOS transistor M327 is electrically connected to the gate of NMOS transistor M334, the drain of NMOS transistor M334, and the gate of NMOS transistor M335. The gate of NMOS transistor M328 is electrically connected to reference voltage terminal LV. The source of NMOS transistor M328 is electrically connected to the drain of NMOS transistor M329. The drain of NMOS transistor M328 is electrically connected to the gate of PMOS transistor M332, the drain of PMOS transistor M332, the gate of PMOS transistor M333, and one end of capacitor C301. The drain of PMOS transistor M333 is electrically connected to one end of resistor R301, the drain of NMOS transistor M335, and the output terminal VOUT of the rail-to-rail operational amplifier. The other end of resistor R301 is electrically connected to the other end of capacitor C301 and the other end of capacitor C302., 7. The rail-to-rail operational amplifier with high open-loop gain according to claim 6, wherein A Gain-boost circuit is adopted in the output stage circuit to increase the open-loop gain. The Gain-boost circuit composed of M310, M311, M312, and M313 is used to increase the open-loop gain of the NMOS input pair transistor side. The Gain-boost circuit composed of M314, M315, M316, M317, M318, M319, M320, and M321 is used to increase the open-loop gain of the PMOS input pair transistor side. M325, M327, and M332 assist in realizing the Class AB output on the PMOS side. M328, M329, and M334 assist in realizing the Class AB output on the NMOS side, thereby realizing the rail-to-rail output function.

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