Multi-phase clock circuit and multi-phase clock signal generation method

Abstract

The invention provides a multi-phase clock circuit and a multi-phase clock signal generation method, which are applied to the technical field of integrated circuits, and the multi-phase clock circuit comprises: an injection switch control module configured to obtain an injection mode control signal representing a frequency injection ratio; the injection switch selection module is configured to determine an injection phase of the four-phase injection clock signal according to the injection mode control signal; the buffer is configured to input a four-phase injection clock signal into the ring oscillator according to an injection phase; the ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into the phase discriminator; the phase discriminator is configured to extract phase deviation information from the N phase clock signals; the frequency matching control module is configured to tune the ring oscillator according to the frequency and phase deviation information of the injection mode control signal and the four-phase injection clock signal. According to the embodiment of the invention, the frequency range of the clock signal can be widened.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and particularly relates to a multi-phase clock circuit and a method for generating a multi-phase clock signal. Background Art

[0002] The injection-locked ring oscillator has the advantage of multiple phases when generating a clock signal. However, with the increase in the number of phases, the number of stages of the ring oscillator limits the clock frequency and performance, resulting in a relatively small frequency range of the clock signal generated by the ring oscillator. Summary of the Invention

[0003] The present disclosure provides a multi-phase clock circuit and a method for generating a multi-phase clock signal.

[0004] In a first aspect, an embodiment of the present disclosure provides a multi-phase clock circuit, including: an injection switch control module, an injection switch selection module, a buffer, a ring oscillator with four-phase injection and N-stage output, a phase detector, and a frequency matching control module;

[0005] The injection switch control module is configured to obtain an injection mode control signal; the injection mode control signal characterizes the frequency injection ratio of the four-phase injection clock signal;

[0006] The injection switch selection module is configured to determine the injection phase of the four-phase injection clock signal according to the injection mode control signal;

[0007] The buffer is configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase;

[0008] The ring oscillator is configured to generate N-phase clock signals based on the four-phase injection clock signal and input the N-phase clock signals into the phase detector;

[0009] The phase detector is configured to extract phase deviation information from the N-phase clock signals;

[0010] The frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal, and the phase deviation information.

[0011] In a possible implementation, the value of the injection mode control signal is a positive odd number.

[0012] In a possible implementation, the frequency matching control module is configured to:

[0013] Before the buffer inputs the four-phase injection clock signal into the ring oscillator, adjust the self-oscillation frequency of the ring oscillator to the target frequency; the target frequency = the frequency of the four-phase injection clock signal / the value of the injection mode control signal;

[0014] After the buffer inputs the four-phase injection clock signal into the ring oscillator, use negative feedback to eliminate the phase deviation information.

[0015] In a possible implementation, the phase detector is configured to:

[0016] Determine the phase detection sign bit according to the injection mode control signal;

[0017] Determine the frequency deviation according to the self-oscillation frequency of the ring oscillator, the frequency of the injection clock signal, and the injection mode control signal;

[0018] Determine the phase deviation information according to the phase detection sign bit and the frequency deviation.

[0019] In a possible implementation, the value of the injection mode control signal is 2k - 1; where k is a positive integer;

[0020] The last two bits of the binary code of k are the mode control word; the phase detection sign bit is determined according to the mode control word.

[0021] In a possible implementation, the four-phase injection clock signal includes a clock signal of the first phase, a clock signal of the second phase, a clock signal of the third phase, and a clock signal of the fourth phase; the first phase, the second phase, the third phase, and the fourth phase are differentially distributed, and the first phase and the second phase are in antiphase, and the third phase and the fourth phase are in antiphase; the injection switch selection module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch;

[0022] The first end of the first switch is used to access the clock signal of the first phase, and the second end is connected to the first injection node of the ring oscillator via a buffer;

[0023] The first end of the second switch is used to access the clock signal of the first phase, and the second end is connected to the second injection node of the ring oscillator via a buffer;

[0024] The first end of the third switch is used to access the clock signal of the second phase, and the second end is connected to the first injection node of the ring oscillator via a buffer;

[0025] The first end of the fourth switch is used to access the clock signal of the second phase, and the second end is connected to the second injection node of the ring oscillator via a buffer;

[0026] The first end of the fifth switch is used to access the clock signal of the third phase, and the second end is connected to the third injection node of the ring oscillator via a buffer;

[0027] The first end of the sixth switch is used to access the clock signal of the third phase, and the second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0028] The first end of the seventh switch is used to access the clock signal of the fourth phase, and the second end is connected to the third injection node of the ring oscillator via a buffer;

[0029] The first end of the eighth switch is used to access the clock signal of the fourth phase, and the second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0030] Wherein, the first injection node, the second injection node, the third injection node and the fourth injection node are output nodes on the ring oscillator with an interval of N / 4, and the interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node.

[0031] In a possible implementation manner, the first switch and the fourth switch are configured to be in the same state;

[0032] The second switch and the third switch are configured to be in a state opposite to that of the first switch and the fourth switch;

[0033] The fifth switch and the eighth switch are controlled by a first control signal determined according to the injection mode control signal;

[0034] The sixth switch and the seventh switch are controlled by a second control signal opposite to the first control signal.

[0035] In a possible implementation manner, the value of the injection mode control signal is 2k - 1; wherein, k is a positive integer;

[0036] The last two bits of the binary code of k are the mode control word; the first control signal and the second control signal are determined according to the second bit of the mode control word.

[0037] In a second aspect, an embodiment of the present disclosure provides a multi-phase clock signal generation method, which is applied to the multi-phase clock circuit in the first aspect. The method includes:

[0038] Obtain an injection mode control signal;

[0039] Determine the injection phase of the four-phase injection clock signal according to the injection mode control signal;

[0040] Input the four-phase injection clock signal into the ring oscillator according to the injection phase;

[0041] Generate N-phase clock signals through the ring oscillator.

[0042] In a possible implementation manner, the obtaining of the injection mode control signal includes:

[0043] Determine the injection mode control signal according to the frequency of the four-phase injection clock signal.

[0044] In a possible implementation manner, the determining of the injection mode control signal according to the frequency of the four-phase injection clock signal includes:

[0045] In response to the frequency of the four-phase injection clock signal being greater than or equal to a preset frequency threshold, determine that the mode control signal is a first value;

[0046] In response to the frequency of the four-phase injection clock signal being less than the frequency threshold, determine that the mode control signal is a second value smaller than the first value.

[0047] In the embodiments of the present disclosure, by using an injection switch control module to obtain an injection mode control signal and an injection switch selection module to determine the injection phase of the four-phase injection clock signal, the four-phase injection clock signal can switch to multiple frequency injection ratios and injection phases when injecting into the ring oscillator. By using a phase discriminator and a frequency matching control module to tune the ring oscillator, when the four-phase injection clock signal is injected into the ring oscillator according to different frequency injection ratios and injection phases, clock signals with better performance can be generated, enabling the multi-phase clock circuit to work properly at different clock frequencies, thereby greatly broadening the frequency range of the clock signals generated by the multi-phase clock circuit. Description of the Drawings

[0048] In the drawings of the embodiments of the present disclosure:

[0049] Figure 1 is a block diagram of a multi-phase clock circuit provided by an embodiment of the present disclosure;

[0050] Figure 2 is a schematic structural diagram of an injection switch selection module provided by an embodiment of the present disclosure;

[0051] Figure 3 is a schematic structural diagram of a ring oscillator provided by an embodiment of the present disclosure;

[0052] Figure 4 Schematic diagram of generation of a switching control signal provided by an embodiment of the present disclosure;

[0053] Figure 5 Schematic diagram of correspondence between a mode control word, a switching control signal, and an injection node provided by an embodiment of the present disclosure;

[0054] Figure 6 Schematic diagram of phase discrimination sign bit control provided by an embodiment of the present disclosure;

[0055] Figure 7 Schematic diagram of generation of a switching control signal provided by an embodiment of the present disclosure;

[0056] Figure 8 Schematic diagram of correspondence between a mode control word, a switching control signal, and a phase discrimination sign bit provided by an embodiment of the present disclosure;

[0057] Figure 9 Schematic diagram of operation of a frequency matching control module provided by an embodiment of the present disclosure;

[0058] Figure 10 Flowchart of a method for generating a multi-phase clock signal provided by an embodiment of the present disclosure;

[0059] Figure 11 Block diagram of another multi-phase clock circuit provided by an embodiment of the present disclosure;

[0060] Figure 12 Schematic diagram of relationship between frequency and phase of an output clock signal provided by an embodiment of the present disclosure;

[0061] Figure 13 Schematic diagram of arrangement order of output clock signals provided by an embodiment of the present disclosure;

[0062] Figure 14 Another schematic diagram of relationship between frequency and phase of an output clock signal provided by an embodiment of the present disclosure;

[0063] Figure 15 Another schematic diagram of arrangement order of output clock signals provided by an embodiment of the present disclosure;

[0064] Figure 16 Schematic diagram of relationship between an injection mode control signal, a mode control word, a control signal, and a frequency provided by an embodiment of the present disclosure;

[0065] Figure 17 Schematic diagram of effect of clock jitter of a switching injection mode control signal provided by an embodiment of the present disclosure. Detailed implementation manners

[0066] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0067] In the following, the present disclosure will be described more fully with reference to the accompanying drawings. However, the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0068] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure, and do not constitute a limitation to the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0069] The present disclosure may be described with reference to the plan views and / or cross-sectional views by means of the ideal schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to the manufacturing techniques and / or tolerances.

[0070] In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0071] The terms used in the present disclosure are only for describing specific embodiments and are not intended to limit the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. As used in the present disclosure, the terms "comprising", "made of", specify the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0072] Unless otherwise defined, all terms (including technical and scientific terms) used in the present disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless the present disclosure clearly so defines.

[0073] The present disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be restrictive.

[0074] In scenarios such as data centers, cloud computing, and fifth-generation mobile communication technology (5G) networks, with the sharp increase in data throughput, the requirements for data transmission rate are constantly rising. Multiphase sampling is the main technology to achieve high throughput of the receiver by interleaving multiple channels while maintaining the data transmission rate per channel.

[0075] Multiphase clocks play a crucial role in high-speed communication systems. The clock frequency of multiphase clocks determines the sampling rate of high-speed communication systems, and their performance such as clock jitter determines the sampling quality of high-speed communication systems. The two together determine the communication quality of high-speed communication systems. In high-speed communication systems, improving the clock frequency and performance of multiphase clocks is one of the key technologies to improve system performance and reliability.

[0076] In some related technologies, multiphase clocks can be implemented by ring oscillators. Usually, the injection locking principle is adopted to make the ring oscillator work at the required frequency. Although the multiphase clock based on the ring oscillator has multiphase advantages, however, with the increase in the number of phases, the number of stages of the ring oscillator limits its clock frequency, resulting in a narrow frequency coverage range of the clock signal generated by the ring oscillator.

[0077] In the embodiments of the present disclosure, by using an injection switch control module to obtain an injection mode control signal and an injection switch selection module to determine the injection phase of the four-phase injection clock signal, the four-phase injection clock signal can switch to various frequency injection ratios and injection phases when injecting into the ring oscillator. By using a phase detector and a frequency matching control module to tune the ring oscillator, when the four-phase injection clock signal is injected into the ring oscillator according to different frequency injection ratios and injection phases, it can generate clock signals with good performance, enabling the multiphase clock circuit to output multiphase clock signals with accurate edges at different clock frequencies, thereby greatly broadening the frequency range of the clock signals generated by the multiphase clock circuit.

[0078] In a first aspect, embodiments of the present disclosure provide a multiphase clock circuit.

[0079] Refer to Figure 1, the multi-phase clock circuit of the embodiments of the present disclosure includes an injection switch control module, an injection switch selection module, a buffer, a ring oscillator with four-phase injection and N-level output, a phase detector, and a frequency matching control module; the injection switch control module is configured to obtain an injection mode control signal; the injection mode control signal characterizes the frequency injection ratio of the four-phase injection clock signal; the injection switch selection module is configured to determine the injection phase of the four-phase injection clock signal according to the injection mode control signal; the buffer is configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase; the ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into the phase detector; the phase detector is configured to extract phase deviation information from the N phase clock signals; the frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal, and the phase deviation information.

[0080] In the embodiments of the present disclosure, the ring oscillator with four-phase injection and N-level output refers to a ring oscillator in which the injection clock signal includes clock signals of four phases and the output clock signal includes clock signals of N phases. Among them, N = 2 m , m is a positive integer, and the value of N can be 8, 16, 32, etc. In the embodiments of the present disclosure, the number of stages (i.e., the value of N) of the ring oscillator with four-phase injection and N-level output (abbreviated as the ring oscillator) is not limited.

[0081] Referring to Figure 1 , the first end of the injection switch selection module is connected to the four-phase injection clock signal, its second end is connected to the injection switch control module, and its third end is connected to the buffer.

[0082] The injection clock signal can represent the clock signal injected into the ring oscillator and is used for injection locking of the ring oscillator. In the embodiments of the present disclosure, the injection clock signal includes clock signals of four phases, so it is called the four-phase injection clock signal. In one example, the four-phase injection clock signal can be a quadrature four-phase clock signal. For example, the four-phase injection clock signal can include a clock signal with a phase of 0°, a clock signal with a phase of 180°, a clock signal with a phase of 90°, and a clock signal with a phase of 270°. The four-phase injection clock signal is injected into the ring oscillator via the injection switch selection module and the buffer.

[0083] The injection mode control signal can characterize the frequency injection ratio of the four-phase injection clock signal. In the embodiments of the present disclosure, the four-phase injection clock signal can inject its frequency into the ring oscillator according to different frequency injection ratios. For example, the four-phase injection clock signal can inject its frequency into the ring oscillator at a ratio of 1 / 3. At this time, the frequency of the clock signal injected into the ring oscillator is 1 / 3 of the frequency of the four-phase injection clock signal. In this way, when the frequency of the four-phase injection clock signal remains unchanged, the effect of injecting multiple frequencies into the ring oscillator is achieved.

[0084] The injection switch control module is configured to obtain the injection mode control signal. After obtaining the injection mode control signal, the injection switch control module can send the injection mode control signal to the injection switch selection module.

[0085] The injection switch selection module is configured to determine the injection phase of the four-phase injection clock signal according to the injection mode control signal. In the embodiments of the present disclosure, under different injection mode control signals, the frequency injection ratios of the four-phase injection clock signal are different, and the injection phases of the clock signals of the corresponding four phases can also be different. The injection switch selection module can adjust the injection phase of the four-phase injection clock signal according to the injection mode control signal, so that the frequency and phase of the four-phase injection clock signal match when it is injected into the ring oscillator, thereby improving the performance of the clock signal generated by the ring oscillator.

[0086] After receiving the four-phase injection clock signal and the injection mode control signal, the injection switch selection module can determine the injection phase of each phase clock signal of the four-phase injection clock signal according to the injection mode control signal. It should be understood that by switching the mode control signal, the injection phase of each phase clock signal can be switched.

[0087] In the embodiments of the present disclosure, the frequency injection ratio of the four-phase injection clock signal and the injection phase of each phase clock signal can be determined by the injection mode control signal, ensuring the successful injection of the four-phase injection clock signal and the stable oscillation of the ring oscillator.

[0088] After that, the injection switch selection module can send the four-phase injection clock signal and the injection phase of each phase clock signal to the buffer.

[0089] Refer to Figure 1 , one end of the buffer is connected to the injection switch selection module, and its other end is connected to the ring oscillator. The buffer can be used to enhance the clock driving ability. The buffer is configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase. The buffer can enhance the four-phase injection clock signal and inject the enhanced four-phase injection clock signal into the ring oscillator according to the injection phase of each phase clock signal.

[0090] It should be understood that the injection phases corresponding to the respective injection nodes in the ring oscillator are different. Therefore, the buffer can inject each phase clock signal of the four-phase injection clock signal into the injection node corresponding to its injection phase respectively.

[0091] Refer to Figure 1 , one end of the ring oscillator is connected to the buffer, and its other end is connected to the phase detector. The ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into the phase detector.

[0092] It should be understood that the N phase clock signals output by the ring oscillator to the phase detector are N phase clock signals with phase deviations. Based on this, the phase detector is configured to receive the N phase clock signals, extract the phase deviation information from the N phase clock signals, and input the phase deviation information into the frequency matching control module to facilitate eliminating the phase deviation.

[0093] In one example, the phase detector can select some of the N phase clock signals as the phase detection clock signals and extract the phase deviation information from the phase detection clock signals. For example, the phase detector can select the clock signal output at the injection node of the ring oscillator as the phase detection clock signal, which can improve the accuracy of the phase deviation information.

[0094] Refer to Figure 1 , one end of the frequency matching control module is connected to the phase detector, and its other end is connected to the ring oscillator.

[0095] The frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal, and the phase deviation information.

[0096] In the embodiments of the present disclosure, when the frequency matching control module tunes the ring oscillator, it first adjusts the self-oscillation frequency of the ring oscillator according to the frequency injection ratio characterized by the injection mode control signal and the frequency of the four-phase injection clock signal; then, it adjusts the phase information of the ring oscillator according to the phase deviation information, thereby completing the tuning of the ring oscillator.

[0097] In the embodiments of the present disclosure, by using an injection switch control module to obtain an injection mode control signal and an injection switch selection module to determine the injection phase of a four-phase injection clock signal, the four-phase injection clock signal can be switched to various frequency injection ratios and injection phases when injecting into a ring oscillator. By using a phase detector and a frequency matching control module to tune the ring oscillator, when the four-phase injection clock signal is injected into the ring oscillator according to different frequency injection ratios and injection phases, a clock signal with better performance can be generated, so that the multi-phase clock circuit can output multi-phase clock signals with accurate edges at different clock frequencies, thereby greatly broadening the frequency range of the clock signals generated by the multi-phase clock circuit.

[0098] In some embodiments, the value of the injection mode control signal is a positive odd number. Wherein, the injection mode control signal is represented by INJ_MODE, then INJ_MODE = 2k - 1, where k is an integer greater than 0. For example, the value of k can be 1, 2, 3, etc., and the corresponding INJ_MODE can be 1, 3, 5, etc.

[0099] The injection mode control signal characterizes the frequency injection ratio of the four-phase injection clock signal. For example, when the value of the injection mode control signal is 3, it means that 1 / 3 of the frequency of the four-phase injection clock signal is injected into the ring oscillator; when the value of the injection mode control signal is 5, it means that 1 / 5 of the frequency of the four-phase injection clock signal is injected into the ring oscillator.

[0100] As a way of the embodiments of the present disclosure, setting the value of the injection mode control signal to a positive odd number can achieve matching with the general mode set and facilitate signal control. It should be noted that in the embodiments of the present disclosure, the injection mode control signal can be used to determine the first control signal, the second control signal, etc., which will be described in detail later and will not be elaborated here.

[0101] In some embodiments, the four-phase injection clock signal includes a clock signal of the first phase, a clock signal of the second phase, a clock signal of the third phase, and a clock signal of the fourth phase; the first phase, the second phase, the third phase, and the fourth phase are differentially distributed, and the first phase and the second phase are in antiphase, and the third phase and the fourth phase are in antiphase; the injection switch selection module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch;

[0102] The first end of the first switch is used to access the clock signal of the first phase, and the second end is connected to the first injection node of the ring oscillator via a buffer;

[0103] The first end of the second switch is used to access the clock signal of the first phase, and the second end is connected to the second injection node of the ring oscillator via a buffer;

[0104] The first end of the third switch is used to access the clock signal of the second phase, and the second end is connected to the first injection node of the ring oscillator via a buffer;

[0105] The first end of the fourth switch is used to access the clock signal of the second phase, and the second end is connected to the second injection node of the ring oscillator via a buffer;

[0106] The first end of the fifth switch is used to access the clock signal of the third phase, and the second end is connected to the third injection node of the ring oscillator via a buffer;

[0107] The first end of the sixth switch is used to access the clock signal of the third phase, and the second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0108] The first end of the seventh switch is used to access the clock signal of the fourth phase, and the second end is connected to the third injection node of the ring oscillator via a buffer;

[0109] The first end of the eighth switch is used to access the clock signal of the fourth phase, and the second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0110] Wherein, the first injection node, the second injection node, the third injection node and the fourth injection node are output nodes on the ring oscillator with an interval of N / 4, and the interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node.

[0111] In the embodiments of the present disclosure, the clock signal with a phase of 0° is used as the clock signal of the first phase (denoted as CLK_0°), the clock signal with a phase of 180° is used as the clock signal of the second phase (denoted as CLK_180°), the clock signal with a phase of 90° is used as the clock signal of the third phase (denoted as CLK_90°), and the clock signal with a phase of 270° is used as the clock signal of the fourth phase (denoted as CLK_270°) for description. At this time, the first phase (0°), the second phase (180°), the third phase (90°), and the fourth phase (270°) are differentially distributed, and the first phase (0°) and the second phase (180°) are in antiphase, and the third phase (90°) and the fourth phase (270°) are in antiphase. It should be understood that the above is only an exemplary illustration of the first phase, the second phase, the third phase, and the fourth phase, and is not a limitation. For example, the first phase, the second phase, the third phase, and the fourth phase can be 45°, 225°, 135°, and 315° respectively.

[0112] In the embodiments of the present disclosure, the clock signal injected into the first injection node is denoted as CKI_A, the clock signal injected into the second injection node is denoted as CKI_B, the clock signal injected into the third injection node is denoted as CKI_C, and the clock signal injected into the fourth injection node is denoted as CKI_D for description.

[0113] Figure 2 is a schematic structural diagram of an injection switch selection module provided by the embodiments of the present disclosure. Refer to Figure 2, the first terminal of the first switch S1 is used to access the clock signal CLK_0° of the first phase, and the second terminal is connected to the first injection node of the ring oscillator via a buffer, and is used to inject (which can also be called input) the clock signal CKI_A. The first terminal of the second switch S2 is used to access the clock signal CLK_0° of the first phase, and the second terminal is connected to the second injection node of the ring oscillator via a buffer, and is used to inject the clock signal CKI_B. The first terminal of the third switch S3 is used to access the clock signal CLK_180° of the second phase, and the second terminal is connected to the first injection node of the ring oscillator via a buffer, and is used to inject the clock signal CKI_A. The first terminal of the fourth switch S4 is used to access the clock signal CLK_180° of the second phase, and the second terminal is connected to the second injection node of the ring oscillator via a buffer, and is used to inject the clock signal CKI_B. The first terminal of the fifth switch S5 is used to access the clock signal CLK_90° of the third phase, and the second terminal is connected to the third injection node of the ring oscillator via a buffer, and is used to inject the clock signal CKI_C. The first terminal of the sixth switch S6 is used to access the clock signal CLK_90° of the third phase, and the second terminal is connected to the fourth injection node of the ring oscillator via a buffer, and is used to inject the clock signal CKI_D. The first terminal of the seventh switch S7 is used to access the clock signal CLK_270° of the fourth phase, and the second terminal is connected to the third injection node of the ring oscillator via a buffer, and is used to inject the clock signal CKI_C. The first terminal of the eighth switch S8 is used to access the clock signal CLK_270° of the fourth phase, and the second terminal is connected to the fourth injection node of the ring oscillator via a buffer, and is used to inject the clock signal CKI_D.

[0114] Referring to Figure 2 , it can be known that the clock signal CLK_0° of the first phase can be used as the clock signal CKI_A or CKI_B, the clock signal CLK_180° of the second phase can be used as the clock signal CKI_A or CKI_B, the clock signal CLK_90° of the third phase can be used as the clock signal CKI_C or CKI_D, and the clock signal CLK_270° of the fourth phase can be used as the clock signal CKI_C or CKI_D.

[0115] Figure 3 is a schematic structural diagram of a ring oscillator provided by an embodiment of the present disclosure. Referring to Figure 3 , the ring oscillator with four-phase injection and N-stage output includes N inverters cascaded in a ring, that is, N inverters are connected end to end in sequence, and the output terminal of each inverter is an output node, which is used to output a clock signal generated by the ring oscillator. The N output nodes included in the ring oscillator can be represented as CKO<N - 1, 0>, and the i-th output node of the ring oscillator can be represented as , 0 ≤ i ≤ N - 1, and i is an integer.

[0116] In an embodiment of the present disclosure, the ring oscillator has four injection nodes, namely a first injection node, a second injection node, a third injection node, and a fourth injection node, and the four injection nodes are output nodes on the ring oscillator with an interval of N / 4. At the same time, the interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node. It can be seen that the third injection node is located between the first injection node and the second injection node. That is to say, the first injection node, the third injection node, the second injection node, and the fourth injection node are arranged in sequence.

[0117] Refer to Figure 3 , the first injection node into which the clock signal CKI_A is injected is the output node CKO<0> of the ring oscillator, and the second injection node into which the clock signal CKI_B is injected is the output node CKO <n 2>, the third injection node into which the clock signal CKI_C is injected is the output node CKO of the ring oscillator <n 4>The fourth injection node into which the clock signal CKI_D is injected is the output node CKO<3N / 4> of the ring oscillator. It can be seen that between the first injection node and the third injection node, between the third injection node and the second injection node, between the fourth injection node and the second injection node, and between the first injection node and the fourth injection node, there are N / 4 output nodes of the ring oscillator spaced apart. The interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node.

[0118] As a way of the embodiment of the present disclosure, by providing an injection switch selection module between the four-phase injection clock signal and the injection node, the clock signals with different phases in the four-phase injection clock signal can be input to different injection nodes through the switching switches, thereby adjusting the phases of the four-phase injection clock signal and broadening the frequency of the injection clock signal.

[0119] In some embodiments, the first switch and the fourth switch are configured to be in the same state; the second switch and the third switch are configured to be in a state opposite to the state of the first switch and the fourth switch; the fifth switch and the eighth switch are controlled by a first control signal determined according to the injection mode control signal; the sixth switch and the seventh switch are controlled by a second control signal opposite to the first control signal.

[0120] Among them, the first switch and the fourth switch being configured to be in the same state means that: both the first switch and the fourth switch are in the closed state, or both the first switch and the fourth switch are in the open state. The second switch and the third switch being configured to be in a state opposite to the state of the first switch and the fourth switch means that: when the first switch and the fourth switch are both in the closed state, the second switch and the third switch are both in the open state; when the first switch and the fourth switch are both in the open state, the second switch and the third switch are both in the closed state.

[0121] Referring to Figure 2 , the first switch S1 is configured to be closed (i.e., on), the second switch S2 is configured to be open (i.e., off), and the clock signal CLK_0° of the first phase is used as the clock signal CKI_A input to the first injection node; the third switch S3 is configured to be open, the fourth switch S4 is configured to be closed, and the clock signal CLK_180° of the second phase is used as the clock signal CKI_B input to the second injection node.

[0122] Among them, the fifth switch and the eighth switch are controlled by a first control signal. Among them, the sixth switch and the seventh switch are controlled by a second control signal. The second control signal is opposite to the first control signal. That is to say, when the first control signal controls the fifth switch and the eighth switch to be turned off, the second control signal controls the sixth switch and the seventh switch to be turned on; when the first control signal controls the fifth switch and the eighth switch to be turned on, the second control signal controls the sixth switch and the seventh switch to be turned off.

[0123] Referring to Figure 2 , the first control signal MC1 controls the fifth switch S5 and the eighth switch S8 to be turned on, and the second control signal MC2 controls the sixth switch S6 and the seventh switch S7 to be turned off. At this time, the clock signal CLK_90° of the third phase is used as the clock signal CKI_C input to the third injection node, and the clock signal CLK_270° of the fourth phase is used as the clock signal CKI_D input to the fourth injection node. Correspondingly, when the first control signal MC1 controls the fifth switch S5 and the eighth switch S8 to be turned off, the second control signal MC2 controls the sixth switch S6 and the seventh switch S7 to be turned on. At this time, the clock signal CLK_90° of the third phase is used as the clock signal CKI_D input to the fourth injection node, and the clock signal CLK_270° of the fourth phase is used as the clock signal CKI_C input to the third injection node.

[0124] Among them, the first control signal is determined according to the injection mode control signal. The second control signal is opposite to the first control signal, which is equivalent to that the second control signal is also determined according to the injection mode control signal.

[0125] As a way of the embodiment of the present disclosure, the first control signal and the second control signal are determined by the injection mode control signal, so as to control the states of the fifth switch, the sixth switch, the seventh switch and the eighth switch. Furthermore, the switching of the clock signals of the third phase and the fourth phase corresponding to the injection nodes is realized through the injection mode control signal.

[0126] In some embodiments, the value of the injection mode control signal is 2k - 1; where k is a positive integer; the last two bits of the binary code of k are the mode control word; the first control signal and the second control signal are determined according to the second bit of the mode control word.

[0127] In the embodiment of the present disclosure, the last two bits of the binary code of k can be represented by b1 and b0, the mode control word can be represented by (b1, b0), the first bit of the mode control word is b1, and the second bit is b0. The switch control signal can be represented by (MC2, MC1), where MC1 represents the first control signal and MC2 represents the second control signal.

[0128] Figure 4 A schematic diagram of the generation of a switch control signal provided by an embodiment of the present disclosure. Refer to Figure 4 , the second bit b0 of the mode control word is connected to the first control signal MC1 and the second control signal MC2. The second bit b0 of the mode control word is connected to the second control signal MC2 through an inverter, and their values are opposite; the second bit b0 of the mode control word is connected to the first control signal MC1 through two inverters, and their values are the same. Among them, when the second control signal MC2 takes the value of 1, the switches (the sixth switch and the seventh switch) connected to it are closed (i.e., on), and when the second control signal MC2 takes the value of 0, the switches connected to it are opened (i.e., off). The first control signal MC1 can refer to the second control signal MC2, which will not be elaborated here.

[0129] Figure 5 A schematic diagram of the correspondence between a mode control word, a switch control signal, and an injection node provided by an embodiment of the present disclosure.

[0130] Refer to Figure 5 , when the mode control word (b1, b0) takes the value of (x, 0), the second control signal MC2 takes the value of 1, controlling the sixth switch S6 and the seventh switch S7 to be closed; the first control signal MC1 takes the value of 0, controlling the fifth switch S5 and the eighth switch S8 to be opened; at this time, the third injection node CKI_C injects the clock signal CLK_270° of the fourth phase, and the fourth injection node CKI_D injects the clock signal CLK_90° of the third phase. It should be understood that the value of the mode control word (b1, b0) being (x, 0) means that the first bit of the mode control word can be 0 or 1, and the second bit is 0.

[0131] Refer to Figure 5 , when the mode control word (b1, b0) takes the value of (x, 1), the second control signal MC2 takes the value of 0, controlling the sixth switch S6 and the seventh switch S7 to be opened; the first control signal MC1 takes the value of 1, controlling the fifth switch S5 and the eighth switch S8 to be closed; at this time, the third injection node CKI_C injects the clock signal CLK_90° of the third phase, and the fourth injection node CKI_D injects the clock signal CLK_270° of the fourth phase. It should be understood that the value of the mode control word (b1, b0) being (x, 1) means that the first bit of the mode control word can be 0 or 1, and the second bit is 1.

[0132] As a way of an embodiment of the present disclosure, the first control signal and the second control signal are determined through the mode control word, and then the closing and opening of the switches are controlled, realizing the switching of the injection phase by injecting the mode control signal.

[0133] In some embodiments, the frequency matching control module is configured to: before the buffer inputs the four-phase injection clock signal into the ring oscillator, adjust the self-oscillation frequency of the ring oscillator to a target frequency; the target frequency = the frequency of the four-phase injection clock signal / the value of the injection mode control signal; after the buffer inputs the four-phase injection clock signal into the ring oscillator, use negative feedback to eliminate the phase deviation information.

[0134] In the embodiments of the present disclosure, the self-oscillation frequency of the ring oscillator is denoted as f osc , the target frequency is denoted as f d , the frequency of the four-phase injection clock signal is denoted as f INJ , and the injection mode control signal is denoted as INJ_MODE. Among them, f d = f INJ / INJ_MODE. In an example, INJ_MODE = 1, then f d = fI NJ ; INJ_MODE = 3, then f d = f INJ / 3; INJ_MODE = 5, then f d = f INJ / 5.

[0135] Before the buffer inputs the four-phase injection clock signal into the ring oscillator, the frequency matching control module adjusts the self-oscillation frequency f osc of the ring oscillator towards the target frequency f d .

[0136] In an example, when the self-oscillation frequency f osc of the ring oscillator is less than the target frequency f d , increase the value of f osc , and when the self-oscillation frequency f osc of the ring oscillator is greater than the target frequency f d , decrease the value of f osc until the self-oscillation frequency of the ring oscillator matches the target frequency. Among them, the adjustment step (increase step or decrease step) of the self-oscillation frequency f osc of the ring oscillator can be set as needed, and the embodiments of the present disclosure do not limit this.

[0137] In an example, when the difference between the self-oscillation frequency f osc of the ring oscillator and the target frequency f d is less than the first preset value, it can be confirmed that the self-oscillation frequency of the ring oscillator matches the target frequency. Among them, the first preset value can be set as needed, and the embodiments of the present disclosure do not limit this. In another example, when the self-oscillation frequency f osc of the ring oscillator and the target frequency f d When the difference is less than a second preset value and the number of adjustment times of the self-oscillation frequency fosc of the ring oscillator is greater than a third preset value, it can be confirmed that the self-oscillation frequency of the ring oscillator matches the target frequency. Wherein, the second preset value and the third preset value can be set as needed, and the embodiments of the present disclosure do not make limitations.

[0138] It should be noted that the above is only the adjustment method of the self-oscillation frequency f of the ring oscillator osc and the confirmation method of the self-oscillation frequency f of the ring oscillator osc matching the target frequency f d This is an exemplary description, and it does not limit the embodiments of the present disclosure. Other methods in related technologies can also be used to adjust the self-oscillation frequency fosc of the ring oscillator and confirm the matching of the self-oscillation frequency of the ring oscillator and the target frequency.

[0139] After the frequency matching control module completes the adjustment of the self-oscillation frequency of the ring oscillator, the buffer can start injecting the four-phase injection clock signal.

[0140] After the buffer inputs the four-phase injection clock signal into the ring oscillator, the frequency matching control module uses negative feedback to eliminate the phase deviation information.

[0141] As a way of the embodiments of the present disclosure, by adjusting the self-oscillation frequency of the ring oscillator before the four-phase injection clock signal is input into the ring oscillator and eliminating the phase deviation of the ring oscillator after the four-phase injection clock signal is input into the ring oscillator, the effective elimination of the phase deviation at multiple self-oscillation frequencies of the ring oscillator is achieved, so that the ring oscillator can generate accurate clock signals at multiple self-oscillation frequencies, thereby improving the frequency coverage range of the clock signal output by the ring oscillator.

[0142] In some embodiments, the phase detector is configured to: determine a phase detection sign bit according to an injection mode control signal; determine a frequency deviation according to the self-oscillation frequency of the ring oscillator, the frequency of the injection clock signal, and the injection mode control signal; and determine the phase deviation information according to the phase detection sign bit and the frequency deviation.

[0143] Wherein, the phase detection sign bit is used to hold or flip the phase. When the value of the phase detection sign bit is 1, the phase can be held; when the value of the phase detection sign bit is 2, the phase can be flipped.

[0144] In one example, the value of the injection mode control signal is 2k - 1, where k is a positive integer, the last two bits of the binary code of k are the mode control word, and the phase discrimination sign bit is determined according to the mode control word. Assuming that the last two bits of the binary code of k are denoted as b1 and b0, the mode control word can be expressed as (b1, b0).

[0145] Figure 6 FIG. is a schematic diagram of phase discrimination sign bit control provided by an embodiment of the present disclosure. Referring to Figure 6 , the frequency matching control module may include a ninth switch S9 and a tenth switch S10. When the ninth switch S9 is closed and the tenth switch S10 is open, the value of the phase discrimination sign bit is -1; when the ninth switch S9 is open and the tenth switch S10 is closed, the value of the phase discrimination sign bit is 1. Among them, the closing or opening of the ninth switch can be controlled by a third control signal MC3, and the closing or opening of the tenth switch can be controlled by a fourth control signal MC4. It should be understood that the third control signal MC3 and the fourth control signal MC4 are opposite, and the states of the ninth switch S9 and the tenth switch S10 are opposite.

[0146] In the embodiment of the present disclosure, the third control signal MC3 and the fourth control signal MC4 can be determined first according to the mode control word (b1, b0), and then the phase discrimination sign bit can be determined according to the third control signal MC3 and the fourth control signal MC4. In one example, the third control signal and the fourth control signal can determine whether the value of the phase discrimination sign bit is 1 or -1 by controlling the opening or closing of the ninth switch and the tenth switch.

[0147] Figure 7 FIG. is a schematic diagram of the generation of a switch control signal provided by an embodiment of the present disclosure. Referring to Figure 7 , the first bit b1 and the second bit b0 of the mode control word are used as the inputs of an exclusive OR gate, and the output of the exclusive OR gate is connected to the fourth control signal MC4. The output of the exclusive OR gate has the same value as the fourth control signal MC4. The first bit b1 and the second bit b0 of the mode control word are used as the inputs of an exclusive OR gate, and the output of the exclusive OR gate is connected to the third control signal MC3 through an inverter. The output of the exclusive OR gate has a value opposite to that of the third control signal MC3. Among them, when the value of the fourth control signal MC4 is 1, the connected tenth switch S10 is closed (i.e., on), and when the value of the fourth control signal MC4 is 0, the connected tenth switch S10 is open (i.e., off). When the value of the third control signal MC3 is 1, the connected ninth switch S9 is closed, and when the value of the third control signal MC3 is 0, the connected ninth switch S9 is open.

[0148] Figure 8 FIG. is a schematic diagram of the correspondence between the mode control word, the switch control signal, and the phase discrimination sign bit provided by an embodiment of the present disclosure.

[0149] Reference Figure 8 Figure 8 , when the values of the mode control word (b1, b0) are (0, 0), the value of the fourth control signal MC4 is 0, and the value of the third control signal MC3 is 1, controlling the tenth switch S10 to open and the ninth switch S9 to close. At this time, the phase discrimination sign bit takes the value of -1.

[0150] Reference Figure 8 Figure 8 , when the values of the mode control word (b1, b0) are (0, 1), the value of the fourth control signal MC4 is 1, and the value of the third control signal MC3 is 0, controlling the tenth switch S10 to close and the ninth switch S9 to open. At this time, the phase discrimination sign bit takes the value of 1.

[0151] Reference Figure 8 Figure 8 , when the values of the mode control word (b1, b0) are (1, 0), the value of the fourth control signal MC4 is 1, and the value of the third control signal MC3 is 0, controlling the tenth switch S10 to close and the ninth switch S9 to open. At this time, the phase discrimination sign bit takes the value of 1.

[0152] Reference Figure 8 Figure 8 , when the values of the mode control word (b1, b0) are (1, 1), the value of the fourth control signal MC4 is 0, and the value of the third control signal MC3 is 1, controlling the tenth switch S10 to open and the ninth switch S9 to close. At this time, the phase discrimination sign bit takes the value of -1.

[0153] Figure 9 This is a schematic diagram of the operation of a frequency matching control module provided by an embodiment of the present disclosure. Refer to Figure 9 Figure 9 , the frequency matching control module of the embodiment of the present disclosure includes a coarse tuning loop and a fine tuning loop. Among them, before the buffer operates (i.e., injecting the four-phase injection clock signal into the buffer), the frequency matching control module coarsely tunes the self-oscillation frequency of the ring oscillator through the coarse tuning loop.

[0154] Reference Figure 9 Figure 9 , the coarse tuning process includes: when the frequency of the four-phase injection clock signal is f INJ INJ and the injection mode control signal is INJ_MODE, the coarse tuning loop obtains and measures the self-oscillation frequency f osc of the ring oscillator, compares fI NJ / INJ_MODE with f osc , and the difference between the two is Δf = f INJ / INJ_MODE - f osc , and then tunes the self-oscillation frequency of the ring oscillator according to Δf. If Δf > 0, then increase f osc , if Δf < 0, then decrease f osc After the buffer operates (i.e., injecting the four-phase injection clock signal into the buffer), the frequency matching control module performs fine-tuning through the fine-tuning loop.

[0155] Referring to Figure 9 , the fine-tuning process includes: the phase detector first determines the phase detection sign bit sign according to the injection mode control signal; then, according to the phase detection sign bit sign and the frequency deviation Δf, determines the phase deviation information V pd . Then, the frequency matching control module is based on V pd Whether it is greater than 0, uses negative feedback to eliminate the above phase deviation signal, and obtains an edge-accurate multi-phase clock signal.

[0156] In one example, the phase deviation information V pd ≈ sign × K pd × Δf.

[0157] Among them, the value of the phase detection sign bit sign is determined by the third control signal MC3 and the fourth control signal MC4. When (MC4, MC3) = (0, 1), sign = -1, and when (MC4, MC3) = (1, 0), sign = 1. (MC4, MC3) under different mode control words (b1, b0) can be referred to Figure 8 .

[0158] Among them, the phase deviation K pd Can be determined according to the selected phase detection clock signal. For example, the selected phase detection clock signal can be the clock signal output at each injection node. Refer to Figure 9 , N to 4 MUX represents a ring oscillator with four-phase injection N-level output, and its output clock signal is CKO<N - 1, 0>, where CKO_A, B, C, D represent the four selected phase detection clock signals CKO_A, CKO_B, CKO_C, and CKO_D. CKO_A represents the clock signal output at the first injection node, CKO_B represents the clock signal output at the second injection node, CKO_C represents the clock signal output at the third injection node, and CKO_D represents the clock signal output at the fourth injection node. Refer to Figure 9 , the phase detection clock signals CKO_A and CKO_B are processed by a multiplier and an adder to obtain a first output result, the phase detection clock signals CKO_C, CKO_D are processed by a multiplier and an adder to obtain a second output result, and the first output result and the second output result can obtain the phase deviation K pd .

[0159] Among them, the frequency deviation Δf refers to the coarse-tuning process, which will not be elaborated here.

[0160] As a way of the embodiments of the present disclosure, by combining a coarse-tuning loop and a fine-tuning loop, the self-oscillation frequency of the ring oscillator can be tuned to different clock frequencies, and the ring oscillator can output multi-phase clock signals with accurate edges at different clock frequencies, thereby greatly broadening the frequency range of the clock signals generated by the multi-phase clock circuit.

[0161] In a second aspect, embodiments of the present disclosure provide a method for generating a multi-phase clock signal, and this method can be applied to the phase clock circuit provided in the first aspect. Referring to Figure 10 , this method may include:

[0162] S1001, obtain an injection mode control signal.

[0163] Among them, the injection mode control signal may refer to the first aspect and will not be elaborated here.

[0164] S1002, determine the injection phase of the four-phase injection clock signal according to the injection mode control signal.

[0165] Among them, the process of determining the injection phase may refer to the first aspect and will not be elaborated here.

[0166] S1003, input the four-phase injection clock signal into the ring oscillator according to the injection phase.

[0167] S1004, generate N-phase clock signals through the ring oscillator.

[0168] In the embodiments of the present disclosure, the injection mode control signal controls the four-phase injection clock signal to be able to switch to various frequency injection ratios and injection phases when injecting into the ring oscillator. At the same time, when the four-phase injection clock signal is injected into the ring oscillator according to different frequency injection ratios and injection phases, clock signals with good performance can be generated, enabling the multi-phase clock circuit to output multi-phase clock signals with accurate edges at different clock frequencies, thereby greatly broadening the frequency range of the clock signals generated by the multi-phase clock circuit.

[0169] In some embodiments, the obtaining of the injection mode control signal includes: determining the injection mode control signal according to the frequency of the four-phase injection clock signal.

[0170] The self-oscillation frequency of the ring oscillator is denoted as f osc , the frequency of the four-phase injection clock signal is denoted as f INJ , the injection mode control signal is denoted as INJ_MODE, then f osc = f INJ / INJ_MODE.

[0171] As a way of an embodiment of the present disclosure, when injecting a mode control signal into a four-phase injection clock signal into a ring oscillator, the injection frequency will be switched, thereby broadening the frequency range of the clock signal generated by the multi-phase clock circuit.

[0172] In some embodiments, determining the injection mode control signal according to the frequency of the four-phase injection clock signal includes: in response to the frequency of the four-phase injection clock signal being greater than or equal to a preset frequency threshold, determining that the mode control signal is a first value; in response to the frequency of the four-phase injection clock signal being less than the frequency threshold, determining that the mode control signal is a second value smaller than the first value.

[0173] Among them, the preset frequency threshold can be used to evaluate whether the frequency of the four-phase injection clock signal is large or small, and the preset frequency threshold can be set as needed, and the embodiments of the present disclosure do not limit it. When the frequency of the four-phase injection clock signal is greater than or equal to the preset frequency threshold, it indicates that the frequency of the four-phase injection clock signal is large; when the frequency of the four-phase injection clock signal is less than the preset frequency threshold, it indicates that the frequency of the four-phase injection clock signal is small.

[0174] Since the jitter performance of the output clock signal deteriorates when the self-oscillation frequency of the ring oscillator is low, and the jitter performance of the output clock signal is good when the self-oscillation frequency of the ring oscillator is high. Therefore, when the frequency of the four-phase injection clock signal is greater than or equal to the preset frequency threshold, a larger first value can be used as the value of the mode control signal, so that the self-oscillation frequency of the ring oscillator becomes larger, realizing the improvement of the jitter performance of the output clock signal; when the frequency of the four-phase injection clock signal is greater than the preset frequency threshold, a smaller second value can be used as the value of the mode control signal, so that the self-oscillation frequency of the ring oscillator is smaller, realizing the expansion of the frequency range.

[0175] As a way of an embodiment of the present disclosure, by adjusting the value of the mode control signal according to the frequency of the four-phase injection clock signal, the switching of the self-oscillation frequency of the ring oscillator is realized, the generation of multi-phase clock signals in a large frequency band range is realized, and the good jitter performance of the clock in a large range is ensured.

[0176] Refer to Figure 11 , the multi-phase clock circuit of the embodiment of the present disclosure includes an injection four-phase injection clock, an injection switch selection module, a buffer, a ring oscillator, a phase detector, a frequency matching control module, and an injection switch control module. Their connection relationships and functions are as follows: the four-phase injection clock signal generates a frequency of fI NJ An accurate four-phase injection clock signal for injection locking; the four-phase injection clock signal is sent to the injection switch selection module, and the correct injection phase is selected under different injection mode control signals to ensure successful injection and stable oscillation; the four-phase injection clock signal is sent to a buffer to enhance the clock driving ability; the buffer is connected to the corresponding injection nodes of the N-ring oscillator, and the corresponding frequency and the four-phase relationship are injected from the injection nodes; the ring oscillator generates clock signals with N phases having phase deviations according to the injected information; the N-phase clock signals containing phase deviation information are sent to a phase detector for extraction to obtain phase deviation information; the obtained phase deviation information is sent to a frequency matching control module, and the ring oscillator is tuned according to the frequency matching requirements under the current injection mode control signal, so as to eliminate the phase deviation and finally generate a group of N-phase clocks with accurate phases. Under the control of the injection mode control signal, this multi-phase clock circuit generation module can cover a wider frequency range and achieve better clock jitter performance.

[0177] Referring to Figure 11 , the four-phase injection clock signal includes clock signals with phases of 0°, 180°, 90°, and 270°. The clock signals injected into the ring oscillator by the four-phase injection clock signal are CKI_A, CKI_B, CKI_C, and CKI_D. The frequency matching control module tunes the ring oscillator through a coarse tuning loop and a fine tuning loop.

[0178] Figure 12 Taking N = 16 as an example, the frequency and phase relationship of the finally output N-phase clock signal when the injection mode control signal is 1 is shown. Referring to Figure 12 , the mode control signal INK_MODE = 1, so the frequency f CKO of the clock signal output by the ring oscillator, the frequency f INJ of the four-phase injection clock signal, and the self-oscillation frequency f osc of the ring oscillator satisfy the frequency relationship f CKO = f INJ = f osc . Figure 13 Taking N = 16 as an example, a schematic diagram of the phase sequence of the output clock signal when the injection mode control signal is 1 is shown. Referring to Figure 13 , arranging the output clock signals in the phase sequence, they are CKO<0>, CKO<9>, CKO<2>, CKO<11>, CKO<4>, CKO<13>, CKO<6>, and CKO<15>, CKO<8>, CKO<1>, CKO<10>, and CKO<3>, CKO<12>, CKO<5>, CKO<14>, and CKO<7> in turn. Referring to Figure 12 , the output clock signals CKO<0>, CKO<9>, CKO<2>, and CKO<11> with adjacent input phases differ by 1 phase from each other.

[0179] Figure 14 Taking N = 16 as an example, the frequency and phase relationship of the finally output N-phase clock signals when the injection mode control signal is 3 is shown. Refer to Figure 14 , the mode control signal INK_MODE = 3, so the frequency f of the clock signal output by the ring oscillator CKO , the frequency f of the four-phase injection clock signal INJ and the self-oscillation frequency f of the ring oscillator osc have the frequency relationship of f CKO = f INJ = 3f osc . Figure 15 Taking N = 16 as an example, the schematic diagram of the phase sequence of the output clock signals when the injection mode control signal is 3 is shown. Refer to Figure 15 , arranging the output clock signals in the phase sequence, they are CKO<0>, CKO<3>, CKO<6>, CKO<9>, CKO<12>, CKO<15>, CKO<2> and CKO<5>, CKO<8>, CKO<11>, CKO<14> and CKO<1>, CKO<4>, CKO<7>, CKO<10> and CKO<3> in turn. Refer to Figure 14 , the output clock signals CKO<0> and CKO<9> with adjacent input phases differ by 3 phases, the output clock signals CKO<9> and CKO<6> differ by 2 phases, and the output clock signals CKO<0> and CKO<3> differ by 1 phase.

[0180] Figure 16 This is a schematic diagram of the relationship between an injection mode control signal, a mode control word, a control signal, and a frequency relationship provided by an embodiment of the present disclosure.

[0181] Refer to Figure 17 , showing the schematic diagram of the effect of achieving low clock jitter by switching the injection mode control signal in the embodiment of the present disclosure. Assume that the tuning range of the designed ring oscillator is f osc =(f min , f max ), where f osc represents the self-oscillation frequency, f min , represents the minimum frequency, f max represents the maximum frequency. Since the clock signal edge of the ring oscillator clock becomes slow at low frequencies, there will be a low-frequency interval (f min , f Jitter,limit ) where the clock jitter performance of the multi-phase clock deteriorates. When f osc > f Jitter,limit When the clock jitter performance is good. When the injection mode control signal INJ_MODE = 5, the frequency variation range of the multi-phase clock circuit is (5f min ~5f max ). However, in the frequency range of (5f min , 5f Jitter,limit ), its clock jitter performance is poor, which greatly reduces the available frequency band range for high-order injection in a single mode. In the embodiments of the present disclosure, the injection mode control signal can be switched. For example, it can be switched to the first-order injection in the frequency range of (5f min , 3f Jitter,limit ) (that is, the injection mode control signal is switched to 1), and switched to the third-order injection in the frequency range of (3f Jitter,limit , 5f Jitter,limit ) (that is, the injection mode control signal is switched to 5), so as to ensure good clock jitter performance. It can be seen that by switching the injection mode control signal, the low-frequency performance deterioration interval and the high-frequency performance good interval are segmented, which not only realizes the generation of multi-phase clocks in a large frequency band range, but also meets the requirement of good clock jitter performance in a large range, and improves the design and application flexibility.

[0182] The present disclosure has disclosed exemplary embodiments, and although specific terms are used, they are used only and should be construed only as general illustrative meanings and not for the purpose of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, the features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various forms and details changes can be made without departing from the scope of the present disclosure as set forth by the appended claims.< / n> < / n>

Claims

1. A multi-phase clock circuit, characterized in that, Comprising: An injection switch control module, an injection switch selection module, a buffer, a ring oscillator with four-phase injection and N-level output, a phase detector, and a frequency matching control module; The injection switch control module is configured to obtain an injection mode control signal; the injection mode control signal characterizes the frequency injection ratio of the four-phase injection clock signal; The injection switch selection module is configured to determine the injection phase of the four-phase injection clock signal according to the injection mode control signal; The buffer is configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase; The ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into the phase detector; The phase detector is configured to extract phase deviation information from the N phase clock signals; The frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal, and the phase deviation information.

2. The multi-phase clock circuit according to claim 1, wherein The value of the injection mode control signal is a positive odd number.

3. The multi-phase clock circuit according to claim 1, wherein The frequency matching control module is configured as follows: Before the buffer inputs the four-phase injection clock signal into the ring oscillator, adjust the self-oscillation frequency of the ring oscillator to the target frequency; The target frequency = the frequency of the four-phase injection clock signal / the value of the injection mode control signal; After the buffer inputs the four-phase injection clock signal into the ring oscillator, use negative feedback to eliminate the phase deviation information.

4. The multi-phase clock circuit according to claim 1, wherein, The phase detector is configured as follows: Determine the phase detection sign bit according to the injection mode control signal; Determine the frequency deviation according to the self-oscillation frequency of the ring oscillator, the frequency of the injection clock signal, and the injection mode control signal; Determine the phase deviation information according to the phase detection sign bit and the frequency deviation.

5. The multi-phase clock circuit according to claim 4, wherein The value of the injection mode control signal is 2k - 1; wherein, k is a positive integer; The last two bits of the binary code of k are the mode control word; the phase detection sign bit is determined according to the mode control word.

6. The multi-phase clock circuit according to claim 1, wherein The four-phase injection clock signal includes a clock signal of the first phase, a clock signal of the second phase, a clock signal of the third phase, and a clock signal of the fourth phase; the first phase, the second phase, the third phase, and the fourth phase are differentially distributed, and the first phase and the second phase are inverted, and the third phase and the fourth phase are inverted; the injection switch selection module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The first end of the first switch is used to access the clock signal of the first phase, and the second end is connected to the first injection node of the ring oscillator via a buffer; The first end of the second switch is used to access the clock signal of the first phase, and the second end is connected to the second injection node of the ring oscillator via a buffer; The first end of the third switch is used to access the clock signal of the second phase, and the second end is connected to the first injection node of the ring oscillator via a buffer; The first end of the fourth switch is used to access the clock signal of the second phase, and the second end is connected to the second injection node of the ring oscillator via a buffer; The first end of the fifth switch is used to access the clock signal of the third phase, and the second end is connected to the third injection node of the ring oscillator via a buffer; The first end of the sixth switch is used to access the clock signal of the third phase, and the second end is connected to the fourth injection node of the ring oscillator via a buffer; The first end of the seventh switch is used to access the clock signal of the fourth phase, and the second end is connected to the third injection node of the ring oscillator via a buffer; The first end of the eighth switch is used to access the clock signal of the fourth phase, and the second end is connected to the fourth injection node of the ring oscillator via a buffer; Wherein, the first injection node, the second injection node, the third injection node and the fourth injection node are output nodes on the ring oscillator with an interval of N / 4, and the interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node.

7. The multi-phase clock circuit according to claim 6, wherein The first switch and the fourth switch are configured to be in the same state; The second switch and the third switch are configured to be in a state opposite to the state of the first switch and the fourth switch; The fifth switch and the eighth switch are controlled by a first control signal determined according to the injection mode control signal; The sixth switch and the seventh switch are controlled by a second control signal opposite to the first control signal.

8. The multi-phase clock circuit according to claim 7, wherein The value of the injection mode control signal is 2k - 1; wherein, k is a positive integer; The last two bits of the binary code of k are the mode control word; the first control signal and the second control signal are determined according to the second bit of the mode control word.

9. A method for generating a multi-phase clock signal, characterized in that, The method is applied to the multi-phase clock circuit according to any one of claims 1 to 8, and the method includes: Obtain an injection mode control signal; Determine the injection phase of the four-phase injection clock signal according to the injection mode control signal; Input the four-phase injection clock signal into the ring oscillator according to the injection phase; Generate N-phase clock signals through the ring oscillator.

10. The method according to claim 9, characterized in that, The obtaining the injection mode control signal includes: Determine the injection mode control signal according to the frequency of the four-phase injection clock signal.

11. The method according to claim 10, wherein The determining the injection mode control signal according to the frequency of the four-phase injection clock signal includes: In response to the frequency of the four-phase injection clock signal being greater than or equal to a preset frequency threshold, determine that the mode control signal is a first value; In response to the frequency of the four-phase injection clock signal being less than the frequency threshold, determine that the mode control signal is a second value smaller than the first value.

Images