Hysteresis voltage dynamically adjustable Schmitt trigger

Abstract

The invention relates to the technical field of integrated circuits, in particular to a hysteresis voltage dynamically adjustable Schmitt trigger, which is characterized in that a drain electrode of a PMOS (P-channel Metal Oxide Semiconductor) tube M7 is connected with a pull-up path in a Schmitt circuit, a source electrode is connected with VCC (Voltage Converter Converter), and a grid electrode is connected with an external control signal VG1; the source electrode of the NMOS tube M8 is connected with the GND, the drain electrode is connected with a pull-down path in the Schmidt circuit, and the grid electrode is connected with an external control signal VG2; the PMOS tube M7 and the NMOS tube M8 adjust the internal on-resistance through correspondingly input external control signals VG1 and VG2, thereby adjusting the positive threshold voltage VT + and the negative threshold voltage VT-of the Schmidt circuit flip threshold. According to the invention, the equivalent impedance of the pull-up path and the pull-down path is changed by adjusting the conduction resistance, the optimization of a traditional six-tube structure is realized, and the positive threshold voltage and the negative threshold voltage are dynamically adjusted on the premise of not changing process parameters.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a Schmitt trigger with dynamically adjustable hysteresis voltage. Background Art

[0002] The traditional six-transistor Schmitt trigger consists of a cross-feedback structure formed by symmetric PMOS and NMOS transistors. Its hysteresis window (hysteresis window) is fixed after manufacturing and cannot be dynamically adjusted according to the noise level or working scenario, resulting in insufficient sensitivity in a low-noise environment or an increased false trigger rate in a strong interference scenario. In the prior art, by adjusting the transistor size or an external resistor network, although the hysteresis voltage (positive threshold voltage VT+ and negative threshold voltage VT-) can be partially adjusted, there are problems such as a limited adjustment range, the need to introduce additional power consumption, and a large area overhead. Summary of the Invention

[0003] The present invention proposes a Schmitt trigger with dynamically adjustable hysteresis voltage to solve the problems of small adjustment range, the need to introduce additional power consumption, and large area overhead when adjusting the hysteresis voltage of the existing Schmitt trigger by adjusting the transistor size or an external resistor network.

[0004] According to an aspect of the present invention, there is provided a Schmitt trigger with dynamically adjustable hysteresis voltage, including: a Schmitt circuit, a PMOS transistor M7, and an NMOS transistor M8; The drain of the PMOS transistor M7 is connected to the pull-up path in the Schmitt circuit, the source of the PMOS transistor M7 is connected to VCC, and the gate of the PMOS transistor M7 is connected to an external control signal VG1; The source of the NMOS transistor M8 is connected to GND, the drain of the NMOS transistor M8 is connected to the pull-down path in the Schmitt circuit, and the gate of the NMOS transistor M8 is connected to an external control signal VG2; The PMOS transistor M7 and the NMOS transistor M8 are used to adjust the internal conduction resistance size through the corresponding input external control signals VG1 and VG2, so as to adjust the positive threshold voltage VT+ and negative threshold voltage VT- of the Schmitt circuit flip threshold.

[0005] Preferably, the Schmitt circuit includes: PMOS transistors M1, M2, M3, and NMOS transistors M4, M5, M6; The source of the PMOS transistor M1 is connected to VCC, and the drain of the PMOS transistor M1 is connected to the source of the PMOS transistor M2; The drain of the PMOS transistor M2 is connected to the drain of the NMOS transistor M4; The source of the NMOS transistor M4 is connected to the drain of the NMOS transistor M5; The source of the NMOS transistor M5 is connected to GND; The gates of PMOS transistor M3 and NMOS transistor M6 are both connected to the output signal OUT; The drain of PMOS transistor M3 is connected to GND, and the source of PMOS transistor M3 is connected between PMOS transistors M1 and M2; The drain of NMOS transistor M6 is connected to VCC, and the source of NMOS transistor M6 is connected between NMOS transistors M4 and M5; The gates of PMOS transistors M1, M2 and NMOS transistors M4, M5 are connected to the input signal IN.

[0006] Preferably, the drain of the PMOS transistor M7 is connected to the source of the PMOS transistor M1 in the pull-up path of the Schmitt circuit; The drain of the NMOS transistor M8 is connected to the source of the NMOS transistor M5 in the pull-down path of the Schmitt circuit.

[0007] Preferably, the sizes of the PMOS transistors M1, M2, M3 and the NMOS transistors M4, M5, M6 are set according to the initial forward threshold voltage VT+ and negative threshold voltage VT-.

[0008] Preferably, the sizes of the PMOS transistor M7 and the NMOS transistor M8 are the same as those of the PMOS transistors M1, M2, M3 and the NMOS transistors M4, M5, M6, or the difference between the two is within a predetermined range.

[0009] Preferably, it further includes: an inversion circuit; The inversion circuit is connected to the output of the Schmitt circuit, and the inversion circuit is used to ensure that the output of the Schmitt circuit is a standard VCC or 0.

[0010] Preferably, the inversion circuit includes: a PMOS transistor M9 and an NMOS transistor M10; The source of the PMOS transistor M9 is connected to VCC; The source of the NMOS transistor M10 is connected to GND; The drains of the PMOS transistor M9 and the NMOS transistor M10 are both connected to the output signal OUT; The gates of the PMOS transistor M9 and the NMOS transistor M10 are connected to the drain outputs of the PMOS transistor M2 and the NMOS transistor M4.

[0011] Preferably, the output signal OUT of the Schmitt circuit is tested under different input voltage signals and different external control signals, and the magnitude of the input external control signal is adjusted according to the test results so that the flip threshold of the Schmitt circuit reaches a predetermined flip threshold.

[0012] Preferably, the change range of the different input voltage signals is 0V ~A and A~0V, where A is the MOS transistor specification voltage.

[0013] Preferably, the PMOS transistor and the NMOS transistor are metal-oxide-semiconductor field effect transistors.

[0014] The present invention has at least the following beneficial effects: The present invention provides a Schmitt trigger with dynamically adjustable hysteresis voltage. By adding a PMOS transistor and an NMOS transistor and connecting an external control signal, the equivalent impedance of the pull-up path and the pull-down path is changed by adjusting the on-resistance, so as to optimize the traditional six-transistor structure, and realize the dynamic adjustment of the positive threshold voltage and the negative threshold voltage without changing the process parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are incorporated herein and form a part of this specification. These drawings illustrate embodiments consistent with the present invention and, together with the specification, are used to explain the technical solutions of the present invention.

[0016] Figure 1 A circuit diagram showing a Schmitt trigger with dynamically adjustable hysteresis voltage according to an embodiment of the present invention; Figure 2 A Schmitt circuit diagram showing an embodiment of the present invention; Figure 3 A schematic diagram showing the positive threshold voltage according to an embodiment of the present invention; Figure 4 A schematic diagram showing the negative threshold voltage according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Hereinafter, various exemplary embodiments, features and aspects of the present invention will be described in detail with reference to the drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0018] The special term "exemplary" herein means "serving as an example, embodiment or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

[0019] The term "and / or" herein is only a description of the associated relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set composed of A, B, and C.

[0020] In addition, to better illustrate the present invention, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present invention can also be implemented without certain specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail in order to highlight the gist of the present invention.

[0021] Figure 1 A circuit diagram of a Schmitt trigger with dynamically adjustable hysteresis voltage according to an embodiment of the present invention is shown; Figure 2 A Schmitt circuit diagram according to an embodiment of the present invention is shown; Figure 3 A schematic diagram of the positive threshold voltage according to an embodiment of the present invention is shown; Figure 4 A schematic diagram of the negative threshold voltage according to an embodiment of the present invention is shown. As Figures 1-4 shown, a Schmitt trigger with dynamically adjustable hysteresis voltage includes: a Schmitt circuit, a PMOS transistor M7, and an NMOS transistor M8; the drain of the PMOS transistor M7 is connected to the pull-up path in the Schmitt circuit, the source of the PMOS transistor M7 is connected to VCC, and the gate of the PMOS transistor M7 is connected to an external control signal VG1; the source of the NMOS transistor M8 is connected to GND, the drain of the NMOS transistor M8 is connected to the pull-down path in the Schmitt circuit, and the gate of the NMOS transistor M8 is connected to an external control signal VG2; the PMOS transistor M7 and the NMOS transistor M8 are used to adjust the magnitude of their internal conduction resistance through the correspondingly input external control signals VG1 and VG2, thereby adjusting the positive threshold voltage VT+ and the negative threshold voltage VT- of the Schmitt circuit flip threshold.

[0022] In an embodiment of the present invention, as Figure 1 shown, to achieve the dynamic adjustment function, the present invention adds a PMOS transistor M7 in the pull-up path of the Schmitt circuit, its source is connected to VCC, its drain is connected to the pull-up path, and its gate is connected to an external control signal VG1; at the same time, an NMOS transistor M8 is added in the pull-down path of the Schmitt circuit, its source is connected to GND, its drain is connected to the pull-down path, and its gate is connected to an external control signal VG2.

[0023] By synchronously or independently adjusting the voltage values of the input external control signals VG1 and VG2, the conduction states of the PMOS transistor M7 and the NMOS transistor M8 can be changed respectively, and further the effective driving capabilities of the pull-up and pull-down paths of the Schmitt circuit can be adjusted, and finally the precise control of the positive threshold voltage VT+ and the negative threshold voltage VT− can be achieved.

[0024] When adjusting the positive threshold voltage VT+ and the negative threshold voltage VT-, by inputting external control signals VG1 and / or VG2 of a predetermined voltage to PMOS transistor M7 and / or NMOS transistor M8, the flip threshold of the output node of the Schmitt circuit is adjusted, that is, the magnitudes of VT- and / or VT+ reach a predetermined flip threshold; wherein, if VG1 increases, VT- decreases, and if VG1 decreases, VT- increases; if VG2 increases, VT+ decreases, and if VG2 decreases, VT+ increases.

[0025] Specifically, when the input signal IN of the Schmitt circuit transitions from 1 (high level) to 0 (low level), the positive feedback mechanism of the Schmitt circuit, that is, the PMOS transistors on the pull-up path are accelerated to conduct, but due to the insertion of PMOS transistor M7, the actual source voltage of the PMOS transistors on the pull-up path is divided by the on-resistance of PMOS transistor M7. If the voltage of the input external control signal VG1 is increased, it will cause the on-resistance of PMOS transistor M7 to increase, such that the output node of the Schmitt circuit requires a lower input voltage to trigger a flip, that is, VT- decreases; conversely, if the voltage of the input external control signal VG1 is decreased, the on-resistance of PMOS transistor M7 decreases, and VT- increases accordingly.

[0026] Similarly, when IN changes from a low level to a high level, if the voltage of the control signal VG2 is increased, the on-resistance of NMOS transistor M8 decreases, and the source voltage of the NMOS transistors in the pull-down line is closer to GND, thereby enhancing the discharge speed of the NMOS pull-down network, such that the output node can complete a flip at a lower input voltage, that is, VT+ decreases; conversely, if VG2 is decreased, the on-resistance of M8 increases, the source voltage of the NMOS transistors in the pull-down line rises, the pull-down ability weakens, and VT+ increases.

[0027] In the present invention, the Schmitt circuit includes: PMOS transistors M1, M2, M3 and NMOS transistors M4, M5, M6; the source of PMOS transistor M1 is connected to VCC, and the drain of PMOS transistor M1 is connected to the source of PMOS transistor M2; the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M4; the source of NMOS transistor M4 is connected to the drain of NMOS transistor M5; the source of NMOS transistor M5 is connected to GND; the gates of PMOS transistor M3 and NMOS transistor M6 are both connected to the output signal OUT; the drain of PMOS transistor M3 is connected to GND, and the source of PMOS transistor M3 is connected between PMOS transistors M1 and M2; the drain of NMOS transistor M6 is connected to VCC, and the source of NMOS transistor M6 is connected between NMOS transistors M4 and M5; the gates of PMOS transistors M1, M2 and NMOS transistors M4, M5 are connected to the input signal IN.

[0028] In an embodiment of the present invention, as Figure 2As shown, the Schmitt circuit structure consists of three PMOS transistors M1 - M3 and three NMOS transistors M4 - M6 to form a core cross - coupled feedback network.

[0029] The positive conversion process of the Schmitt circuit is as follows: When the input signal IN is 0 (low level), NMOS transistors M4 and M5 are closed, and NMOS transistor M6 conducts to pull down OUT. When the input signal IN increases from 0 to the point where NMOS transistor M4 conducts, the output starts to drop, causing NMOS transistor M6 to slowly turn off. At the same time, as the input continues to increase, NMOS transistor M4 conducts faster, the output drops faster, and NMOS transistor M6 turns off faster. Finally, NMOS transistors M4 and M5 are fully conducting. This is a positive feedback process.

[0030] The principle of the negative conversion of the Schmitt circuit is the same as that of the positive conversion, that is: When the input is 1 (high level), PMOS transistors M1 and M2 are closed, and PMOS transistor M3 conducts to pull down OUT. When the input decreases from 1 to the point where PMOS transistor M2 conducts, the output starts to rise, causing PMOS transistor M3 to slowly turn off. At the same time, as the input continues to decrease, PMOS transistor M2 conducts faster, the output rises faster, and PMOS transistor M3 turns off faster. Finally, PMOS transistors M1 and M2 are fully conducting.

[0031] In the present invention, the drain of the PMOS transistor M7 is connected to the source of the PMOS transistor M1 in the pull - up path of the Schmitt circuit; the drain of the NMOS transistor M8 is connected to the source of the NMOS transistor M5 in the pull - down path of the Schmitt circuit.

[0032] In the embodiment of the present invention, when the input signal IN transitions from a high level to a low level, the positive feedback mechanism of the Schmitt circuit causes PMOS transistors M1 - M2 to conduct faster. However, due to the insertion of the PMOS transistor M7, the actual source voltage of the PMOS transistor M1 is divided by the on - resistance of the PMOS transistor M7. If the voltage of the control signal VG1 is increased, the on - resistance of the PMOS transistor M7 increases, causing the output node between PMOS transistors M5 and M6 to require a lower input voltage to trigger a flip, that is, VT - decreases; conversely, if VG1 is decreased, the on - resistance of the PMOS transistor M7 decreases, and VT - rises accordingly.

[0033] When the input signal IN changes from a low level to a high level, if the voltage of the control signal VG2 is increased, the on - resistance of the NMOS transistor M8 decreases, and the source voltage of the NMOS transistor M5 is closer to GND, thereby enhancing the discharge speed of the NMOS pull - down network, enabling the output node to complete a flip at a lower input voltage, that is, VT + decreases; conversely, if VG2 is decreased, the on - resistance of the NMOS transistor M8 increases, the source voltage of the NMOS transistor M5 rises, the pull - down ability weakens, and VT + rises.

[0034] In the present invention, the sizes of the PMOS transistors M1, M2, M3 and the NMOS transistors M4, M5, M6 are set according to the initial positive threshold voltage VT+ and negative threshold voltage VT-.

[0035] In an embodiment of the present invention, the initial hysteresis window (the difference between VT+ and VT-) of the Schmidt circuit is determined by the width-to-length ratio (W / L) ratios of M1 and M3, and M5 and M6. By adjusting the sizes of the transistors (MOS transistors), the setting of the initial fixed switching threshold can be achieved, but the overall structure depends on the strict matching of the transistor (MOS transistor) parameters.

[0036] In the present invention, the sizes of the PMOS transistor M7 and the NMOS transistor M8 are the same as those of the PMOS transistors M1, M2, M3 and the NMOS transistors M4, M5, M6, or the difference between the two is within a predetermined range.

[0037] In an embodiment of the present invention, if the sizes of the PMOS transistor M7 and the NMOS transistor M8 are set too large or too small, the external control signals VG1 and VG2 to be input during adjustment, as well as the power supply and circuit interference, will be affected, and at the same time, the subsequent layout design workload will increase.

[0038] During adjustment, if an input signal can be sent by the same controller to drive IN, VG1, and VG2, the sizes of the PMOS transistor M7 and the NMOS transistor M8 and the sizes of M1-M6 cannot differ too much. Therefore, in order to reduce the usage cost, when setting the PMOS transistor M7 and the NMOS transistor M8, it is necessary to make their sizes as consistent as possible with those of M1-M6.

[0039] In the present invention, it further includes: a reverse circuit; the reverse circuit is connected to the output of the Schmidt circuit, and the reverse circuit is used to ensure that the output of the Schmidt circuit is a standard VCC or 0.

[0040] In an embodiment of the present invention, there is a problem when adjusting by adding the PMOS transistor M7 and the NMOS transistor M8, that is, the output signal may not reach the power supply voltage (VCC) or ground 0 (GND). The reason is that if the external control voltage VG1 of the gate of the newly added PMOS transistor M7 is not low enough, for example, not close to 0, its on-resistance R M7 will increase significantly, resulting in insufficient pull-up ability. Similarly, if the external control voltage VG2 of the gate of the newly added NMOS transistor M8 is not high enough, for example, not close to VCC, its on-resistance R M8 will also increase, weakening the pull-down ability.

[0041] To solve the above problems, an inverter composed of PMOS transistor M9 and NMOS transistor M10 is added after the output of the original Schmitt circuit. That is, if the original output fails to reach 0 or VCC, the subsequent inverter can still output standard VCC and 0, and at the same time make the high / low logic of the output consistent with that of the input, which is convenient for subsequent designs.

[0042] In the present invention, the reverse circuit includes: PMOS transistor M9 and NMOS transistor M10; the source of the PMOS transistor M9 is connected to VCC; the source of the NMOS transistor M10 is connected to GND; the drains of the PMOS transistor M9 and the NMOS transistor M10 are both connected to the output signal OUT; The gates of the PMOS transistor M9 and the NMOS transistor M10 are connected to the drain outputs of the PMOS transistor M2 and the NMOS transistor M4.

[0043] In the embodiment of the present invention, the functions of the PMOS transistor M9 and the NMOS transistor M10 are to pull the level back to VCC or GND again to prevent the output signal range from being lower than VCC or higher than GND.

[0044] Taking the standard CMOS inverter (reverse circuit) as the output stage, using the complementary switching characteristics of its PMOS transistor M9 and NMOS transistor M10, the non-ideal levels (such as high level = VCC−ΔV1, low level = ΔV2) output by the Schmitt core circuit are restored to the complete power rails (VCC, 0); the input logic threshold of the inverter matches the Schmitt output level to ensure that the final output signal is in phase (in-phase or anti-phase) with the input signal, realizing the restoration of the output swing and the guarantee of signal integrity.

[0045] In the present invention, the output signal OUT of the Schmitt circuit is tested under different input voltage signals and different external control signals, and the magnitude of the input external control signal is adjusted according to the test results so that the flip threshold of the Schmitt circuit reaches a predetermined flip threshold.

[0046] In the present invention, the variation range of the different input voltage signals is 0V~A and A~0V, where A is the MOS transistor specification voltage.

[0047] In the embodiment of the present invention, the output signal results under different input voltage signals and different external control signals are as Figure 3 and 4 shown, where the different external input signal voltage values set are 0v, 1.25v, 2.5v, 3.75v, 5v respectively. Figure 3 It is a schematic diagram of the change of the forward threshold voltage VT+ (the intersection of the input signal IN of the Schmitt circuit and the external input signal) caused by the change of VG2 from 0-5v when the input signal IN changes from 0-5v; Figure 4Schematic diagram of the change in the negative threshold voltage VT− (the intersection of the input signal IN of the Schmitt circuit and the external input signal) caused by the change of VG1 from 0 - 5V when the input signal IN changes from 5V - 0.

[0048] Through this structural design, the adjustment of VT+ and VT− is completely decoupled. Users can independently set the width and position of the hysteresis window, that is, the threshold value, according to actual needs. This adjustment process does not require modifying the physical structure or manufacturing parameters of the circuit, and only needs to be completed in real time through an external voltage signal, significantly improving the environmental adaptability and functional flexibility of the circuit.

[0049] In the present invention, the PMOS transistor and the NMOS transistor are metal - oxide semiconductor field - effect transistors.

[0050] In the present invention, in the pull - up path of the six - transistor Schmitt trigger, a fourth PMOS transistor M7 with controllable gate voltage is added between the power supply (VCC) and the source of the uppermost PMOS transistor M1, and its gate is connected to an external control signal VG1; in the pull - down path, a fourth NMOS transistor M8 with controllable gate voltage is added between the ground (GND) and the source of the lowermost NMOS transistor M5, and its gate is connected to an external control signal VG2; at the output end of the Schmitt core circuit, a standard CMOS inverter (composed of a PMOS transistor M9 and an NMOS transistor M10) is cascaded, its input is connected to the Schmitt output node, and the output is used as the final signal terminal, and the power supply of the inverter shares VDD / GND with the Schmitt circuit.

[0051] By adjusting the voltage value of VG1, the on - resistance of M7 is controlled, thereby changing the equivalent impedance of the PMOS pull - up path: when VG1 decreases, the conduction of M7 enhances, and the negative threshold voltage VT− of the Schmitt circuit increases; conversely, VT− decreases; by adjusting the voltage value of VG2, the on - resistance of M8 is controlled, thereby changing the equivalent impedance of the NMOS pull - down path: when VG2 increases, the conduction of M8 enhances, and the positive threshold voltage VT+ of the Schmitt circuit decreases; conversely, VT+ increases; the adjustment of VT+ and VT− is independent of each other, and the hysteresis window (ΔVH = VT+ minus VT−) can be set as required.

[0052] It can be understood that the above - mentioned various embodiments of the present invention can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, the present invention will not elaborate further.

[0053] The present invention designs a Schmitt trigger circuit with dynamically adjustable hysteresis voltage and complete output swing. By adding a PMOS transistor and an NMOS transistor with controllable gate voltages in the pull-up and pull-down paths respectively, and integrating the output stage of a standard CMOS inverter, the dual functions of dynamic adjustment of the threshold voltage and full swing recovery of the output signal are achieved, significantly improving the environmental adaptability and signal integrity of the circuit. The beneficial effects of the present invention at least include the following: 1. The hysteresis window is dynamically adjustable, enhancing the scene adaptability; by designing the gate voltages of the independently adjustable PMOS transistor (M7) and NMOS transistor (M8), the positive threshold voltage VT+ and the negative threshold voltage VT− can be accurately controlled, avoiding the difficulty in adapting to the changing working environment due to the fixed hysteresis interval after manufacturing. 2. The output swing is restored without loss, ensuring signal integrity; a standard CMOS inverter (M9 and M10) is set as the output buffer stage, and its low-impedance driving characteristic is used to force the attenuation level caused by the series resistance in the previous stage to be restored to the power rail, eliminating the level loss. The input high / low logic thresholds of the inverter match the Schmitt core circuit, ensuring that the output signal is in phase with the input. 3. The structure is compatible with the standard process and the cost is controllable; by setting two controllable MOS transistors and an inverter, without special devices or complex control modules, it can be directly manufactured based on the existing CMOS production line. By inserting controlled MOS transistors in the pull-up path and the pull-down path respectively on the basis of the Schmitt circuit to adjust the on-resistance, the convenient and rapid adjustment of the Schmitt trigger flip threshold is realized without changing the transistor size, reducing the production and use costs.

[0054] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.

Claims

1. A Schmitt trigger with dynamically adjustable hysteresis voltage, characterized in that, Including: A Schmitt circuit, a PMOS transistor M7, and an NMOS transistor M8; The drain of the PMOS transistor M7 is connected to the pull-up path in the Schmitt circuit, the source of the PMOS transistor M7 is connected to VCC, and the gate of the PMOS transistor M7 is connected to an external control signal VG1; The source of the NMOS transistor M8 is connected to GND, the drain of the NMOS transistor M8 is connected to the pull-down path in the Schmitt circuit, and the gate of the NMOS transistor M8 is connected to an external control signal VG2; The PMOS transistor M7 and the NMOS transistor M8 are used to adjust the internal on-resistance by corresponding input external control signals VG1 and VG2, thereby adjusting the positive threshold voltage VT+ and the negative threshold voltage VT- of the Schmitt circuit flip threshold.

2. The Schmitt trigger with hysteresis voltage dynamically adjustable according to claim 1, characterized in that, The Schmitt circuit includes: PMOS transistors M1, M2, M3 and NMOS transistors M4, M5, M6; The source of the PMOS transistor M1 is connected to VCC, and the drain of the PMOS transistor M1 is connected to the source of the PMOS transistor M2; The drain of the PMOS transistor M2 is connected to the drain of the NMOS transistor M4; The source of the NMOS transistor M4 is connected to the drain of the NMOS transistor M5; The source of the NMOS transistor M5 is connected to GND; The gates of the PMOS transistor M3 and the NMOS transistor M6 are both connected to the output signal OUT; The drain of the PMOS transistor M3 is connected to GND, and the source of the PMOS transistor M3 is connected between the PMOS transistors M1 and M2; The drain of the NMOS transistor M6 is connected to VCC, and the source of the NMOS transistor M6 is connected between the NMOS transistors M4 and M5; The gates of the PMOS transistors M1, M2 and the NMOS transistors M4, M5 are connected to the input signal IN.

3. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 2, characterized in that: The drain of the PMOS transistor M7 is connected to the source of the PMOS transistor M1 in the pull-up path of the Schmitt circuit; The drain of the NMOS transistor M8 is connected to the source of the NMOS transistor M5 in the pull-down path of the Schmitt circuit.

4. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 1, characterized in that: The sizes of the PMOS transistors M1, M2, M3 and the NMOS transistors M4, M5, M6 are set according to the initial positive threshold voltage VT+ and negative threshold voltage VT-.

5. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 1, characterized in that The sizes of the PMOS transistor M7 and the NMOS transistor M8 are the same as those of the PMOS transistors M1, M2, M3 and the NMOS transistors M4, M5, M6, or the difference between the two is within a predetermined range.

6. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 2, characterized in that, It further includes: An inverter circuit; The inverter circuit is connected to the output of the Schmitt circuit, and the inverter circuit is used to ensure that the output of the Schmitt circuit is a standard VCC or 0.

7. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 6, wherein The inverter circuit includes: a PMOS transistor M9 and an NMOS transistor M10; The source of the PMOS transistor M9 is connected to VCC; The source of the NMOS transistor M10 is connected to GND; The drains of the PMOS transistor M9 and the NMOS transistor M10 are both connected to the output signal OUT; The gates of the PMOS transistor M9 and the NMOS transistor M10 are connected to the drain outputs of the PMOS transistor M2 and the NMOS transistor M4.

8. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 1, characterized in that: The output signal OUT of the Schmitt circuit under different input voltage signals and different external control signals is tested, and the magnitude of the input external control signal is adjusted according to the test results, so that the flip threshold of the Schmitt circuit reaches a predetermined flip threshold.

9. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 8, characterized in that: The variation range of the different input voltage signals is 0V~A and A~0V, where A is the specification voltage of the MOS transistor.

10. The Schmitt trigger with dynamically adjustable hysteresis voltage according to claim 1, characterized in that: The PMOS transistor and the NMOS transistor are metal-oxide-semiconductor field effect transistors.

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