Low-power-consumption dynamic comparator with dynamic tail current and operation method
By increasing the tail current DC path and load capacitance, the problem of difficulty in fully establishing and amplifying the input signal in low-power dynamic comparator is solved, the complete amplification of the input signal and the reduction of power consumption are achieved, and the resolution and frequency of the comparator are improved.
Patent Information
- Application Number
- CN202510333215.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-07-04
AI Technical Summary
There is no DC path for the tail current source in the low-power dynamic comparator, which makes it difficult to fully establish and amplify the input signal during amplification, and the small parasitic capacitance makes it difficult to fully establish and amplify the input signal during amplification, affecting the resolution of the comparator.
A low-power dynamic comparator with dynamic tail current is designed, and the tail current DC path and load capacitance is added. A dynamic tail current source module is formed through the charge collection module and the tail current DC path to ensure that the input signal is fully established and amplified during the amplification period, and the tail current is dynamically adjusted to turn off the switch tube in advance to reduce power consumption.
Complete establishment and amplification of the input signal during amplification is achieved, the resolution of the comparator is improved, and the power consumption of the comparator is reduced.
Smart Images
Figure CN120263157A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of analog integrated circuits, relates to a dynamic comparator, and particularly relates to a low-power dynamic comparator with a dynamic tail current and an operation method thereof. Background Art
[0002] In the design of low-power ADCs such as SAR ADCs, the most commonly used comparator is the dynamic comparator. Among them, although the dynamic comparator with a StrongArm structure can reduce power consumption, the input common-mode voltage of the StrongArm structure must be stable within a specific range. If the common-mode voltage is too high, the input pair transistors are easily turned into the linear region, resulting in a decrease in gain, deterioration of noise and offset. If the common-mode voltage is too low, the speed of the comparator will be significantly affected. In the traditional Double Tail structure comparator, the voltage provided by the parasitic capacitance cannot ensure the complete establishment of the input signal. And after obtaining the result, the parasitic capacitance in the preamplification stage is still discharging until it enters the reset stage before stopping, resulting in an increase in the power consumption of the comparator. In reference [1], a dynamic bias module is added to the preamplification stage, and a capacitor is connected in series in the tail current of the preamplification stage to generate a dynamic voltage to turn off the tail current source in a timely manner to reduce the power consumption of the comparator. However, this solution has the following two problems: 1) There is no direct current path for the tail current source, resulting in difficulty in fully amplifying the input signal during amplification; 2) The parasitic capacitance is used to supply power to the input stage of the preamplifier. However, due to the small size of the parasitic capacitance itself and the fast discharge speed, it is difficult for the input signal to be fully established and amplified during the signal amplification in the preamplification stage. If the signal is not fully established and amplified, it may cause the latch stage to fail to correctly identify the input difference, and the comparator cannot distinguish between similar input voltages, resulting in a decrease in the resolution of the comparator.
[0003] [1].H.S.Bindra,C.E.Lokin,D.Schinkel,A.Annema and B.Nauta,"A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise,"in IEEE Journal of Solid-State Circuits,vol.53,no.7,pp.1902-1912,July 2018,doi:10.1109 / JSSC.2018.2820147。 Summary of the Invention
[0004] Objective of the Invention: To solve the problems that the tail current source in a low-power dynamic comparator has no DC path and the parasitic capacitance is small, resulting in difficulty in fully establishing and amplifying the input signal during signal amplification in the preamplification stage, and to provide a low-power dynamic comparator with a dynamic tail current and an operating method.
[0005] Technical Solution: To achieve the above objective, the present invention provides a low-power dynamic comparator with a dynamic tail current, including a preamplification stage and a latch comparator; the preamplification stage is used to amplify the differential input signal to improve the accuracy of the comparator; the latch comparator is used to generate a rail-to-rail comparison result and improve the operating frequency of the comparator;
[0006] The preamplification stage is composed of an input amplification stage and a dynamic tail current source module. The input amplification stage is composed of an input stage and a load capacitor. The input stage is composed of a fully differential Cascode, an active load, and a set-one switch. The load capacitor is composed of an externally added capacitor and the parasitic capacitance at the output end of the preamplification stage. The dynamic tail current source module is composed of a charge collection module and a tail current DC path;
[0007] The latch comparator is composed of a fully differential positive feedback comparison module, input pair transistors, and a reset switch.
[0008] Further, in the input stage, the fully differential Cascode is composed of MN1, MN4 and MN2, MN3, which are responsible for amplifying the input signal; the active load is composed of MP3 and MP4, which are responsible for pulling N and P to V DD during the reset stage of the comparator; the set-one switch includes MP1 and MP2, which are responsible for pulling X and Y to V DD .
[0009] Further, in the load capacitor, the externally added capacitors are C1 and C2, and the parasitic capacitances at the output end of the preamplification stage are C P , C N . The upper plate of capacitor C1 is connected to the drain of MN4, and the lower plate is grounded; the upper plate of C2 is connected to the drain of MN3, and the lower plate is grounded.
[0010] Further, the gate of MN1 is connected to the input signal V IP , the source is connected to the source of MN2 and the drain of MP9, and the drain is connected to the source of MN4 and the drain of MP1; the gate of MN2 is connected to the input signal V IN , the drain is connected to the source of MN3 and the drain of MP2; the gate of MN3 is connected to the power supply voltage V DD , the drain is connected to the drain of MP4 and the gate of MP6; the gate of MN4 is connected to the power supply voltage V DD, the drain is connected to the drain of MP3 and the gate of MP5; the gates of MP1, MP2, MP3, and MP4 are all connected to the clock control signal CLK, and the sources are all connected to the power supply voltage V DD .
[0011] Further, the charge collection module includes: NMOS transistors MN9, MN10, and capacitor C3; the gate of MN9 is connected to the clock control signal CLK, and the source is connected to the drain of MN10; the gate of MN10 is connected to the clock control signal CLKZ, and the source is grounded; the upper plate of capacitor C3 is connected to the drain of MN10, and the lower plate is grounded.
[0012] Further, the tail current DC path includes NMOS transistor NM11, and the gate and drain of NM11 are commonly connected to the source of MN9, and the source is grounded.
[0013] Further, the fully differential positive feedback comparison module includes MN7, MN8, MP7, and MP8; the input pair transistors include MP5 and MP6; the reset switches include MN5 and MN6.
[0014] Further, the latch comparator includes NMOS transistors MN5, MN6, MN7, MN8, PMOS transistors MP5, MP6, MP7, MP8. The gate of MN5 is connected to the clock control signal CLKZ, the source is grounded, and the drain is connected to the drain of MN7; the gate of MN6 is connected to the clock control signal CLKZ, the source is grounded, and the drain is connected to the drain of MN8; the gate of MN7 is connected to the gate of MP7, the drain of MP6, and the drain of MN8, the source is grounded, and the drain is connected to the drain of MP5. The gate of MN8 is connected to the gate of MP8, the drain of MP5, and the drain of MP7, the source is grounded, and the drain is connected to the drain of MP6; the source of MP5 is connected to the drain of MP7, the source of MP6 is connected to the drain of MP8, the source of MP7 is connected to the power supply voltage V DD , the source of MP8 is connected to the power supply voltage V DD .
[0015] The present invention also provides an operation method of a low-power dynamic comparator with a dynamic tail current, including:
[0016] CLKZ is the inverted signal of CLK. When CLK is at a low level, the comparator is in the reset stage, and the active loads MP3 and MP4 are turned on to charge the capacitors C1 and C2 at N and P to V DD , and the switches MP1 and MP2 are turned on to charge the node capacitors at X and Y to V DD, supply power to the input stage of the preamplifier so that the input signal can be fully established and amplified during signal amplification, and the input pair transistors MP5 and MP6 are turned off; MN9 is turned off and MN10 is turned on. To ensure the normal operation of the next comparison stage, the upper plate of capacitor C3 is discharged to zero; the reset switches MN5 and MN6 are turned on and the output terminals V OP and V ON are pulled to GND;
[0017] When CLK rises from low level to high level, the comparator enters the comparison stage. The switches MP1 and MP2, and the active loads MP3 and MP4 are turned off. MN9 is turned on and MN10 is turned off. The reset switches MN5 and MN6 are turned off. At this time, the node capacitors at X and Y start to discharge first. MN11 is turned on to form a DC loop to charge capacitor C3. When the node voltages at X and Y decrease to make MN4 and MN3 turn on, the capacitors at N and P charge capacitor C3. When the node voltages at N and P drop by a threshold voltage of MP5 and MP6 respectively from V DD , MP5 and MP6 are turned on;
[0018] The V IP and V IN of the differential input voltage are different, which leads to different discharge rates. Assuming that V IP is greater than V IN , the discharge rate at node N is faster than that at P, resulting in MP5 turning on before MP6. The output terminal voltage V OP is first pulled up to V DD by MP7. When V OP is greater than the threshold voltage of MN8, MN8 is turned on, and there is an additional discharge path to GND at the output terminal V ON . The cross-coupled latch composed of MN7, MP7 and MN8, MP8 forms positive feedback and quickly pulls up V OP to V DD , and V ON is pulled down to GND to complete the comparison. As the voltage of the upper plate of capacitor C3 rises, MN9 is turned off in advance, avoiding the continuous decrease of the node voltages at N and P after obtaining the comparison result, and reducing the power consumption of the comparator.
[0019] In the present invention, capacitors C1 and C2 are additionally added to supply power to the input stage of the preamplifier so that the input signal can be fully established and amplified during signal amplification. The DC path of the tail current is increased to ensure that there is a DC path for the tail current source, so that the input signal can be fully amplified during amplification. At the same time, the tail current can be dynamically adjusted to make the switching transistor turn off in advance, reducing the power consumption of the comparator.
[0020] Beneficial effects: Compared with the prior art, the present invention has the following advantages:
[0021] 1. An NMOS transistor MN11 is added to ensure a DC path for the tail current source, enabling the input signal to be fully amplified during the amplification period. Meanwhile, the tail current can be dynamically adjusted to cause the switching transistor MN9 to cut off earlier, reducing the power consumption of the comparator.
[0022] 2. Capacitors C1 and C2 are added to supply power to the input stage of the preamplifier, enabling the input signal to be fully established and amplified during the signal amplification period. Description of the Drawings
[0023] Figure 1 It is the circuit diagram of the dynamic comparator in the embodiment of the present invention.
[0024] Figure 2 It is the circuit simulation diagram of the dynamic comparator in the embodiment of the present invention. Detailed Embodiments
[0025] The present invention will be further illustrated below in conjunction with the drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. After reading the present invention, various equivalent modifications made by those skilled in the art fall within the scope defined by the appended claims of this application.
[0026] Embodiment 1:
[0027] As Figure 1 shown, this embodiment provides a low-power dynamic comparator with a dynamic tail current, including: a preamplifier stage 10 and a latch comparator 20. Among them, the preamplifier stage 10 is composed of an input amplification stage 101 and a dynamic tail current source module 102. The input amplification stage 101 is composed of an input stage 1011 and a load capacitor 1012. The input stage 1011 is composed of cascode, active load, and set-1 switch; the load capacitor 1012 is composed of externally added capacitors C1, C2 and parasitic capacitors C N 、C P constitute; the dynamic tail current source module 102 is composed of a charge collection module 1021 and a tail current DC path 1022.
[0028] The input stage 1011 includes NMOS transistors MN1, MN2, MN3, MN4, and PMOS transistors MP1, MP2, MP3, MP4. Among them, for the NMOS transistors MN1, MN2, W / L = 14μm / 180nm; for the NMOS transistors MN3, MN4, W / L = 10μm / 180nm; for the PMOS transistors MP1, MP2, W / L = 5μm / 180nm; for the PMOS transistors MP3, MP4, W / L = 8μm / 180nm. The gate of MN1 is connected to the input signal V IP, the source is connected to the source of MN2 and the drain of MP9, and the drain is connected to the source of MN4 and the drain of MP1; the gate of MN2 is connected to the input signal V IN , the drain is connected to the source of MN3 and the drain of MP2; the gate of MN3 is connected to the power supply voltage V DD , the drain is connected to the drain of MP4 and the gate of MP6; the gate of MN4 is connected to the power supply voltage V DD , the drain is connected to the drain of MP3 and the gate of MP5; the gates of MP1, MP2, MP3, and MP4 are all connected to the clock control signal CLK, and the sources are all connected to the power supply voltage V DD .
[0029] The load capacitor 1012 includes capacitors C1, C2, and parasitic capacitors C P , C N . The capacitance value of capacitor C1 is 100 pF, and the capacitance value of capacitor C1 is 100 pF. The upper plate of capacitor C1 is connected to the drain of MN4, and the lower plate is grounded; the upper plate of C2 is connected to the drain of MN3, and the lower plate is grounded.
[0030] The charge collection module 1021 includes NMOS transistors MN9, MN10, and capacitor C3. Among them, for NMOS transistor MN9, W / L = 2 μm / 180 nm, for NMOS transistor MN10, W / L = 4 μm / 180 nm, and the capacitance value of capacitor C3 is 100 pF. The gate of MN9 is connected to the clock control signal CLK, and the source is connected to the drain of MN10; the gate of MN10 is connected to the clock control signal CLKZ, and the source is grounded; the upper plate of capacitor C3 is connected to the drain of MN10, and the lower plate is grounded.
[0031] The tail current DC path 1022 includes NMOS transistor NM11. For MN11, W / L = 4 μm / 180 nm, and the gate and drain of NM11 are commonly connected to the source of MN9, and the source is grounded.
[0032] The latch comparator 20 is composed of a fully differential positive feedback comparison module, input pair transistors, and a reset switch. The fully differential positive feedback comparison module includes MN7, MN8, MP7, and MP8; the input pair transistors include MP5 and MP6; the reset switch includes MN5 and MN6.
[0033] Based on this, the latch comparator 20 includes NMOS transistors MN5, MN6, MN7, MN8, and PMOS transistors MP5, MP6, MP7, MP8. The W / L of NMOS transistors MN5 and MN6 is 10μm / 180nm, the W / L of NMOS transistors MN7 and MN8 is 4μm / 180nm, the W / L of PMOS transistors MP5 and MP6 is 8μm / 180nm, and the W / L of PMOS transistors MP7 and MP8 is 8μm / 180nm. The gate of MN5 is connected to the clock control signal CLKZ, the source is connected to the ground terminal, and the drain is connected to the drain of MN7; the gate of MN6 is connected to the clock control signal CLKZ, the source is connected to the ground terminal, and the drain is connected to the drain of MN8; the gate of MN7 is connected to the gate of MP7, the drain of MP6, and the drain of MN8, the source is connected to the ground terminal, and the drain is connected to the drain of MP5. The gate of MN8 is connected to the gate of MP8, the drain of MP5, and the drain of MP7, the source is connected to the ground terminal, and the drain is connected to the drain of MP6; the source of MP5 is connected to the drain of MP7, the source of MP6 is connected to the drain of MP8, the source of MP7 is connected to the power supply voltage V DD , and the source of MP8 is connected to the power supply voltage V DD .
[0034] In this embodiment, the W / L design of the MOS transistor is essentially a multi-objective optimization of the performance of the comparator, such as speed, power consumption, and gain. By optimizing the device parameters, the design goal of low power consumption of the comparator is finally achieved.
[0035] Embodiment 2:
[0036] Based on the low-power dynamic comparator provided in Embodiment 1, this embodiment provides an operating method for a low-power dynamic comparator with a dynamic tail current, including:
[0037] CLKZ is the inverted signal of CLK. When CLK is at a low level, the comparator is in the reset stage. The active loads MP3 and MP4 are turned on and charge the capacitors C1 and C2 at N and P to V DD , the switches MP1 and MP2 are turned on and charge the node capacitors at X and Y to V DD , provide power to the input stage of the preamplifier, so that the input signal can be fully established and amplified during the signal amplification period, and the input pair transistors MP5 and MP6 are turned off; MN9 is turned off and MN10 is turned on. In order to work properly in the next comparison stage, the upper plate of the capacitor C3 is discharged to zero; the reset switches MN5 and MN6 are turned on and pull the output terminals V OP and V ON to GND;
[0038] When the CLK rises from low level to high level, the comparator enters the comparison stage. The switches MP1 and MP2, and the active loads MP3 and MP4 are turned off. MN9 is turned on, and MN10 is turned off. The reset switches MN5 and MN6 are turned off. At this time, the node capacitors at X and Y start to discharge first. MN11 is turned on to form a DC loop to charge the capacitor C3. When the node voltages at X and Y decrease to make MN4 and MN3 conduct, the capacitors at N and P charge the capacitor C3. When the node voltages at N and P drop by a threshold voltage of MP5 and MP6 respectively, MP5 and MP6 conduct; DD When the differential input voltages V
[0039] and V IP and V IN are different, the discharge rates will be different. Assuming V IP is greater than V IN , the discharge rate at node N is faster than that at P, resulting in MP5 conducting before MP6. The output voltage V OP is first pulled up to V DD by MP7. When V OP is greater than the threshold voltage of MN8, MN8 conducts, and there is an additional path for the output V ON to discharge to the ground. The cross-coupled latch formed by MN7, MP7 and MN8, MP8 forms positive feedback and quickly pulls up V OP to V DD , and V ON is pulled down to GND to complete the comparison. As the voltage of the upper plate of capacitor C3 rises, MN9 turns off in advance, avoiding the continuous decrease of the node voltages at N and P after obtaining the comparison result and reducing the power consumption of the comparator.
[0040] Embodiment 3:
[0041] In this embodiment, simulation experiments are carried out to verify the effectiveness and effects of the solution of the present invention, as follows:
[0042] In the simulation as shown in Figure 2 , label 1 is the clock signal CLK of the comparator, label 2 is the inverted clock signal CLKZ of CLK, label 3 is the node voltages at N and P, label 3 is the voltage of the upper plate of capacitor C3, and label 4 is the comparator output V OP and V ON signals.
[0043] When the input signal V IP is greater than V IN , when CLK is at low level, the comparator is in the reset stage. N and P are charged to approximately the power supply voltage, the voltage of the upper plate of C3 is 0, and V OP and V ONAll are reset to the low level; when CLK flips to the high level, the comparator enters the comparison stage, the voltages at N and P decrease, and the voltage drop rate at N is faster than that at P. The voltage of the upper plate of capacitor C3 rises to obtain the comparison result, V OP is at the high level, V ON is at the low level, and the voltages at N and P finally stabilize at 133.3 mV. MN9 is turned off in advance, avoiding the continuous decrease of the node voltages at N and P, thereby reducing the power consumption of the comparator.
Claims
1. A low-power dynamic comparator with a dynamic tail current, characterized in that It includes a pre-amplification stage and a latch comparator. The pre-amplification stage is used to amplify a differential input signal, and the latch comparator is used to generate a rail-to-rail comparison result; The pre-amplification stage is composed of an input amplification stage and a dynamic tail current source module. The input amplification stage is composed of an input stage and a load capacitor. The input stage is composed of a fully differential Cascode, an active load, and a set-one switch. The load capacitor is composed of an externally added capacitor and a parasitic capacitor at the output end of the pre-amplification stage. The dynamic tail current source module is composed of a charge collection module and a direct current path of the tail current; The latch comparator is composed of a fully differential positive feedback comparison module, input pair transistors, and a reset switch.
2. The low-power dynamic comparator with a dynamic tail current according to claim 1, wherein In the input stage, the fully differential Cascode is composed of MN1, MN4 and MN2, MN3, which is responsible for amplifying the input signal; the active load is composed of MP3 and MP4, which is responsible for connecting N and P to V during the comparator reset stage DD ; The set-one switch includes MP1 and MP2, which is responsible for connecting X and Y to V during the comparator reset stage DD .
3. A low-power dynamic comparator with a dynamic tail current according to claim 2, characterized in that, Among the load capacitors, the external capacitors are C1 and C2, and the parasitic capacitors at the output end of the preamplifier stage are C P and C N . The upper plate of capacitor C1 is connected to the drain of MN4, and the lower plate is grounded; the upper plate of C2 is connected to the drain of MN3, and the lower plate is grounded.
4. A low-power dynamic comparator with a dynamic tail current according to claim 3, characterized in that The gate of MN1 is connected to the input signal V IP , the source is connected to the source of MN2 and the drain of MP9, and the drain is connected to the source of MN4 and the drain of MP1; the gate of MN2 is connected to the input signal V IN , the drain is connected to the source of MN3 and the drain of MP2; the gate of MN3 is connected to the power supply voltage V DD , the drain is connected to the drain of MP4 and the gate of MP6; the gate of MN4 is connected to the power supply voltage V DD , the drain is connected to the drain of MP3 and the gate of MP5; the gates of MP1, MP2, MP3, and MP4 are all connected to the clock control signal CLK, and the sources are all connected to the power supply voltage V DD .
5. A low-power dynamic comparator with a dynamic tail current according to claim 4, characterized in that The charge collection module includes: NMOS transistors MN9 and MN10, and capacitor C3; the gate of MN9 is connected to the clock control signal CLK, and the source is connected to the drain of MN10; the gate of MN10 is connected to the clock control signal CLKZ, and the source is connected to the ground terminal; the upper plate of capacitor C3 is connected to the drain of MN10, and the lower plate is connected to the ground terminal.
6. The low-power dynamic comparator with a dynamic tail current according to claim 5, characterized in that The direct current path of the tail current includes NMOS transistor NM11. The gate and drain of NM11 are commonly connected to the source of MN9, and the source is connected to the ground terminal.
7. A low-power dynamic comparator with a dynamic tail current according to claim 6, characterized in that In the latch comparator, the fully differential positive feedback comparison module includes MN7, MN8, MP7, and MP8, the input pair transistors include MP5 and MP6, and the reset switch includes MN5 and MN6.
8. A low-power dynamic comparator with a dynamic tail current according to claim 7, characterized in that The latch comparator includes NMOS transistors MN5, MN6, MN7, MN8, PMOS transistors MP5, MP6, MP7, MP8. The gate of MN5 is connected to the clock control signal CLKZ, the source is connected to the ground terminal, and the drain is connected to the drain of MN7. The gate of MN6 is connected to the clock control signal CLKZ, the source is connected to the ground terminal, and the drain is connected to the drain of MN8. The gate of MN7 is connected to the gate of MP7, the drain of MP6, and the drain of MN8, the source is connected to the ground terminal, and the drain is connected to the drain of MP5. The gate of MN8 is connected to the gate of MP8, the drain of MP5, and the drain of MP7, the source is connected to the ground terminal, and the drain is connected to the drain of MP6. The source of MP5 is connected to the drain of MP7, the source of MP6 is connected to the drain of MP8, the source of MP7 is connected to the power supply voltage V DD , and the source of MP8 is connected to the power supply voltage V DD .
9. A method for operating a low-power dynamic comparator with a dynamic tail current, characterized in that, It includes: CLKZ is the inverted signal of CLK. When CLK is at a low level, during the reset phase of the comparator, the active loads MP3 and MP4 conduct and charge the capacitors C1 and C2 at N and P to V DD , the switches MP1 and MP2 conduct and charge the node capacitors at X and Y to V DD , providing power to the input stage of the preamplifier so that the input signal can be fully established and amplified during the signal amplification period. The input pair transistors MP5 and MP6 are turned off; MN9 is turned off and MN10 is turned on. To ensure normal operation in the next comparison stage, the upper plate of the capacitor C3 is discharged to zero; the reset switches MN5 and MN6 conduct and pull the output terminals V OP and V ON to GND; When the CLK rises from low level to high level, the comparator enters the comparison stage. The switches MP1 and MP2, and the active loads MP3 and MP4 are turned off. MN9 conducts, and MN10 is turned off. The reset switches MN5 and MN6 are turned off. At this time, the node capacitors at X and Y start to discharge first. MN11 conducts, forming a DC loop to charge the capacitor C3. When the node voltages at X and Y decrease to make MN4 and MN3 conduct, the capacitors at N and P charge the capacitor C3. When the node voltages at N and P respectively drop by a threshold voltage of MP5 and MP6, MP5 and MP6 conduct; DD When they have dropped by a threshold voltage of MP5 and MP6, MP5 and MP6 conduct; The V of the differential input voltage IP and V IN differences will result in different discharge rates. Assuming that V IP is greater than V IN , the discharge rate at node N is faster than that at P, causing MP5 to conduct before MP6, and the output voltage V OP is first pulled up to V DD . When V OP is greater than the threshold voltage of MN8, MN8 conducts, and the output terminal V ON has an additional discharge path to the ground. The cross-coupled latch formed by MN7, MP7 and MN8, MP8 forms positive feedback and quickly pulls up V OP to V DD , V ON is pulled down to GND to complete the comparison; as the voltage of the upper plate of capacitor C3 rises, MN9 turns off in advance.