Multi-path parallel high-precision NCO digital circuit based on lookup table deep optimization

Abstract

The invention discloses a multi-path parallel high-precision NCO digital circuit based on lookup table depth optimization. The multi-path parallel high-precision NCO digital circuit comprises a phase accumulator and M phase amplitude mappers, wherein the phase accumulator receives a system clock sysclk and a low (N-m) bit Xlt of an N-bit frequency control word X; (N-m-1): 0gt; and a phase offset value (pheeoffset < t >); w-1: 0gt; according to the system clock sysclk, the N-bit frequency controls the low (N-m) bit Xlt of the word X; (N-m-1): 0gt; and a phase offset value (pheeoffset < t >); w-1: 0gt; outputting an H-bit phase accumulator output value Ylt; h-1: 0gt; ; the structures of the M phase amplitude mappers are the same, and the input of the ith phase amplitude mapper is from the (P-1) th bit to the 0th bit Qilt of the input value Qi of the ith phase amplitude mapper; p-1: 0gt; the output of the SINI2pilt is SINI2pilt; i: 0gt; and COSi < 2 [pi] < lt >; i: 0gt; . According to the invention, the problem that the scale of the lookup table is too large when the high-precision NCO utilizes the lookup table to realize phase amplitude mapping is solved, and the working frequency and the output precision of an NCO digital circuit are greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital circuit design, and particularly relates to a high-precision NCO digital circuit based on lookup table depth optimization and multi-channel parallelism. Background Art

[0002] A numerically controlled oscillator is a fully digital frequency synthesizer that can generate periodic sine and cosine signals. Compared with traditional analog oscillators, NCOs have the advantages of high frequency resolution, strong phase continuity, strong stability, and easy integration. The core function of an NCO is to achieve precise control of frequency and phase offset values through the input frequency control word (FTW) and phase offset value (phase_offset).

[0003] The phase-amplitude mapper of a traditional NCO digital circuit consists of sine and cosine lookup tables. The phase accumulator generates an accumulated phase based on the input frequency control word, and phase_offset is used to adjust the phase offset value. The phase-amplitude mapper performs a lookup table mapping based on the accumulated phase input and outputs the corresponding amplitude value. There are some limitations in the design of the phase-amplitude mapper of this traditional NCO:

[0004] First, there is a contradiction between accuracy and resources. The depth of the sine and cosine lookup tables in the phase-amplitude mapper increases exponentially with the increase of the phase bit width. If the upper 20 bits of the phase are taken as the valid bits and the quantization bit width is 16 bits, the scale of the lookup table will reach 2 20 ·2 16 bit, which will consume huge hardware resources;

[0005] Second, in high-rate application scenarios, the processing speed of a single-channel phase-amplitude mapper may not meet the requirements;

[0006] Third, the NCO phase-amplitude mapper usually truncates the lower bits of the phase output by the phase accumulator and retains the higher bits to be sent to the phase-amplitude mapper for lookup table mapping. Since the output of the phase accumulator is periodic, the error generated by truncation is also periodic, which will be manifested as spurs at specific frequencies in the characteristic spectrum of the output waveform. Summary of the Invention

[0007] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, providing a high-precision NCO digital circuit based on lookup table depth optimization and multi-channel parallelism, solving the problem of too large a scale of the lookup table when a high-precision NCO uses a lookup table to achieve phase-amplitude mapping, and the multi-channel parallel structure and phase jitter injection greatly improve the operating frequency and output accuracy of the NCO digital circuit.

[0008] The object of the present invention is achieved by the following technical solutions: A high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism, comprising: a phase accumulator and M phase-amplitude mappers; wherein, the phase accumulator receives the system clock sysclk, the low N-m bits X of the N-bit frequency control word X <n-m-1:0>and the phase offset value phase_offset <w-1:0>, according to the system clock sysclk and the lower N - m bits X of the N - bit frequency control word X <n-m-1:0>and the phase offset value phase_offset <w-1:0>Output the output value Y of the H-bit phase accumulator <h-1:0>; The structures of the M amplitude-phase mappers are the same. Among them, the input of the i-th amplitude-phase mapper is the input value Q of the i-th amplitude-phase mapper i from the (P - 1)-th bit to the 0-th bit of Q i <p-1:0>, the output is SIN i _2π <i:0>and COS i _2π <i:0>; where i = 0, 1, …… M - 1, and M = 2 m , SIN i _2π <i:0>is the I-th bit to the 0-th bit of the first output signal of the i-th phase amplitude mapper, COS i _2π <i:0>is the I-th bit to the 0-th bit of the second output signal of the i-th phase amplitude mapper, Q i <p-1:0>For Y <h-1:0>With i·X <n-1:n-h>The high P bits of the sum, where M, N, m, H, P, and I are all positive integers, and N - m ≥ H ≥ P.

[0009] In the above high-precision NCO digital circuit with lookup table depth optimization and multi-way parallelism, the phase accumulator includes DFF flip-flops; among them, the DFF flip-flops, at the rising edge of the system clock sysclk, transfer the low N - m bits X of the N-bit frequency control word X at the data input end (i.e., the D end) of the DFF flip-flops. <n-m-1:0>It is sent to the master output terminal, i.e., the Q terminal, of the DFF flip-flop and held for one clock cycle until the rising edge of the next system clock sysclk. The input of the D terminal of the DFF flip-flop is the output of the Q terminal and X <n-m-1:0>The sum will naturally overflow when the output value at the Q terminal exceeds the maximum modulus value 2 of the N-m bit data. N-m -1.

[0010] In the above high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism, the phase offset value phase_offset of the high H bits output at the Q terminal and the W bits input <w-1:0>Add after high alignment to obtain the output value Y of the H-bit phase accumulator after phase offset <h-1:0>。

[0011] In the above high-precision NCO digital circuit based on lookup table depth optimization and multi-path parallelism, the phase-amplitude mapper includes a phase symmetry circuit, a dither injection circuit, a high-order lookup table circuit, a low-order Taylor interpolation circuit, and an octant mapping circuit; among them, the input of the phase symmetry circuit is Q i <p-3:0>, the output of the phase symmetry circuit is Q i _inv <p-3:0>; where Q i <p-3:0>Q is the input value for the i-th phase amplitude mapper i from bit P - 3 to bit 0 of, Q i _inv <p-3:0>is the output value Q of the phase-symmetric circuit i bits P-3 to 0 of _inv; the input of the dither injection circuit is Q i _inv <p-3-k:0>, the output of the jitter injection circuit is a single-bit pseudo-random signal jitter; where Q i _inv <p-3-k:0>The output value Q of the phase-symmetric circuit i Bits P - 3 - K to 0 of _inv; the input to the high-order lookup table circuit is K-bit Q i _J, and the output of the high-order lookup table circuit is S-bit sine output data SIN i _H <s-1:0>and cosine output data COS i _H <s-1:0>; The input of the low-order Taylor interpolation circuit is SIN i _H <s-1:0>, COS i _H <s-1:0>and Q i _inv <p-3-k:0>, the output of the low-order Taylor interpolation circuit is an (I + 1)-bit SIN i _π / 4 <i:0>and COS i _π / 4 <i:0>; where SIN i _π / 4 <i:0>is the sine output data of the low-order Taylor interpolation circuit, COS i _π / 4 <i:0>is the cosine output data of the low-order Taylor interpolation circuit; the input of the octant mapping circuit is SIN i _π / 4 <i:0>, COS i _π / 4 <i:0>and Q i <p-1:p-3>, the output of the octant mapping circuit is SIN of I + 1 bits i _2π <i:0>and COS i _2π <i:0>; where K, W, and S are all positive integers, N - m ≥ H ≥ P ≥ K + 3, W ≤ H, K ≥ 1 and S ≥ I, Q i <p-1:p-3>is the input value Q of the i-th phase amplitude mapper i from bit P - 1 to bit P - 3, SIN i _2π <i:0>is the sine output data of the octant circle mapping circuit, COS i _2π <i:0>It is the cosine output data of the octant circle mapping circuit.

[0012] In the above high-precision NCO digital circuit with optimized lookup table depth and multi-channel parallelism, when Q i <p-3>When it is 1, Q i _inv <p-3:0> ＝2 P-3 -Q i <p-4:0>; When Q i <p-3>When it is 0, Q i _inv <p-3:0>= {1’b0, Q i <p-4:0>}; where 1'b0 is a 1-bit binary number 0, and {} is a concatenation operator.

[0013] In the above high-precision NCO digital circuit with optimized lookup table depth and multi-way parallelism, when P - 2 - K is odd, if Q i _inv <p-3-k:0>Among the P - 2 - K bits, if the number of bits with value 1 is greater than or equal to (P - 1 - K) / 2, let jitter = 1, otherwise jitter = 0; when P - 2 - K is even, if Q i _inv <p-3-k:1>Among the P - 3 - K bits, if the number of 1s is greater than or equal to (P - 2 - K) / 2, let jitter = 1; otherwise, jitter = 0. At this time, jitter can be regarded as a pseudo - random signal. Combine jitter with the high K bits of Q i _inv i _inv <p-3:p-2-k>Add them, and use the result as the input Q of the high - order lookup - table circuit i _J

[0014] In the above - mentioned high - precision NCO digital circuit with optimized lookup - table depth and multi - path parallelism, SIN i _H <s-1:0>=ROUND(sin(Q i _J <p-3:p-2-k>×2 P-2-K / 2 P-3 ×π / 4)×2 S );COS i _H <s-1:0>=ROUND(cos(Q i _J <p-3:p-2-k>×2 P-2-K / 2 P-3 ×π / 4)×(2 S -1)); ROUND is the rounding function.

[0015] In the above high-precision NCO digital circuit with optimized lookup table depth and multi-way parallelism, SIN i _π / 4 <i:0>={1’b0, SIN i <s-1:s-i>}; COS i _π / 4 <i:0>= {1’b0, COS i <s-1:s-i>}}; Among them, COS i = COS i _L + COS i _H <s-1:0>; SIN i = SIN i _L + SIN i _H <s-1:0>; SIN i _L = COS i _H <s-1:0>·(Q i _J <p-3-k:0> / 2 P-3 ×π / 4); COS i _L = SIN i _H <s-1:0>·(Q i _J <p-3-k:0> / 2 P-3 ×π / 4).

[0016] In the above high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism, COS i _2π <i:0> ＝(Q i <p-1> ^Q i <p-2>)? (-COS i _π): COS i _π; COS i _π=(Q i <p-3> ^Q i <p-2>)? SIN i _π / 4 <i:0>:COS i _π / 4 <i:0>。

[0017] In the above high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism, SIN i _2π <i:0> ＝(Q i <p-1>)? (-SIN i _π):SIN i _π;SIN i _π=(Q i <p-3> ^Q i <p-2>)? COS i _π / 4 <i:0>:SIN i _π / 4 <i:0>。

[0018] The present invention has the following beneficial effects compared with the prior art:

[0019] The present invention solves the problem of the too large scale of the look-up table when the high-precision NCO realizes the phase-amplitude mapping by using the look-up table. The multi-path parallel structure and the phase jitter injection greatly improve the working frequency and the output precision of the NCO digital circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0021] Figure 1 is a schematic diagram of a high-precision NCO digital circuit based on look-up table depth optimization and multi-path parallel provided by an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of the phase accumulator circuit provided by an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of the phase-amplitude mapper provided by an embodiment of the present invention;

[0024] Figure 4 is an input-output waveform diagram of the phase symmetry circuit in the phase-amplitude mapper provided by an embodiment of the present invention;

[0025] Figure 5 is an input-output waveform diagram of the octant mapping circuit in the phase-amplitude mapper provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Hereinafter, the exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Hereinafter, the present invention will be described in detail with reference to the drawings and in conjunction with the embodiments.

[0027] Figure 1 is a schematic diagram of a high-precision NCO digital circuit based on look-up table depth optimization and multi-path parallel provided by an embodiment of the present invention. As Figure 1 As shown, the high-precision NCO digital circuit based on lookup table depth optimization and multi-channel parallelism includes: a phase accumulator and M phase-amplitude mappers; among them, the phase accumulator receives the system clock sysclk and the low N-m bits X of the N-bit frequency control word X <n-m-1:0>and phase offset value phase_offset <w-1:0>, according to the system clock sysclk and the lower N-m bits X of the N-bit frequency control word X <n-m-1:0>and the phase offset value phase_offset <w-1:0>Output the output value Y of the H-bit phase accumulator <h-1:0>; The structures of the M amplitude-phase mappers are the same. Among them, the input of the i-th amplitude-phase mapper is the input value Q of the i-th amplitude-phase mapper i from the (P - 1)-th bit to the 0-th bit of Q i <p-1:0>, the output is SIN i _2π <i:0>and COS i _2π <i:0>; where \(i = 0, 1,\cdots,M - 1\) and \(M = 2\) m , SIN i _2π <i:0>are the I-th to 0-th bits of the first output signal of the i-th phase amplitude mapper, COS i _2π <i:0>is the I-th bit to the 0-th bit of the second output signal of the i-th phase mapper, Q i <p-1:0>Is Y <h-1:0>With i·X <n-1:n-h>The high P bits of the sum, where M, N, m, H, P, and I are all positive integers, and N - m ≥ H ≥ P.

[0028] The phase accumulator inputs are the system clock sysclk and the frequency control word X <n-m-1:0>and phase offset value phase_offset <w-1:0>, the output is Y <h-1:0>; where H is the total number of bits of the output Y of the phase accumulator, N is the total number of bits of the frequency control word X, W is the total number of bits of the phase offset value phase_offset, and the value of m is related to the parallel design number M of the phase-amplitude mapper, M = 2 m ; X <n-m-1:0>is the lower N - m bits of the N - bit frequency control word X;

[0029] The phase - amplitude mapper adopts an M - way parallel design. There are M phase - amplitude mappers corresponding to M channels. The input of the phase - amplitude mapper in channel i is Q i <p-1:0>, the output is SIN i _2π <i:0>and COS i _2π <i:0>, the structure of the amplitude-phase mapper in each path is the same, Q i <p-1:0>Is Y <h-1:0>With i·X <n-1:n-h>The high P bits of the sum, Y <h-1:0>is the output signal of the phase accumulator, X <n-1:n-h>is the (N - 1)th to (N - H)th bit of the frequency control word X, i represents the i-th channel, SIN i _2π <i:0>, COS i _2π <i:0>They are respectively the I-th to 0-th bits of the two groups of output signals SIN i _2π and COS i _2π in path i, and the total number of bits of SIN i _2π and COS i _2π is I + 1; where M = 2 m , and the values of i are successively 0, 1,..., M - 1; "successively" is used to distinguish similar objects, rather than to describe or represent a specific order or sequence.

[0030] As Figure 2 shown, the phase accumulator includes DFF flip-flops; where the DFF flip-flops, at the rising edge of the system clock sysclk, transfer the low N - m bits X <n-m-1:0>Sent to the master output terminal Q of the DFF flip-flop and held for one clock cycle until the rising edge of the next system clock sysclk. The input of the D terminal of the DFF flip-flop is the output of the Q terminal and X <n-m-1:0>When the sum exceeds the maximum modulus value of 2 for N - m bit data, it will naturally overflow when the output value at the Q terminal exceeds 2 N-m -1. The phase offset value phase_offset of the high H bits output at the Q terminal and the W bits input <w-1:0>After high-bit alignment and addition, the output value Y of the H-bit phase accumulator after phase offset is obtained <h-1:0>。

[0031] The input of the phase accumulator is the system clock sysclk and the low N-m bits X of the frequency control word X <n-m-1:0>and the phase_offset of the W bit <w-1:0>, the output is Y with H bits <h-1:0>; The DFF flip-flop in the phase accumulator will send the N-m bit data at its data input end, i.e., the D end, to the main output end, i.e., the Q end, at the rising edge of the system clock sysclk, and hold it for one clock cycle until the next rising edge of sysclk. The input of the D end of the DFF flip-flop is the output of its Q end and X <n-m-1:0>When the sum exceeds the maximum modulus value of 2 of the N - m bit data, it will naturally overflow when the output value at the Q terminal exceeds 2 N-m -1; The high H bits output at the Q terminal and the phase_offset of the W bits input <w-1:0>Add after high alignment to obtain Y after phase shift <h-1:0>。

[0032] The phase amplitude mapper includes a phase symmetry circuit, a dither injection circuit, a high-order look-up table circuit, a low-order Taylor interpolation circuit, and an octant mapping circuit; among them, the input of the phase symmetry circuit is Q i <p-3:0>, the output of the phase-symmetric circuit is Q i _inv <p-3:0>; where Q i <p-3:0>Q is the input value for the i-th phase mapper i from bit P - 3 to bit 0 of, Q i _inv <p-3:0>The output value Q of the phase-symmetric circuit i Bits P - 3 to 0 of _inv; when Q i <p-3>When it is 1, Q i _inv <p-3:0> ＝2 P-3 -Q i <p-4:0>; When Q i <p-3>When it is 0, Q i _inv <p-3:0>= {1’b0, Q i <p-4:0>}; where 1’b0 is a 1-bit binary number 0, and {} is a concatenation operator.

[0033] The input of the dither injection circuit is Q i _inv <p-3-k:0>, the output of the jitter injection circuit is a single-bit pseudo-random signal jitter; where Q i _inv <p-3-k:0>is the output value Q of the phase-symmetric circuit i from the (P - 3 - K)-th bit to the 0-th bit of _inv; when P - 2 - K is odd, if Q i _inv <p-3-k:0>Among the P - 2 - K bits, if the number of bits with value 1 is greater than or equal to (P - 1 - K) / 2, let jitter = 1; otherwise, jitter = 0. When P - 2 - K is even, if Q i _inv <p-3-k:1>Among the P - 3 - K bits, if the number of bits that are 1 is greater than or equal to (P - 2 - K) / 2, let jitter = 1; otherwise, jitter = 0. At this time, jitter can be regarded as a pseudo - random signal. Combine jitter with the high K bits of Q i _inv i _inv <p-3:p-2-k>Add them together, and use the result as the input Q to the high-order lookup table circuit i _J。

[0034] The input to the high-order lookup table circuit is Q with K bits i _J, and the output of the high-order lookup table circuit is the S-bit sine output data SIN i _H <s-1:0>and cosine output data COS i _H <s-1:0>; SIN i _H <s-1:0>=ROUND(sin(Q i _J <p-3:p-2-k>×2 P-2-K / 2 P-3 ×π / 4)×2 S );COS i _H <s-1:0>=ROUND(cos(Q i _J <p-3:p-2-k>×2 P-2-K / 2 P-3 ×π / 4)×(2 S -1)); ROUND is the rounding function.

[0035] The input of the low-order Taylor interpolation circuit is SIN i _H <s-1:0>, COS i _H <s-1:0>and Q i _inv <p-3-k:0>, the output of the low-order Taylor interpolation circuit is SIN with I + 1 bits i _π / 4 <i:0>and COS i _π / 4 <i:0>; where SIN i _π / 4 <i:0>is the sine output data of the low-order Taylor interpolation circuit, COS i _π / 4 <i:0>is the cosine output data of the low-order Taylor interpolation circuit; SIN i _π / 4 <i:0>= {1’b0, SIN i <s-1:s-i>}; COS i _π / 4 <i:0>= {1’b0, COS i <s-1:s-i>}}; Among them, COS i , SIN i have a total number of digits of S, and SIN i <s-1:s-i>, COS i <s-1:s-i>They are SIN respectively i and COS i from the (S - 1)-th bit to the S-I-th bit, that is, the high I bits; COS i = COS i _L + COS i _H <s-1:0>; SIN i = SIN i _L + SIN i _H <s-1:0>; SIN i _L = COS i _H <s-1:0>·(Q i _J <p-3-k:0> / 2 P-3 ×π / 4); COS i _L = SIN i _H <s-1:0>·(Q i _J <p-3-k:0> / 2 P-3 ×π / 4).

[0036] The input of the octant mapping circuit is SIN i _π / 4 <i:0>, COS i _π / 4 <i:0>and Q i <p-1:p-3>, the output of the octant mapping circuit is SIN with I + 1 bits i _2π <i:0>and COS i _2π <i:0>; where K, W, and S are all positive integers, N - m ≥ H ≥ P ≥ K + 3, W ≤ H, K ≥ 1, and S ≥ I, Q i <p-1:p-3>Q is the input value for the i-th phase amplitude mapper i from bit P - 1 to bit P - 3, SIN i _2π <i:0>is the sine output data of the octant mapping circuit, COS i _2π <i:0>is the cosine output data of the octant circle mapping circuit. Among them, COS i _2π <i:0> ＝(Q i <p-1> ^Q i <p-2>)? (-COS i _π): COS i _π; COS i _π = (Q i <p-3> ^Q i <p-2>)? SIN i _π / 4 <i:0>:COS i _π / 4 <i:0>。SIN i _2π <i:0> ＝(Q i <p-1>)? (-SIN i _π):SIN i _π;SIN i _π=(Q i <p-3> ^Q i <p-2>)? COS i _π / 4 <i:0>:SIN i _π / 4 <i:0>。

[0037] The input of the phase-symmetric circuit is Q i <p-3:0>, the output is Q i _inv <p-3:0>; When Q i <p-3>When it is 1, Q i _inv = 2 P-3 -Q i <p-4:0>, when Q i <p-3>When it is 0, Q i _inv = {1’b0, Q i <p-4:0>}, Q i _inv is the phase-symmetric output, which is a P - 2 bit binary number; among them, Q i <p-3:0>For the P-bit input signal Q of the phase-amplitude mapper in path i i <p-1:0>from the (P-3)-th bit to the 0-th bit, Q i _inv <p-3:0>The output signal Q of the phase-symmetric circuit in path i i From the (P - 3)-th bit to the 0-th bit of _inv.

[0038] The input of the jitter injection circuit is Q i _inv <p-3-k:0>, the output is a single-bit pseudo-random signal jitter; when P - 2 - K is odd, if Q i _inv <p-3-k:0>Among the P - 2 - K bits, if the number of bits with value 1 is greater than or equal to (P - 1 - K) / 2, let jitter = 1; otherwise, jitter = 0. When P - 2 - K is even, if Q i _inv <p-3-k:1>Among the P - 3 - K bits, if the number of bits that are 1 is greater than or equal to (P - 2 - K) / 2, let jitter = 1; otherwise, jitter = 0. At this time, jitter can be regarded as a pseudo - random signal. Combine jitter with the high K bits of Q i _inv i _inv <p-3:p-2-k>Add them together, and use the result as the input Q to the high-order lookup table i _J; where Q i _inv <p-3-k:0>For the output signal Q of the phase-symmetric circuit in path i i From the (P - 3 - K)-th bit to the 0-th bit of _inv, where K is the number of bits at the input of the high-order lookup table.

[0039] The input of the high-order lookup table circuit is Q with K bits i _J, and the output is the S-bit sine-cosine output SIN i _H <s-1:0>and COS i _H <s-1:0>; The mapping relationship between the input and output is: SIN i _H <s-1:0>=ROUND(sin(Q i _J <p-3:p-2-k>×2 P-2-K / 2 P-3 ×π / 4)×2 S ),COS i _H <s-1:0>=ROUND(cos(Q i _J <p-3:p-2-k>×2 P-2-K / 2 P-3 ×π / 4)×(2 S -1)), ROUND is the rounding function; where, Q i _J is Q i the high K bits of Q i _inv <p-3:p-2-k>The sum with the pseudo-random signal jitter, SIN i _H <s-1:0>, COS i _H <s-1:0>The two groups of output signals of the high - order lookup table circuit in path i are SIN i _H and COS i from the (S - 1)-th bit to the 0-th bit of _H, where S is the total number of bits of SIN i _H and COS i _H

[0040] The input of the low - order Taylor interpolation is SIN i _H <s-1:0>, COS i _H <s-1:0>and Q i _inv <p-3-k:0>, the output is an (I + 1)-bit SIN i _π / 4 <i:0>and COS i _π / 4 <i:0>; Denote SIN i _L = COS i _H · (Q i _J <p-3-k:0> / 2 P-3 ×π / 4); Denote COS i _L = SIN i _H·(Q i _J <p-3-k:0> / 2 P-3 × π / 4); Denote COS i = COS i _L + COS i _H, Denote SIN i = SIN i _L + SIN i _H, then SIN i _π / 4 <i:0>={1’b0, SIN i <s-1:s-i>}, COS i _π / 4 <i:0>= {1’b0, COS i <s-1:s-i>}}; Among them, SIN i _π / 4 <i:0>, COS i _π / 4 <i:0>For the two sets of output signals SIN i _π / 4 and COS i from the I-th bit to the 0-th bit of _π / 4 in path i, SIN i _π / 4 and COS i _π / 4 have a total number of bits of I + 1.

[0041] The input of the octant mapping is SIN i _π / 4 <i:0>, COS i _π / 4 <i:0>and Q i <p-1:p-3>; The output is an (I + 1)-bit SIN i _2π and COS i _2π; Denote the half-cycle sine output SIN i _π = (Q i <p-3> ^Q i <p-2>)? COS i _π / 4: SIN i _π / 4, record the half-cycle cosine output COS i _π = (Q i <p-3> ^Q i <p-2>)? SIN i _π / 4:COS i _π / 4; then the cosine output COS for a full period i _2π <i:0> ＝(Q i <p-1> ^Q i <p-2>)? (-COS i _π): COS i _π; full-cycle sine output SIN i _2π <i:0> ＝(Q i <p-1>)?(-SIN i _π):SIN i _π。

[0042] N - m ≥ H ≥ P ≥ K + 3, W ≤ H, K ≥ 1, S ≥ I and N, m, H, P, K, W, S, I are all positive integers.

[0043] This embodiment is based on a high - precision NCO digital circuit with lookup - table depth optimization and multi - path parallelism. Its phase - amplitude mapper realizes phase - amplitude mapping by using the method of lookup table, and uses three parts of circuits, namely high - order lookup table, low - order Taylor interpolation, and octant mapping, to deeply optimize the size of the lookup table. The method of dither injection is used to inject random dither into the periodic phase during high - order table lookup to optimize the spurs of the output waveform of the phase - amplitude mapper. In addition, the phase - amplitude mapper uses a multi - path parallel structure to improve the throughput of the circuit; during the specific implementation of the present invention, the selection of parameter values will affect the implementation effect. For example, the required range of parameter K is P - 3 ≥ K ≥ 1. The larger the value of K, the greater the mapping accuracy of the low - order Taylor interpolation circuit, but the scale of the high - order lookup table will also increase exponentially; this embodiment will give reference values of the parameters involved in a high - precision NCO digital circuit: N = 48, M = 4, m = 2, W = 16, H = 32, P = 20, S = 18, I = 15, K = 7.

[0044] As Figure 1 shown is the schematic diagram of the high - precision NCO digital circuit based on lookup - table depth optimization and multi - path parallelism of the present invention. It can be seen from the figure that the high - precision NCO digital circuit based on lookup - table depth optimization and multi - path parallelism includes two parts: a phase accumulator and a phase - amplitude mapper. The input of the phase accumulator is the system clock sysclk, the lower 46 bits X<45:0> of the frequency control word X, and 16 - bit phase_offset<15:0>, and the output is 32 - bit Y<31:0>; the phase - amplitude mapper adopts a 4 - path parallel design, and the 4 paths correspond to 4 phase - amplitude mappers. The input of the phase - amplitude mapper in path i is the high 20 bits Q i <19:0> of the sum of Y<31:0> and i·X<47:16>, and the output is SIN i _2π<15:0> and COS i _2π<15:0>. The structure of the phase - amplitude mapper in each path is the same, where the values of i are 0, 1, 2, 3 in sequence; "in sequence" is used to distinguish similar objects, rather than to describe or represent a specific order or sequence.

[0045] As Figure 2 The schematic diagram of the phase accumulator circuit in the high-precision NCO digital circuit based on lookup table depth optimization and multi-channel parallelism of the present invention is shown. The inputs of the phase accumulator are the system clock sysclk, the lower 46 bits X<45:0> of the frequency control word X, and the 16-bit phase_offset<15:0>, and the output is the 32-bit Y<31:0>. The DFF flip-flop in the phase accumulator will send the 46-bit data input at the D end to the output Q end at the rising edge of the system clock sysclk and hold it for one clock cycle until the next rising edge of sysclk. The input at the D end of the DFF flip-flop is the sum of its Q-end output and X<45:0>. When the output value at the Q end exceeds the maximum modulus value 2 46 of the 46-bit data by -1, it will naturally overflow. The high 32 bits of the Q-end output are added after being aligned with the high bits of the input 16-bit phase_offset<15:0> to obtain the phase-offset-adjusted Y<31:0>.

[0046] As Figure 3 shown, the schematic diagram of the phase-amplitude mapper circuit in the high-precision NCO digital circuit based on lookup table depth optimization and multi-channel parallelism of the present invention is composed of five parts: a phase symmetry circuit, a dither injection circuit, a high-order lookup table circuit, a low-order Taylor interpolation circuit, and an octant mapping circuit.

[0047] As Figure 4 shown, the input-output waveform diagram of the phase symmetry circuit in the phase-amplitude mapper of the present invention is shown. The input of the phase symmetry circuit is Q i <17:0>, and the output is Q i _inv<17:0>. Q i <17> will alternate between 0 and 1 as the phase accumulates. The minimum value of Q i <16:0> is 0, and the maximum value is 2 17 -1. When Q i <17> is 1, Q i _inv = 2 17 - Q i <16:0>. When Q i <17> is 0, Q i _inv = Q i <16:0>. Q i _inv is the phase symmetry output, which is an 18-bit binary number. The minimum value of Q i _inv is 0, and the maximum value is 2 17 .

[0048] The input of the dither injection circuit is Q i _inv<10:0>, and the output is a single-bit pseudo-random signal jitter. If Q i If the number of bits equal to 1 in the 11 bits of _inv<10:0> is greater than or equal to 6, let jitter = 1; otherwise, jitter = 0. At this time, jitter can be regarded as a pseudo-random signal, and it is added to Q i The high 7 bits of _inv, Q i _inv<17:11>, and the result is used as the input Q of the high-order lookup table i _J.

[0049] The input of the high-order lookup table circuit is 7-bit Q i _J, and the output is 18-bit sine and cosine outputs SIN i _H and COS i _H; the mapping relationship between the input and output is: SIN i _H<17:0> = ROUND(sin(Q i _J<17:11> × 2 11 / 2 17 × π / 4) × 2 18 ), COS i _H<17:0> = ROUND(cos(Q i _J<17:11> × 2 11 / 2 17 × π / 4) × (2 18 -1)), ROUND is the rounding function.

[0050] The input of the low-order Taylor interpolation is SIN i _H, COS i _H and Q i _inv<10:0>, and the output is 16-bit SIN i _π / 4 and COS i _π / 4; denote SIN i _L = ROUND(COS i _H · (Q i _J<10:0> / 2 17 × π / 4)); denote COS i _L = ROUND(SIN i _H · (Q i _J<10:0> / 2 17 × π / 4)); denote COS i = COS i _L + COS i _H, denote SIN i = SIN i _L + SIN i _H, then SIN i _π / 4<15:0> = {1’b0, SIN i <17:3>}, COS i _π / 4 <15:0> = {1’b0, COS i <17:3>}, ROUND is the rounding function.

[0051] As Figure 5 shown is the input-output waveform diagram of the octant mapping circuit in the phase-amplitude mapper of the present invention. The input of the octant mapping is SIN i _π / 4, COS i _π / 4 and Q i <19:17>; the output is the 16-bit SIN i _2π and COS i _2π; denote the half-period sine output SIN i _π = (Q i <17> ^ Q i <18>)? COS i _π / 4 : SIN i _π / 4, denote the half-period cosine output COS i _π = (Q i <17> ^ Q i <18>)? SIN i _π / 4 : COS i _π / 4; then the full-period cosine output COS i _2π <15:0> = (Q i <19> ^ Q i <18>)? (-COS i _π) : COS i _π; the full-period sine output SIN i _2π <15:0> = Q i <19>? (-SIN i _π) : SIN i _π. It should be understood that "……? …… : ……” is a ternary conditional operator, and its expression form is: <conditional expression>? <expression 1> : <expression 2>. When the conditional expression is 1, expression 1 is executed; when the conditional expression is 0, expression 2 is executed. Therefore, for the formula A = B? C1 : C2, when B is 1, A = C1; when B is 0, A = C2.

[0052] In this embodiment, the high-order lookup table, low-order Taylor interpolation, and octant algorithm are used to deeply optimize the size of the lookup table in the phase-amplitude mapper; assuming that the sine and cosine lookup tables in the traditional NCO phase-amplitude mapper perform table lookup mapping on the P-bit phase, the depth of the lookup table is 2 P By using the octant algorithm, the scale of the lookup table can be reduced to 2 P-3 , the high K bits of the phase are looked up through the high bit lookup table, and the size of the lookup table becomes 2 P-3-K The low-order phase is Taylor interpolated, and after multiplication and addition with the output of the high-order lookup table, the phase-amplitude mapping output of the complete phase can be obtained. Compared with the traditional NCO lookup table, the depth is reduced to 2 K+3 One percent.

[0053] This embodiment uses multiple parallel phase-amplitude mappers to double the original circuit, exchanging resources and area for throughput. There are M phase-amplitude mappers in M ​​paths, and the circuit throughput is increased by M times compared with the traditional NCO, and the requirement for the circuit operation speed is reduced by M times.

[0054] This embodiment uses jitter injection technology in the phase-amplitude mapper to generate a pseudo-random signal jitter in a clever and simple way. The jitter is added to the high K bits of the phase and then a table lookup is performed to break up the periodicity of the truncation error, greatly reducing the spurious output waveform of the phase-amplitude mapper, and improving its spurious-free dynamic range by about 35dB.

[0055] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention. < / i:0> < / p-1> < / i:0> < / p-3> < / p-3> < / p-3> < / i:0> < / p-3> < / p-1> < / i:0> < / p-3:0> < / p-3> < / i:0> < / p-3> < / p-1> < / i:0> < / p-3:0>

Claims

1. A high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism, characterized in that Including: A phase accumulator and M phase-amplitude mappers; wherein, The phase accumulator receives the system clock sysclk and the low N - m bits X of the N - bit frequency control word X <n-m-1:0>and the phase offset value phase_offset <w-1:0>, according to the system clock sysclk and the lower N-m bits X of the N-bit frequency control word X <n-m-1:0>and phase offset value phase_offset <w-1:0>Output the output value Y of the H-bit phase accumulator <h-1:0> ；< / h-1:0> The structures of the M amplitude-phase mappers are the same. Among them, the input of the i-th amplitude-phase mapper is the input value Q of the i-th amplitude-phase mapper i from the (P - 1)-th bit to the 0-th bit of Q i <p-1:0>, the output is SIN i _2π <i:0>and COS i _2π <i:0>; where i = 0, 1, …… M - 1, and M = 2 m , SIN i _2π <i:0>is the \(I^{th}\) to \(0^{th}\) bit of the first output signal of the \(i^{th}\) phase amplitude mapper, COS i _2π <i:0>is the I-th bit to the 0-th bit of the second output signal of the i-th phase amplitude mapper, Q i <p-1:0>It is Y <h-1:0>With i·X <n-1:n-h>The high P bits of and, M, N, m, H, P, and I are all positive integers, and N - m ≥ H ≥ P. < / n-1:n-h> 2. The high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism according to claim 1, characterized in that: The phase accumulator includes DFF flip-flops; wherein, The DFF flip-flop transfers the low N-m bits X of the N-bit frequency control word X at the data input terminal, i.e., the D terminal, of the DFF flip-flop to the output terminal at the rising edge of the system clock sysclk. <n-m-1:0>Sent to the main output terminal of the DFF flip-flop, that is, the Q terminal, and held for one clock cycle until the rising edge of the next system clock sysclk. The input of the D terminal of the DFF flip-flop is the output of the Q terminal and X <n-m-1:0>When the sum, when the output value at the Q end exceeds the maximum modulus value 2 of the N - m bit data N-m - 1, it will overflow naturally.

3. The high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism according to claim 2, wherein: The phase offset value phase_offset of the high H bits output at the Q end and the W bits of the input <w-1:0>After high-alignment and addition, the output value Y of the H-bit phase accumulator after phase offset is obtained <h-1:0> 。< / h-1:0> 4. The high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism according to claim 1, characterized in that: The phase-amplitude mapper includes a phase symmetry circuit, a dither injection circuit, a high-order look-up table circuit, a low-order Taylor interpolation circuit, and an octant mapping circuit; wherein, The input of the phase symmetry circuit is Q i <p-3:0>, the output of the phase symmetry circuit is Q i _inv <p-3:0>; where Q i <p-3:0>The input value Q for the i-th phase amplitude mapper i from bit P - 3 to bit 0 of, Q i _inv <p-3:0>is the output value Q of the phase symmetric circuit i the bits from the (P - 3)-th bit to the 0-th bit of _inv; The input of the dither injection circuit is Q i _inv <p-3-k:0>, the output of the jitter injection circuit is a single-bit pseudo-random signal jitter; among them, Q i _inv <p-3-k:0>The output value Q of the phase-symmetric circuit i Bits from the (P - 3 - K)-th bit to the 0-th bit of _inv; The input of the high-order lookup table circuit is K-bit Q i _J, and the output of the high-order lookup table circuit is S-bit sine output data SIN i _H <s-1:0>and cosine output data COS i _H <s-1:0> ；< / s-1:0> The input of the low-order Taylor interpolation circuit is SIN i _H <s-1:0>, COS i _H <s-1:0>and Q i _inv <p-3-k:0>, the output of the low-order Taylor interpolation circuit is SIN with I + 1 bits i _π / 4 <i:0>and COS i _π / 4 <i:0>; where SIN i _π / 4 <i:0>is the sine output data of the low-order Taylor interpolation circuit, COS i _π / 4 <i:0>Is the cosine output data of the low-order Taylor interpolation circuit; < / i:0> The input of the octant circle mapping circuit is SIN i _π / 4 <i:0>, COS i _π / 4 <i:0>and Q i <p-1:p-3>, the output of the octant circle mapping circuit is SIN with I + 1 bits i _2π <i:0>and COS i _2π <i:0>; where K, W, and S are all positive integers, N - m ≥ H ≥ P ≥ K + 3, W ≤ H, K ≥ 1 and S ≥ I, Q i <p-1:p-3>Q is the input value for the i-th phase amplitude mapper i from bit P - 1 to bit P - 3, SIN i _2π <i:0>Is the sine output data of the octant circle mapping circuit, COS i _2π <i:0>Is the cosine output data of the octant mapping circuit. < / i:0> 5. The high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism according to claim 4, characterized in that: When Q i <p-3>When it is 1, Q i _inv <p-3:0> ＝2 P-3 -Q i <p-4:0>; When Q i <p-3>When it is 0, Q i _inv <p-3:0>={1’b0, Q i <p-4:0>}; wherein, 1’b0 is the 1-bit binary number 0, and {} is the concatenation operator. < / p-4:0> < / p-3:0> 6. The high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism according to claim 4, characterized in that: When P-2-K is odd, if Q i _inv <p-3-k:0>Among the P - 2 - K bits, if the number of 1s is greater than or equal to (P - 1 - K) / 2, let jitter = 1; otherwise, jitter = 0. When P - 2 - K is even, if Q i _inv <p-3-k:1>Among the P - 3 - K bits, if the number of 1s is greater than or equal to (P - 2 - K) / 2, let jitter = 1; otherwise, jitter = 0. At this time, jitter can be regarded as a pseudo - random signal. Combine jitter with the high K bits of Q i _inv i _inv <p-3:p-2-k>Add them together, and use the result as the input Q of the high-order lookup table circuit i _J 7. The high-precision NCO digital circuit based on look-up table depth optimization and multi-way parallelism according to claim 4, characterized in that: SIN i _H <s-1:0>=ROUND(sin(Q i _J <p-3:p-2-k> ×2 P-2-K / 2 P-3 ×π / 4)×2 S )；< / p-3:p-2-k> COS i _H <s-1:0>=ROUND(cos(Q i _J <p-3:p-2-k> ×2 P-2-K / 2 P-3 ×π / 4)×(2 S -1))；< / p-3:p-2-k> ROUND is the rounding function.

8. The high-precision NCO digital circuit based on lookup table depth optimization and multi-way parallelism according to claim 4, characterized in that: SIN i _π / 4 <i:0>= {1’b0, SIN i <s-1:s-i>}; COS i _π / 4 <i:0>= {1'b0, COS i <s-1:s-i>}; wherein, < / s-1:s-i> COS i = COS i _L + COS i _H <s-1:0> ；< / s-1:0> SIN i = SIN i _L + SIN i _H <s-1:0> ；< / s-1:0> SIN i _L = COS i _H <s-1:0>·(Q i _J <p-3-k:0> / 2 P-3 ×π / 4)；< / p-3-k:0> COS i _L = SIN i _H <s-1:0>·(Q i _J <p-3-k:0> / 2 P-3 ×π / 4)。< / p-3-k:0> 9. The high-precision NCO digital circuit based on look-up table depth optimization and multi-way parallelism according to claim 4, characterized in that: COS i _2π <i:0> ＝(Q i <p-1> ^Q i <p-2>)? (-COS i _π): COS i _π; < / p-1> < / i:0> COS i _π=(Q i <p-3> ^Q i <p-2>)?SIN i _π / 4 <i:0>:COS i _π / 4 <i:0> 。< / i:0> < / p-3> 10. The high-precision NCO digital circuit based on look-up table depth optimization and multi-way parallelism according to claim 4, characterized in that: SIN i _2π <i:0> ＝(Q i <p-1>)? (-SIN i _π):SIN i _π; < / i:0> SIN i _π=(Q i <p-3> ^Q i <p-2>)? COS i _π / 4 <i:0>:SIN i _π / 4 <i:0> 。< / i:0> < / p-3>

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