Constant transconductance bias negative resistance compensation continuous time Sigma-Delta modulator

Abstract

The invention provides a continuous time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation. The continuous time Sigma-Delta modulator comprises a loop filter, a quantizer and a digital-to-analog converter, the loop filter is used for amplifying a signal in an effective signal bandwidth and attenuating an out-of-band signal at the same time, and the loop filter comprises a first-stage negative resistance compensation integrator and a second-stage negative resistance compensation integrator which are connected in sequence, the first-stage negative resistance compensation integrator comprises a first negative resistance unit containing a negative resistance of a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, and a single operational amplifier resonator structure is formed to generate a second-order response; the integrator of the second-stage negative resistance compensation comprises a second negative resistance unit and a second integrator unit comprising an operational amplifier; and the quantizer is connected with the loop filter, adopts a successive approximation analog-to-digital converter, and is used for converting the analog voltage signal into a digital signal and outputting the digital signal. And the digital-to-analog converter is used for converting the digital signal into an analog signal and feeding back the analog signal to the loop filter.

Description

Technical Field

[0001] The present disclosure relates to the technical field of circuit design, and particularly to a continuous-time Sigma-Delta modulator with constant transconductance biasing and negative resistance compensation. Background Art

[0002] With the growth of the demand for portable audio devices and Internet of Things (IoT) devices, how to reduce power consumption while ensuring high-precision signal acquisition has become a key challenge in design. In portable audio applications, such as Bluetooth headsets and smart speakers, the devices need to run for a long time and provide a high-quality audio experience; while in IoT applications, the devices are usually powered by batteries, requiring accurate data acquisition while consuming low power. To meet these requirements, continuous-time Sigma-Delta analog-to-digital converters have become an ideal solution due to their advantages such as low power consumption, high precision, excellent noise suppression ability, and high linearity. Their continuous-time architecture can efficiently implement signal sampling and conversion, while avoiding the power consumption and noise problems brought by traditional sampling structures, and is suitable for promoting portable audio and IoT devices to higher precision and longer battery life.

[0003] A continuous-time Sigma-Delta analog-to-digital converter consists of a continuous-time Sigma-Delta modulator and a digital decimation filter. The continuous-time Sigma-Delta modulator is responsible for modulating quantization noise to high frequencies, which directly determines the linearity and noise performance of the analog-to-digital converter. Therefore, in order to achieve high-precision conversion, the design of the modulator is crucial for the performance of the entire system. The performance of the modulator is mainly determined by the loop filter. The loop filter processes continuous-time signals and provides the necessary filtering effect to ensure the accuracy and noise performance of the system.

[0004] The loop filter usually consists of multiple integrators and accounts for a large proportion of the power consumption in the entire continuous-time Delta-Sigma modulator. To ensure that the system has sufficient accuracy, the integrators in the loop filter need to rely on operational amplifiers with high gain, high bandwidth, and high linearity. However, these requirements usually lead to a significant increase in the power consumption of the operational amplifiers. Therefore, how to reduce the power consumption of the operational amplifiers in the integrators while ensuring high precision and good noise performance remains a technical problem to be solved urgently. Summary of the Invention

[0005] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a continuous-time Sigma-Delta modulator with constant transconductance biasing and negative resistance compensation.

[0006] To achieve the above object, the technical solution of the present disclosure is as follows:

[0007] According to an embodiment of the present disclosure, a continuous-time Sigma-Delta modulator with constant transconductance bias for negative resistance compensation is provided, including: a loop filter for amplifying signals within the effective signal bandwidth while attenuating out-of-band signals. The loop filter includes a first-stage integrator with negative resistance compensation and a second-stage integrator with negative resistance compensation connected in sequence. Among them, the first-stage integrator with negative resistance compensation includes a first negative resistance unit with a negative resistance containing a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, forming a single-op amp resonator structure to generate a second-order response; the second-stage integrator with negative resistance compensation includes a second negative resistance unit and a second integrator unit containing an operational amplifier; a quantizer connected to the loop filter, using a successive approximation analog-to-digital converter, for converting an analog voltage signal into a digital signal and outputting; and a digital-to-analog converter, including a first resistive digital-to-analog converter and a second resistive digital-to-analog converter. Among them, the first resistive digital-to-analog converter is connected to the input terminal of the operational amplifier in the first integrator unit and connected to the output terminal of the quantizer through a data weighted averaging module to achieve first-stage feedback, and the second resistive digital-to-analog converter is connected to the output terminal of the quantizer and the input terminal of the operational amplifier in the second integrator unit to achieve second-stage feedback.

[0008] The continuous-time Sigma-Delta modulator with constant transconductance bias for negative resistance compensation proposed by the present disclosure introduces a negative resistance unit inside the integrator. The negative resistance compensation effectively reduces the non-ideal effects of the operational amplifier and reduces the strict requirements for the design of the operational amplifier. The negative resistance is provided by a constant transconductance bias circuit, ensuring high matching, low current, and low noise. The first-stage integrator adopts a single-op amp resonator structure to generate a second-order response, so that the entire loop filter can be realized with only two operational amplifiers. The quantizer uses a successive approximation analog-to-digital converter, and only one comparator is required to achieve multi-bit quantization, and direct feedback is achieved through a capacitor array inside the quantizer, avoiding additional feedback digital-to-analog converters and adders. This design significantly reduces power consumption while ensuring high precision, improving the energy efficiency of the system. This circuit can be applied to portable audio devices and Internet of Things devices to provide low-power and high-precision data conversion. Description of the Drawings

[0009] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0010] Figure 1 It is a schematic diagram of the composition of a continuous-time Sigma-Delta modulator.

[0011] Figure 2 It is a third-order continuous-time Sigma-Delta modulator with negative resistance compensation in the prior art.

[0012] Figure 3 Schematic diagram of the equivalent circuit model and working principle of the negative resistance structure.

[0013] Figure 4 Schematic diagram of the negative resistance structure of the prior art.

[0014] Figure 5 Schematic diagram of the structure of the first negative resistance unit of the present disclosure.

[0015] Figure 6 Schematic diagram of the structure of the continuous-time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation according to the embodiment of the present disclosure.

[0016] Figure 7 Schematic diagram of the principle of the second-order feedforward loop filter.

[0017] Figure 8 Schematic diagram of the operation principle of the capacitor array of the quantizer according to the embodiment of the present disclosure.

[0018] Figure 9 Schematic diagram of the conversion phase workflow of the quantizer according to the embodiment of the present disclosure.

[0019] Figure 10 Schematic diagram of the simulated power spectral density of the continuous-time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation according to the embodiment of the present disclosure. Detailed implementation manners

[0020] The present disclosure provides a continuous-time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation. For the structure of the third-order continuous-time Sigma-Delta modulator based on negative resistance compensation, a negative resistance module is introduced inside the integrator. The negative resistance compensation effectively reduces the non-ideal effects of the operational amplifier, thereby reducing the strict requirements for the design of the operational amplifier. The bias of the negative resistance is provided by a constant transconductance bias circuit, which can ensure high matching and has the advantages of low current and low noise. To further simplify the design, the integrator with the first-stage negative resistance compensation adopts a single-opamp resonator structure to generate a second-order response, so that the entire loop filter only requires two operational amplifiers. The quantizer part adopts a successive approximation analog-to-digital converter, and only one comparator is needed to achieve multi-bit quantization. Moreover, the direct feedback of the modulator is realized through the capacitor array inside the quantizer, which avoids an additional feedback digital-to-analog converter and adder. This structure can significantly reduce the power consumption of the modulator while ensuring high precision, and improves the energy efficiency of the overall system.

[0021] A continuous-time Sigma-Delta analog-to-digital converter (ADC) consists of a continuous-time Sigma-Delta modulator and a digital decimation filter. The design of the modulator directly determines the performance of the entire ADC. The structural block diagram of the continuous-time Sigma-Delta modulator is as shown in Figure 1 and mainly consists of three modules: a loop filter, a quantizer, and a digital-to-analog converter (DAC). The loop filter is composed of multiple integrators and has a relatively large power consumption ratio. The performance of the loop filter determines the linearity and noise performance of the modulator. Therefore, its design needs to balance the requirements of accuracy and power consumption. The quantizer usually consists of a low-resolution ADC and is used to convert the output voltage signal of the loop filter into a digital signal. The digital-to-analog converter then converts the digital signal output by the modulator back into an analog signal and feeds it back into the loop filter to achieve closed-loop regulation. In the architecture of the continuous-time Sigma-Delta modulator, a direct feedback path is also required to feedback to the input of the quantizer to ensure the stability of the modulator. The principle of the modulator is to construct a negative feedback loop with a high loop gain within the bandwidth to suppress the quantization noise generated by the quantizer within the bandwidth and modulate it to the high-frequency band outside, so as to achieve high precision within the band. Figure 1 in which represents the transfer function of the input signal u passing through the loop filter, and

[0022]

[0023] Figure 2 The prior art provides a method as shown in Figure 2A three-level FIR feedback third-order continuous-time Sigma-Delta modulator with negative resistance compensation implemented using a 65nm process and a 1.2V power supply voltage, [Reference paper: M. Jang, C. Lee and Y. Chae, "A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC," in IEEE Journal of Solid-State Circuits, vol. 56, no. 6, pp. 1761-1771, June 2021.], achieved a signal-to-noise and distortion ratio (SNDR) of 99.4dB and a figure of merit of 181.9dB ), and the power consumption was 134μW. The three-level FIR feedback can reduce the swing inside the integrator compared to the traditional two-level feedback, thereby improving the overall linearity and reducing the power consumption of the operational amplifier. The negative resistance compensated loop filter structure suppresses the quantization noise floor lift caused by the finite DC gain and finite bandwidth of the operational amplifier by introducing a negative resistance module in the integrator of the loop filter, and reduces the thermal noise and frequency-dependent flicker noise caused by the operational amplifier. The negative resistance output of the first-stage negative resistance compensated integrator is chopped to modulate the frequency-dependent flicker noise in its output outside the bandwidth of the entire analog-to-digital converter.

[0024] Figure 3 The equivalent circuit model of the negative resistance structure shown consists of an integrator and a controlled current source with a transconductance of The integrator is equivalent to an input current source , input resistance , integration load and an operational amplifier, and the current generated by the controlled current source is:

[0025] I COMP =G M V G (1).

[0026] Where, V G is the voltage at the negative input terminal of the amplifier. If this controlled current source is regarded as a resistor, the equivalent resistance value is:

[0027]

[0028] This equivalent resistance is denoted as the negative resistance, and a represents the equivalent resistance value and the input resistance Matching coefficient.

[0029] Assume that the operational amplifier in Figure 3 is ideal, i.e., the gain and input resistance are infinite, and the output resistance is 0. Then the voltage at the negative input terminal of the operational amplifier , and all the input current flows through the load impedance , so there is:

[0030]

[0031] Assume that the actual operational amplifier is a single-pole system, is the DC gain of the operational amplifier, is the pole of the system, and its transfer function H(s) is:

[0032]

[0033] Assume At this time, there is:

[0034]

[0035] is the output voltage, is the input voltage, s represents the complex variable. It can be seen from Equation (5) that due to the finite response of the operational amplifier, the transfer function of the integrator changes and deviates from the response of the ideal integrator, which will lead to a weaker suppression effect on in-band quantization noise. If the transconductance then there is:

[0036]

[0037] To ensure that the integrator has a high gain within the bandwidth, it is necessary to satisfy within the bandwidth. When a is slightly greater than 1, compared with Equation (5), the influence of the term and the term on the integrator transfer function is weakened. When the matching coefficient a = 1, the integrator transfer function becomes:

[0038]

[0039] It can be seen from Equation (7) that when the matching coefficient a = 1, it is perfect compensation. At this time, the integrator has an extra pole compared with the ideal integrator. In the actual design process, the position of this pole far exceeds the bandwidth of the modulator, so the influence on the in-band is negligible. At this time, the response of the actual integrator with negative resistance compensation within the bandwidth is basically the same as that of the ideal integrator. From the circuit point of view, it is when that is, when there is no negative resistance, due to Figure 3 the non-zero voltage , this will cause a part of the input current to flow into the input resistor, that is , resulting in the response of the actual integrator shown in Equation (5) deviating from that of the ideal integrator. After introducing the negative resistance, the negative resistance generates a compensation current to compensate for the current lost on the input resistor, making the response of the integrator tend to that of the ideal integrator. When the matching coefficient a = 1, perfect compensation can be achieved. At this time, almost all of the input current flows into the load Therefore, the response of the integrator with negative resistance compensation within the frequency band is basically the same as that of the ideal integrator. In addition, the input noise of the operational amplifier is equivalent to the input of the integrator and will also be reduced by the negative resistance.

[0040] An existing negative resistance structure is as Figure 4 shown, where the resistor , the transconductance of the PMOS input transistor in the input transistor group is , the transconductance of the two NMOS input transistors is , and it satisfies , the equivalent negative resistance of the negative resistance can be expressed as:

[0041]

[0042] When it satisfies , it can be seen from Equation (8) that the equivalent transconductance only depends on , and when the resistor and the input resistor Figure 2 in take the same type of resistor, high matching can be guaranteed, that is, the resistance value of the negative resistance can follow the change of the input resistor well even when the temperature and process corner change, that is, the matching coefficient a remains basically unchanged.

[0043] Most of the negative resistances in the currently existing continuous-time Sigma-Delta modulators based on negative resistance compensation adopt Figure 4 the structure shown to ensure better matching between the negative resistance and the input resistor, but this structure has two problems: one is that it needs to satisfy , which requires the negative resistance to consume a large current to make the input MOS transistor generate a large transconductance ; the other is that due to the introduction of the resistor contributing a new noise source, the thermal noise performance deteriorates. In addition, the third-order continuous-time Sigma-Delta modulator requires at least three operational amplifiers, resulting in a large power consumption overhead of the loop filter, and in Figure 2 the structure shown, the implementation method of the direct feedback path is through the resistor The passive summation is achieved by resistor voltage division formed by a three-level resistor digital-to-analog converter (RDAC). However, this method introduces new poles that may cause stability problems.

[0044] Therefore, the present disclosure proposes a continuous-time Sigma-Delta modulator structure with constant transconductance bias and negative resistance compensation. By introducing a constant transconductance bias circuit to achieve negative resistance compensation, high matching, low noise, and low current consumption are ensured. The integrator with the first-stage negative resistance compensation adopts a single operational amplifier resonator structure, so that the entire third-order Sigma-Delta modulator can be realized with only two operational amplifiers, significantly reducing power consumption and circuit complexity. In addition, the direct feedback of the modulator is realized by means of a successive approximation analog-to-digital converter, avoiding the stability problems that may be brought by passive summation and the increase in power consumption caused by active summation. This design scheme effectively improves the overall performance and energy efficiency of the modulator while ensuring high precision.

[0045] To make the objectives, technical solutions, and advantages of the present disclosure clearer and more understandable, the following further details the present disclosure in conjunction with specific embodiments and with reference to the accompanying drawings.

[0046] In an embodiment of the present disclosure, a continuous-time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation is provided. In combination with Figure 6 and Figure 5 as shown, the modulator includes a loop filter, a quantizer, and a digital-to-analog converter.

[0047] The loop filter is used to amplify the signals within the effective signal bandwidth and attenuate the out-of-band signals at the same time. The loop filter includes a first-stage integrator with negative resistance compensation and a second-stage integrator with negative resistance compensation connected in sequence. Among them, the first-stage integrator with negative resistance compensation includes a first negative resistance unit with a negative resistance containing a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, forming a single operational amplifier resonator structure to generate a second-order response; the second-stage integrator with negative resistance compensation includes a second negative resistance unit and a second integrator unit containing an operational amplifier;

[0048] The quantizer is connected to the loop filter and adopts a successive approximation analog-to-digital converter, which is used to convert the analog voltage signal into a digital signal and output it;

[0049] The digital-to-analog converter includes a first resistor digital-to-analog converter and a second resistor digital-to-analog converter. Among them, the first resistor digital-to-analog converter is connected to the input end of the operational amplifier in the first integrator unit and is connected to the output end of the quantizer through a data weighted averaging module to achieve the first-stage feedback, and the second resistor digital-to-analog converter is connected to the output end of the quantizer and the input end of the operational amplifier in the second integrator unit to achieve the second-stage feedback.

[0050] According to an embodiment of the present disclosure, in combination with Figure 6 and Figure 5 as shown, the first negative resistance unit includes an input transistor group, a P-type transistor group, and an N-type transistor group, where:

[0051] The input transistor group includes PMOS transistor M IP and NMOS transistor M P7 whose gates are respectively connected to the input terminal V N7 , and PMOS transistor M IN and NMOS transistor M P8 whose gates are respectively connected to the input terminal V N8 ;

[0052] The P-type transistor group includes multiple PMOS transistors for providing a first bias current to PMOS transistors M P7 , M P8 in the input transistor group; and

[0053] The N-type transistor group includes multiple NMOS transistors for providing a second bias current to NMOS transistors , in the input transistor group.

[0054] According to an embodiment of the present disclosure, the first bias current and the second bias current are equal, both being N×I OUT , where N is a positive integer, and the constant transconductance bias circuit includes multiple branches, and I OUT is the current of one of the branches.

[0055] According to an embodiment of the present disclosure, the P-type transistor group includes PMOS transistors M P1 , M P2 , M P3 , M P4 , M P5 , M P6 . The source of PMOS transistor M P1 is connected to resistor R S and then connected to the power supply terminal VDD. The sources of PMOS transistors M P2 , M P3 are directly connected to the power supply terminal VDD. The sources of PMOS transistors M P4 , M P5 , M P6 serving as shielding transistors are respectively connected to the drains of PMOS transistors M P1 , M P2 , M P3 such that the drain voltages of PMOS transistors M P1 , M P2 , M P3 are equal; the drains of PMOS transistors M P1 , M P2, M P3 is connected to the gate of PMOS transistor M P5 and then connected to the drain of PMOS transistor to form a current mirror. PMOS transistor copies the current of PMOS transistor and amplifies it by N times. PMOS transistor , form a current source. The drain of is connected to the source of PMOS transistors , in the input transistor group as the output of the current source to provide a first bias current.

[0056] According to an embodiment of the present disclosure, the N-type transistor group includes NMOS transistors M N1 , M N2 , M N3 , M N4 , M N5 , M N6 . The sources of NMOS transistors M N1 , M N2 , M N3 are grounded respectively. The sources of NMOS transistors M N4 , M N5 , M N6 serving as shielding transistors are connected to the drains of NMOS transistors M N1 , M N2 , M N3 respectively, such that the drain voltages of NMOS transistors M N1 , M N2 , M N3 are equal. The gates of NMOS transistors M N1 , M N2 , M N3 are connected and then connected to the drain of NMOS transistor to form a current mirror. NMOS transistor copies the current of NMOS transistor . NMOS transistor copies the current of NMOS transistor and amplifies it by N times. NMOS transistor forms a current source. The drain of is connected to the sources of NMOS transistors , in the input transistor group as the output of the current source to provide a second bias current.

[0057] According to an embodiment of the present disclosure, the first negative resistance unit further includes resistors , , where:

[0058] Resistor One end is connected to the NMOS transistor The drain of and the NMOS transistor M N1 、M N2 、M N3 The gate, and the other end is connected to the drain of the PMOS transistor M P4 And the NMOS transistor 、 The gate, and is used to provide a stable gate voltage for the NMOS transistors M N4 、M N5 、M N6 So that all the NMOS transistors in the N-type transistor group operate in the saturation region; the resistor One end is connected to the drain of the PMOS transistor And the PMOS transistors M P1 、M P2 、M P3 The gate, and the other is connected to the drain of the NMOS transistor M N5 And the PMOS transistor 、 The gate, and is used to provide a stable gate voltage for the PMOS transistors 、 So that all the PMOS transistors in the P-type transistor group operate in the saturation region.

[0059] According to an embodiment of the present disclosure, the PMOS transistors 、 、 、 、the NMOS transistors 、 、 、 And the resistors R S 、R1, R2 form a constant transconductance biasing circuit, and the constant transconductance biasing circuit's PMOS transistors 、 、and the NMOS transistors 、 Together provide stable biasing for the input transistor group.

[0060] According to an embodiment of the present disclosure, as Figure 6 Shown, the first integrator unit is of a differential structure, including a first operational amplifier, capacitors C1, C2, C1′, C2′, and resistors R in1 、R in1 ′、R1, R2, R1′, R2′, wherein, the resistor R in1 Is connected to the negative input terminal V of the signal INThe non-inverting input terminal of the first operational amplifier, the capacitor C1 and the resistor R1 are connected in parallel between the non-inverting input terminal and the inverting output terminal of the first operational amplifier, and the resistor R2 and the capacitor C2 are connected in series between the non-inverting input terminal and the non-inverting output terminal of the first operational amplifier. The resistor R in1 ' is connected to the positive input terminal V of the signal IP and the inverting input terminal of the first operational amplifier. The capacitor C1' and the resistor R1' are connected in parallel between the inverting input terminal and the non-inverting output terminal of the first operational amplifier, and the resistor R2' and the capacitor C2' are connected in series between the inverting input terminal and the inverting output terminal of the first operational amplifier.

[0061] According to an embodiment of the present disclosure, the second negative resistance unit includes a negative resistance with source feedback; the second integrator unit includes a second operational amplifier, resistors R in2 、R in2 ', capacitors C3, C3', wherein the resistor R in2 is connected between the inverting output terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier, the resistor R in2 ' is connected between the non-inverting output terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier, the capacitor C3 is connected between the non-inverting input terminal and the inverting output terminal of the second operational amplifier, and the capacitor C3' is connected between the inverting input terminal and the non-inverting output terminal of the second operational amplifier.

[0062] According to an embodiment of the present disclosure, the quantizer includes a capacitor array, a comparator and a digital logic unit, and the direct feedback path is implemented on the capacitor array inside the quantizer.

[0063] Specifically, the embodiment of the present disclosure provides a negative resistance structure with a constant transconductance bias as shown in Figure 5 , wherein the source of the PMOS transistor is connected to the resistor , the PMOS transistors 、 and the NMOS transistors 、 and the resistor act together to generate a current . The gates of the PMOS transistors 、 and are connected to the drain of , and the PMOS transistors and form a current mirror, and the PMOS transistor copies the current of and amplifies it by N times. The gates of the NMOS transistors 、 and are connected to the gate of the NMOS transistor The drain of which forms a current mirror, and the NMOS transistor duplicates the current of, and the NMOS transistor duplicates the current of and amplifies it by N times. The PMOS transistors and and have their sources connected to and and the drains of respectively, and are used as shielding transistors to ensure that the PMOS transistors and and have equal drain voltages. The NMOS transistors and and have their sources connected to the drains of the NMOS transistors and and respectively, and are used as shielding transistors to ensure that the NMOS transistors and and have equal drain voltages. One end of the resistor is connected to the drain of the NMOS transistor and the gates of the NMOS transistors M N1 , M N2 , M N3 , and the other end is connected to the drain of the PMOS transistor M P4 and the gates of the NMOS transistors and for providing a stable gate voltage to enable the NMOS transistors of the N-type transistor group to all operate in the saturation region; one end of the resistor N4 , M N5 , M N6 P1 is connected to the drain of the PMOS transistor and the gates of the PMOS transistors M P1 , M P2 , M P3 , and the other is connected to the drain of the NMOS transistor M N5 and the gates of the PMOS transistors and for providing a stable gate voltage to enable the PMOS transistors of the P-type transistor group to all operate in the saturation region. The PMOS transistors and , , , , , and the NMOS transistors and and , form a core negative resistance circuit. The PMOS transistor and form a current source. The drain of the PMOS transistor is connected to the source of the input PMOS transistors and of the negative resistance as the output of the current source and provides a bias current, where the current value is . The NMOS transistors and form a current source. The drain of the NMOS transistor is connected to the source of the NMOS transistors and in the input transistor group of the negative resistance as the output of the current source and provides a bias current, where the current value is .

[0064] The specific analysis of the first negative resistance unit of the negative resistance containing a constant transconductance bias circuit is as follows. and represent the hole and electron mobilities respectively, represents the gate oxide capacitance per unit area, K represents the ratio of the number of parallel-connected unit transistors of the PMOS transistor to , represents the threshold voltage of the PMOS transistor. By adding the voltage across the gate-source of to the voltage drop across the resistor being equal to the gate-source voltage of, we can obtain:

[0065] .

[0066]

[0067] The aspect ratios of the PMOS transistors and are , and the transconductance is . The aspect ratios of the NMOS transistors and are , and the transconductance is . N represents the ratio of the number of parallel-connected unit transistors of to and the ratio of the number of parallel-connected unit transistors of

[0068]

[0069]

[0070] The equivalent resistance of the first negative resistance unit can be expressed as:

[0071]

[0072] It can be seen from Equation (13) that the equivalent resistance is proportional to the resistance . Similarly, if the resistance takes the same type of resistance as the input resistance, then the equivalent resistance can well follow the change of the input resistance with the process corner. However, due to the presence of the ratio of electron mobility to hole mobility in Equation (12), which varies with temperature. However, in the actual design process, the transconductance will be set, and and the influence of the change also needs to be square-rooted and placed in the denominator. Therefore, in a large temperature range such as -40°C to 125°C, the matching coefficient a changes little. Since the negative resistance structure proposed in the present disclosure can not only ensure high matching under process corner and temperature changes, but also the transconductance and in the negative resistance do not need to be designed with very large values, only need to take a specific value, which greatly reduces the current consumed by the negative resistance. At the same time, the source resistance of the input MOS transistor is removed, reducing the output noise of the negative resistance.

[0073] Figure 6 As shown in the 4-bit quantization third-order continuous-time Sigma-Delta modulator proposed in the present disclosure, the negative resistance compensation simplifies the design of the operational amplifier and reduces the requirements for bandwidth, gain, and noise to achieve power consumption reduction. The first negative resistance unit G M1 is Figure 5 the negative resistance structure with a constant transconductance bias circuit shown, avoiding the disadvantages of large current and large noise of the existing negative resistance structure. The output of the first negative resistance unit is connected to the input of the first-stage operational amplifier (the operational amplifier in the integrator with the first negative resistance compensation) through a chopper. The chopper operates at a chopping frequency half of the sampling frequency, modulating the flicker noise of the negative resistance to the out-of-band frequency.

[0074] The principle block diagram of a second-order feedforward loop filter is as shown in Figure 7 . k1 represents the first-order feedforward coefficient, k2 represents the second-order feedforward coefficient, g represents the local feedback coefficient, s represents the complex variable, and its transfer function is:

[0075]

[0076] As shown in Figure 6As shown, the main body of the present disclosure is an integrator with a first-stage negative resistance compensation of a differential structure. On the basis of a traditional active RC integrator, additional devices (resistors , and capacitors ) are introduced to form the structure of a single operational amplifier resonator. Taking one side of the differential structure as an example, its transfer function can be expressed as:

[0077]

[0078] Only by making in Equation (15), Equation (15) will have the form of Equation (14), that is, the same transfer function as that of the design requiring two operational amplifiers in the traditional design can be achieved with one operational amplifier. The second negative resistance unit (G M2 ) in the integrator with a second-stage negative resistance compensation consumes extremely small current due to its large resistance value, so the negative resistance structure shown in Figure 4 is adopted. Resistors , capacitors and the second operational amplifier constitute the second-stage integrator unit (type: active RC integrator). The inputs and of the modulator are fed forward to the input of the second operational amplifier through resistor , thereby reducing the output swing of the integrator with a first-stage negative resistance compensation and improving the linearity. The entire modulator can achieve the design of at least three operational amplifiers required by the traditional third order with only two operational amplifiers, saving the power consumption of one operational amplifier.

[0079] The quantizer of the present disclosure adopts a 4-bit successive approximation analog-to-digital converter, which can further reduce the quantization noise, the swing of the loop filter and the sampling frequency of the entire modulator compared with the three-level FIR feedback and the traditional two-level feedback, thereby further reducing the power consumption. The quantizer is composed of a capacitor array, a comparator and a digital logic unit. As Figure 6 shown, the 4-bit binary digital code D<3:0> output by the quantizer is fed back to the loop filter through the resistor digital-to-analog converters RDAC1 and RDAC2 half a cycle (Z -0.5 ) after the sampling ends. The data weighted average module is used to process the static error caused by the mismatch between the internal units of RDAC1. T<14:0> represents the 15-bit thermometer code output by the quantizer after passing through the digital weighted average module. The digital logic unit can control the potential of the lower plates of the capacitors in the dashed box. C RES and C RES ' represent the capacitors not participating in the conversion.

[0080] The direct feedback path is implemented on the capacitor array inside the quantizer. The operation process of the capacitor array is as Figure 8 shown, C represents the unit capacitance value. and respectively represent the positive reference voltage to ground and the negative reference voltage to ground, and the voltage at the input of the comparator is . During the sampling phase, the bottom plate of the capacitor array is connected to the outputs DP j and DN j (j = 0, 1, 2, 3) of the quantizer in the previous period. The 8C and 4C in the capacitor array are connected to to prevent a large change in the common-mode level of the comparator during the conversion phase. At the end of the sampling phase is connected to , and at this time, there is:

[0081]

[0082] represents the output voltage of the loop filter, and respectively represent the positive output voltage and the negative output voltage of the loop filter. represents the voltage fed back by the direct feedback path. n represents the sequence number of the sampling period, indicating that the current is the nth sampling period. It can be seen from Equation (16) that this method realizes a direct feedback path with a coefficient of 0.5, avoiding the power consumption overhead introduced by additional digital-to-analog converters and adders, as well as the poles introduced when using passive summation. In addition, this method also doubles the output of the loop filter, so the coefficient of the last-stage integrator can be attenuated to 0.5 times the original, and the output swing is also reduced synchronously without exceeding the power supply voltage. Figure 9 The working process of the quantizer during the conversion phase is shown in Figure 8 and Figure 9 . At the beginning of the conversion phase, compare with 0. According to the result, obtain the new and , and change the value of . Repeat this process until the new and values are obtained, and at this time the sampling phase ends. During the conversion phase, the potential connected to the bottom plate of is based on the new and obtained from 4 cycles from i = 1 to i = 4, and the state of the capacitor array gradually changes from the state during the sampling phase to the state at the end of the conversion phase shown in Figure 8 .

[0083] The continuous-time Sigma-Delta modulator proposed in this disclosure is built using a 180nm process, operates at a power supply voltage of 1.8V, and at a sampling frequency of 3.2MHz, the simulation results are Figure 10The shown simulated power spectral density diagram has a signal-to-noise distortion ratio (SNDR) of 101.8 dB, a bandwidth (BW) of 25 KHz, and a power consumption (POWER) of 148 μW. The figure of merit achieved by comprehensively considering the three metrics of SNDR, bandwidth, and power consumption is 184.2 dB, ( ), which is better than that of the prior art third-order continuous-time Sigma-Delta modulator. The results show that the continuous-time Sigma-Delta modulator of the present disclosure meets the design requirements of low power consumption and high resolution.

[0084] The present disclosure proposes a negative resistance compensation structure with a constant transconductance bias to avoid introducing a source resistance to ensure matching; the integrator with the first-stage negative resistance compensation in the proposed continuous-time Sigma-Delta modulator adopts a single-op amp resonator structure, reducing one operational amplifier; the proposed direct feedback path based on a successive approximation analog-to-digital converter avoids the need for additional feedback digital-to-analog converters and adders (including active adders and passive adders) in traditional designs, while reducing the swing inside the loop filter and the sampling frequency of the modulator. The integrator with the first-stage negative resistance compensation adopts a single-op amp resonator structure, simplifying the circuit design and enabling the modulator to require only two operational amplifiers; the quantizer adopts a successive approximation analog-to-digital converter, and the stability and power consumption problems in traditional designs are avoided through the direct feedback method based on the successive approximation analog-to-digital converter; the non-ideal effects of the operational amplifier are reduced through the negative resistance compensation structure with a constant transconductance bias, ensuring high matching, low noise, and small current. This design significantly reduces power consumption while ensuring high precision.

[0085] Compared with traditional designs and the prior art, this structure significantly reduces the number of operational amplifiers. Specifically, the quantizer adopts a successive approximation analog-to-digital converter, and multi-bit quantization can be achieved by using only one comparator. In addition, the modulator adopts a direct feedback implementation based on a successive approximation analog-to-digital converter, avoiding the need for additional feedback digital-to-analog converters and adders (including active adders or passive adders) in traditional designs, thus effectively reducing the circuit complexity and power consumption overhead. In addition, the present disclosure also proposes a negative resistance structure based on a constant transconductance bias to compensate for the non-ideal effects inside the integrator. This innovative structure effectively solves the problems of large current and poor noise performance in the prior art, ensuring both high matching and the advantages of low current and low noise. Through this design, the design requirements for the operational amplifier in the integrator can be relaxed, thereby further reducing the system power consumption.

[0086] Thus far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the accompanying drawings or the main text of the specification, the implementation manners that are not illustrated or described are all forms known to those of ordinary skill in the art and have not been described in detail. In addition, the definitions of the above-mentioned various elements and methods are not limited to the specific structures, shapes, or manners mentioned in the embodiments, and those of ordinary skill in the art can make simple changes or substitutions thereto.

[0087] It should be noted that, in this document, unless otherwise specified, having an element "a" does not limit to having only one such element, but may have one or more of such elements.

[0088] In addition, in this document, unless otherwise specified, ordinal numbers such as "first", "second", etc. are only used to distinguish multiple elements with the same name and do not indicate that there is a rank, level, execution order, or process order between them. A "first" element and a "second" element may appear in the same component together, or in different components separately. The existence of an element with a larger ordinal number does not necessarily mean the existence of another element with a smaller ordinal number.

[0089] In this document, unless otherwise specified, the so-called feature A "or" (or) or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist simultaneously; the so-called feature A "and" (and) or "and" (and) or "and" (and) feature B means that A and B exist simultaneously; the so-called "comprising", "including", "having", "containing" mean including but not limited to this.

[0090] In addition, in this document, terms such as "upper", "lower", "left", "right", "front", "rear", or "between" are only used to describe the relative positions between multiple elements and can be extended in the interpretation to include cases of translation, rotation, or mirror image. In addition, in this document, unless otherwise specified, the statement that "one element is on another element" or a similar statement does not necessarily mean that the element contacts the other element.

[0091] In addition, unless otherwise specifically described or steps that must occur in sequence, the order of the above steps is not limited to those listed above and can be changed or rearranged according to the required design. And the above embodiments can be mixed and used with each other or mixed and used with other embodiments based on considerations of design and reliability, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0092] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A continuous-time Sigma-Delta modulator with negative resistance compensation of constant transconductance bias, comprising: A loop filter for amplifying signals within the effective signal bandwidth while attenuating out-of-band signals. The loop filter includes a first-stage integrator with negative resistance compensation and a second-stage integrator with negative resistance compensation connected in sequence. Among them, the first-stage integrator with negative resistance compensation includes a first negative resistance unit with a negative resistance containing a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, forming a single-op amp resonator structure to generate a second-order response; the second-stage integrator with negative resistance compensation includes a second negative resistance unit and a second integrator unit containing an operational amplifier; A quantizer connected to the loop filter, using a successive approximation analog-to-digital converter, for converting an analog voltage signal into a digital signal and outputting; and A digital-to-analog converter, including a first resistive digital-to-analog converter and a second resistive digital-to-analog converter. Among them, the first resistive digital-to-analog converter is connected to the input terminal of the operational amplifier in the first integrator unit and is connected to the output terminal of the quantizer through a data weighted averaging module to achieve first-stage feedback, and the second resistive digital-to-analog converter is connected to the output terminal of the quantizer and the input terminal of the operational amplifier in the second integrator unit to achieve second-stage feedback.

2. The modulator according to claim 1, wherein the first negative resistance unit includes: An input transistor group, including PMOS transistors M IP whose gates are respectively connected to the input terminal V P7 and NMOS transistors M N7 , and PMOS transistors M IN whose gates are respectively connected to the input terminal V P8 and NMOS transistors M N8 ; P-type transistor group, including multiple PMOS transistors, for supplying a first bias current to PMOS transistors M P7 , M P8 in the input transistor group; And N-type transistor group, including a plurality of NMOS transistors, for supplying a second bias current to the NMOS transistors in the input transistor group , ​ 3. The modulator according to claim 2, wherein the first bias current and the second bias current are equal and both are N×I OUT , where N is a positive integer, the constant transconductance bias circuit includes multiple branches, and I OUT is the current of one of the branches.

4. The modulator according to claim 2 or 3, wherein the P-type transistor group includes PMOS transistors M P1 , M P2 , M P3 , M P4 , M P5 , M P6 . The source of the PMOS transistor M P1 is connected to the resistor R S and then connected to the power supply terminal VDD. The sources of the PMOS transistors M P2 , M P3 are directly connected to the power supply terminal VDD. The sources of the PMOS transistors M P4 , M P5 , M P6 serving as shielding transistors are respectively connected to the drains of the PMOS transistors M P1 , M P2 , M P3 , so that the drain voltages of the PMOS transistors M P1 , M P2 , M P3 are equal; PMOS transistor M P1 and M P2 and M P3 are connected at their gates and then connected to the drain of PMOS transistor M P5 . And the PMOS transistors form a current mirror, and the PMOS transistor copies the current of the PMOS transistor and amplifies it by N times; the PMOS transistors and form a current source, and the drain of is connected to the sources of the PMOS transistors and in the input transistor bank as the output of the current source to provide a first bias current.

5. The modulator according to claim 4, wherein the N-type transistor group includes NMOS transistors M N1 , M N2 , M N3 , M N4 , M N5 , M N6 . The sources of the NMOS transistors M N1 , M N2 , M N3 are grounded respectively and serve as shielding transistors. The sources of the NMOS transistors M N4 , M N5 , M N6 are connected to the drains of the NMOS transistors M N1 , M N2 , M N3 respectively, such that the drain voltages of the NMOS transistors M N1 , M N2 , M N3 are equal; NMOS transistor M N1 , M N2 , M N3 are connected to the gate of NMOS transistor and form a current mirror with the drain of NMOS transistor copying the current of NMOS transistor , and NMOS transistor copying the current of NMOS transistor and amplifying it by N times; NMOS transistor forms a current source, with the drain of which as the output of the current source being connected to the sources of NMOS transistors , in the input transistor group to provide a second bias current.

6. The modulator according to claim 5, wherein the first negative resistance unit further includes a resistor , wherein: Resistor One end of the resistor is connected to the drain of the NMOS transistor and the gates of NMOS transistors M N1 , M N2 , M N3 . The other end is connected to the drain of PMOS transistor M P4 and the gates of NMOS transistors , , and is used to provide a stable gate voltage for NMOS transistors M N4 , M N5 , M N6 so that all NMOS transistors in the N-type transistor group operate in the saturation region; Resistor One end is connected to the drain of the PMOS transistor and the gates of PMOS transistors M P1 , M P2 , M P3 , and the other end is connected to the drain of NMOS transistor M N5 and the gates of PMOS transistors , , for providing a stable gate voltage to PMOS transistors , so that all PMOS transistors in the P-type transistor group operate in the saturation region.

7. The modulator according to claim 6, PMOS transistor , , , , NMOS transistor , , , and resistor R S , R1, and R2 form a constant transconductance bias circuit, and the PMOS transistors , , and NMOS transistors , together provide a stable bias for the input transistor group.

8. The modulator according to claim 1, wherein the first integrator unit includes a first operational amplifier, capacitors C1, C2, C1′, C2′, and resistors R in1 , R in1 ′, R1, R2, R1′, R2′, wherein Resistor R in1 is connected to the negative input terminal V of the signal IN and the non-inverting input terminal of the first operational amplifier. Capacitor C1 and resistor R1 are connected in parallel between the non-inverting input terminal and the inverting output terminal of the first operational amplifier. Resistor R2 and capacitor C2 are connected in series between the non-inverting input terminal and the non-inverting output terminal of the first operational amplifier; Resistor R in1 is connected to the positive input terminal V of the signal IP and the inverting input terminal of the first operational amplifier. Capacitor C1' and resistor R1' are connected in parallel between the inverting input terminal and the non-inverting output terminal of the first operational amplifier. Resistor R2' and capacitor C2' are connected in series between the inverting input terminal and the inverting output terminal of the first operational amplifier.

9. The modulator according to claim 1, wherein the second negative resistance unit includes a negative resistance with source feedback; the second integrator unit includes a second operational amplifier, and resistors R in2 , R in2 ', capacitors C3, C3', wherein the resistor R in2 is connected between the inverting output terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier, and the resistor R in2 ' is connected between the non-inverting output terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier, the capacitor C3 is connected between the non-inverting input terminal and the inverting output terminal of the second operational amplifier, and the capacitor C3' is connected between the inverting input terminal and the non-inverting output terminal of the second operational amplifier.

10. The modulator according to claim 1, wherein the quantizer includes a capacitor array, a comparator, and a digital logic unit, and the direct feedback path is implemented on the capacitor array inside the quantizer.

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