Transmitter compatible with different power supply voltages

Abstract

The invention discloses an emitter compatible with different power supply voltages, and relates to the technical field of emitters. The transmitter comprises an input pair circuit, a first matching circuit, a second matching circuit and a voltage generating circuit. The input pair circuit outputs a plurality of output signals via a plurality of signal pads according to a plurality of input signals. The first matching circuit is powered via a first supply voltage and is turned on according to some control signals to operate as a load of the input-to-circuit in a first mode. The second matching circuit is powered via a second supply voltage and is turned on according to other control signals to operate as a load of the input pair circuit in a second mode. The voltage generating circuit generates the plurality of control signals and bias voltages according to the level of one of the plurality of signal pads, the first and second power supply voltages, the second power supply voltage and a plurality of selection signals. The first matching circuit and the second matching circuit also perform overvoltage and leakage protection according to the bias voltages.

Description

Technical Field

[0001] This application relates to the technical field of transmitters, and particularly to a transmitter that can be compatible with different power supply voltages. Background Art

[0002] In the prior art, transmitters for transmitting data (especially audio and video data) usually need to be paired with components on an external circuit board (such as variable resistors, switches, etc.) to make the transmitter applicable to different data transmission protocols. In the above technology, when the data transmission protocol applied by the transmitter changes, the components on the external circuit board need to be changed accordingly, causing inconvenience to the user in operation. In addition, the components on the external circuit board also consume a large area, resulting in an increase in the overall cost. Summary of the Invention

[0003] In some embodiments, one of the purposes of this application is to provide a transmitter that can be compatible with different power supply voltages to improve the deficiencies of the prior art.

[0004] In some embodiments, the transmitter includes an input pair circuit, a first matching circuit, a second matching circuit, and a voltage generation circuit. The input pair circuit generates a first output signal and a second output signal according to a first input signal and a second input signal, and outputs the first output signal via a first signal pad and outputs the second output signal via a second signal pad. The first matching circuit is powered by a first power supply voltage and selectively conducts according to a first control signal and a second control signal to operate as a load of the input pair circuit in a first mode and provide a first terminal resistance value to the first signal pad and the second signal pad. The second matching circuit is powered by a second power supply voltage and selectively conducts according to a third control signal and a fourth control signal to operate as a load of the input pair circuit in a second mode and provide a second terminal resistance value to the first signal pad and the second signal pad. The voltage generation circuit generates the first control signal, the second control signal, the third control signal, the fourth control signal, a first bias voltage, and a second bias voltage according to a level of a corresponding signal pad among the first signal pad and the second signal pad, the first power supply voltage, the second power supply voltage, and a plurality of selection signals. Wherein, the first matching circuit further performs a first overvoltage and leakage protection in the second mode according to the first bias voltage, and the second matching circuit further performs a second overvoltage and leakage protection in the first mode according to the second bias voltage.

[0005] Regarding the features, implementation, and effects of this application, detailed embodiments are described below in conjunction with the accompanying drawings. Brief Description of the Drawings

[0006] Figure 1Schematic diagram of a transmitter drawn according to some embodiments of the present application;

[0007] Figure 2 Schematic diagram drawn according to some embodiments of the present application Figure 1 of the transmitter;

[0008] Figure 3A Schematic diagram drawn according to some embodiments of the present application Figure 2 of the voltage generator in; and

[0009] Figure 3B Schematic diagram drawn according to some embodiments of the present application Figure 2 of another voltage generator in.

[0010] 100: Transmitter;

[0011] 101: Receiver;

[0012] 110: Input pair circuit;

[0013] 111: Current source;

[0014] 120: Matching circuit;

[0015] 130: Matching circuit;

[0016] 140: Voltage generation circuit;

[0017] 142, 144: Voltage generator;

[0018] 301, 302, 303, 304, 305, 311, 312, 313, 314: Voltage selector;

[0019] DIN, DIP: Input signal;

[0020] DON, DOP: Output signal;

[0021] MN1, MN2: Transistor;

[0022] MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8: Transistor;

[0023] PN, PP: Signal pad;

[0024] R1, R2, R3, R4: Resistor;

[0025] S1, S2, S3: Signal;

[0026] SEL1, SEL2, SEL3: Selection signal;

[0027] VB1, VB2: Bias voltage;

[0028] VC1, VC2, VC3, VC4: Control signals;

[0029] VDD1, VDD2: Power supply voltages;

[0030] VPAD: Level. Detailed implementation manners

[0031] All the terms used in this application have their ordinary meanings. The definitions of the above terms in commonly used dictionaries include only examples of the use of any of the terms discussed herein and should not limit the scope and meaning of this application. Similarly, this application is not limited only to the various embodiments shown in this specification.

[0032] Regarding the use of "coupled" or "connected" herein, it can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, and can also refer to two or more components operating or acting on each other. As used herein, the term "circuit" can be a device that processes signals by connecting at least one transistor and / or at least one active or passive component in a certain manner.

[0033] Figure 1 FIG. 100 is a schematic diagram of a transmitter 100 drawn according to some embodiments of this application. In some embodiments, the transmitter 100 can operate in multiple modes using different power supply voltages. For example, when the transmitter 100 operates in the first mode, the power supply voltage VDD1 mainly used by the transmitter 100 is about 1.8 volts. Or, when the transmitter 100 operates in the second mode, the power supply voltage VDD2 mainly used by the transmitter 100 is about 3.3 volts. In other words, the transmitter 100 can be compatible with different power supply voltages (such as the aforementioned power supply voltage VDD1 and power supply voltage VDD2, and the power supply voltage VDD1 is lower than the power supply voltage VDD2). In some embodiments, the aforementioned first mode and second mode correspond to different data transmission protocols. For example, the first mode can be, but is not limited to, the DisplayPort mode (i.e., the DP mode), and the second mode can be, but is not limited to, the High Definition Multimedia Interface (HDMI) mode.

[0034] In some embodiments, the transmitter 100 includes an input pair circuit 110, a matching circuit 120, a matching circuit 130, and a voltage generation circuit 140. The input pair circuit 110 generates an output signal DOP and an output signal DON according to an input signal DIP and an input signal DIN, outputs the output signal DON to the receiver 101 via a signal pad PP, and outputs the output signal DOP to the receiver 101 via a signal pad PN.

[0035] The matching circuit 120 is powered by the power supply voltage VDD1 and is used to selectively conduct according to the control signal VC1 and the control signal VC2, so as to operate as the load of the input pair circuit 110 in the first mode, and provide a terminal resistance value (for example, the resistance values of the resistors R1 and R2 of Figure 2 ) to the signal pads PP and PN. Similarly, the matching circuit 130 is powered by the power supply voltage VDD2 and is used to selectively conduct according to the control signal VC3 and the control signal VC4, so as to operate as the load of the input pair circuit 110 in the second mode, and provide a terminal resistance value (for example, the resistance values of the resistors R3 and R4 of Figure 2 ) to the signal pads PP and PN.

[0036] Specifically, when the transmitter 100 operates in the first mode, the matching circuit 120 is turned on, and the matching circuit 130 is not turned on. Under this condition, the receiver 101 is a receiver supporting the first mode, and the matching circuit 120 can operate as the load of the input pair circuit 110 in the first mode to cooperate with the input pair circuit 110 to generate the output signal DOP and the output signal DON. At the same time, the matching circuit 120 can provide the terminal resistance value for the receiver 101 supporting the first mode. On the other hand, when the transmitter 100 operates in the second mode, the matching circuit 130 is turned on, and the matching circuit 120 is not turned on. Under this condition, the receiver 101 is a receiver supporting the second mode, and the matching circuit 130 can operate as the load of the input pair circuit 110 in the second mode to cooperate with the input pair circuit 110 to generate the output signal DOP and the output signal DON. At the same time, the matching circuit 130 can provide the terminal resistance value for the receiver 101 supporting the second mode.

[0037] The voltage generation circuit 140 generates a plurality of control signals VC1 to VC4, the bias voltage VB1, and the bias voltage VB2 according to the level of a corresponding signal pad in the signal pads PP and PN (in this example, the signal pad PP, but it can also be the signal pad PN), the power supply voltage VDD1, the power supply voltage VDD2, and a plurality of selection signals SEL1, SEL2, and SEL3. The matching circuit 120 can further perform first overvoltage and leakage current protection in the second mode according to the bias voltage VB1 to ensure that the voltage across both ends of the internal transistor in the matching circuit 120 will not be too high in the second mode, and also avoid unnecessary leakage current generated by the internal transistor. Similarly, the matching circuit 130 can further perform second overvoltage and leakage current protection in the first mode according to the bias voltage VB2 to ensure that the voltage across both ends of the internal transistor in the matching circuit 130 will not be too high in the first mode, and also avoid unnecessary leakage current generated by the internal transistor.

[0038] Figure 2 Drawn according to some embodiments of the present applicationFigure 1 Schematic diagram of the transmitter 100. The input pair circuit 110 includes a transistor MN1, a transistor MN2, and a current source 111. The first end (e.g., the drain) of the transistor MN1 is coupled to the signal pad PN and is used to generate an output signal DOP. The second end (e.g., the source) of the transistor MN1 is coupled to the ground via the current source 111, and the control end (e.g., the gate) of the transistor MN1 receives an input signal DIP. The first end of the transistor MN2 is coupled to the signal pad PP and is used to generate an output signal DON. The second end of the transistor MN2 is coupled to the ground via the current source 111, and the control end of the transistor MN2 receives an input signal DIN.

[0039] The matching circuit 120 includes a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP4, a resistor R1, and a resistor R2. The first end (e.g., the source) of the transistor MP1 receives a power supply voltage VDD1. The second end (e.g., the drain) of the transistor MP1 is coupled to the first end of the transistor MP2, and the control end (e.g., the gate) of the transistor MP1 receives a control signal VC1. The second end of the transistor MP2 is coupled to the signal pad PN via the resistor R1, and the control end of the transistor MP2 receives a control signal VC2. The first end of the transistor MP3 receives the power supply voltage VDD1. The second end of the transistor MP3 is coupled to the first end of the transistor MP4, and the control end of the transistor MP3 receives a control signal VC1. The second end of the transistor MP4 is coupled to the signal pad PP via the resistor R2, and the control end of the transistor MP4 receives a control signal VC2.

[0040] With the above arrangement, the transistors MP1 and MP3 can receive the power supply voltage VDD1 and selectively conduct according to the control signal VC1. The resistor R1 is coupled to the signal pad PN, and the resistor R2 is coupled to the signal pad PP to provide the aforementioned terminal resistance value (e.g., can be, but is not limited to, 50 ohms). The transistor MP2 is coupled between the transistor MP1 and the resistor R1 and selectively conducts according to the control signal VC2. The transistor MP4 is coupled between the transistor MP3 and the resistor R2 and selectively conducts according to the control signal VC2. On the other hand, the base of each of the transistors MP1, MP2, MP3, and MP4 also receives a bias voltage VB1, and adjusts its respective threshold voltage according to this bias voltage VB1 to achieve leakage current protection.

[0041] Similarly, the matching circuit 130 includes transistor MP5, transistor MP6, transistor MP7, transistor MP8, resistor R3, and resistor R4. The first terminal of transistor MP5 receives the power supply voltage VDD2. The second terminal of transistor MP5 is coupled to the first terminal of transistor MP6, and the control terminal of transistor MP5 receives the control signal VC3. The second terminal of transistor MP6 is coupled to the signal pad PP via resistor R3, and the control terminal of transistor MP6 receives the control signal VC4. The first terminal of transistor MP7 receives the power supply voltage VDD2. The second terminal of transistor MP7 is coupled to the first terminal of transistor MP8, and the control terminal of transistor MP7 receives the control signal VC3. The second terminal of transistor MP8 is coupled to the signal pad PN via resistor R4, and the control terminal of transistor MP8 receives the control signal VC4.

[0042] With the above-described arrangement, transistors MP5 and MP7 can receive the power supply voltage VDD2 and selectively conduct according to the control signal VC3. Resistor R3 is coupled to the signal pad PP, and resistor R4 is coupled to the signal pad PN to provide the aforementioned termination resistance value (e.g., can be, but is not limited to, 50 ohms). Transistor MP6 is coupled between transistor MP5 and resistor R3 and selectively conducts according to the control signal VC3. Transistor MP8 is coupled between transistor MP7 and resistor R4 and selectively conducts according to the control signal VC4. On the other hand, the base of each of transistors MP5, MP6, MP7, and MP8 also receives the bias voltage VB2 and adjusts its respective threshold voltage according to this bias voltage VB2 to achieve leakage current protection.

[0043] In some embodiments, the voltage generation circuit 140 includes a voltage generator 142 and a voltage generator 144. The voltage generator 142 generates the control signal VC1, the control signal VC2, and the bias voltage VB1 for providing to the matching circuit 120. The voltage generator 144 generates the control signal VC3, the control signal VC4, and the bias voltage VB2 for providing to the matching circuit 130.

[0044] The following describes possible application scenarios of the transmitter 100. In the first scenario, the transmitter 100 is applied to the first mode (hereinafter referred to as the DP mode), and there is a power supply voltage VDD2 in the applied chip environment. In other words, in the first scenario, both the power supply voltage VDD1 and the power supply voltage VDD2 are powered on. Under this condition, the power supply voltage VDD1 is about 1.8 volts, the power supply voltage VDD2 is about 3.3 volts, and the amplitude range of the levels on the signal pads PN and PP is about 0 to 1.8 volts. Since it is applied to the first mode, the control signals VC1 and VC2 are set to 0 volts, causing the matching circuit 120 to conduct. On the other hand, the control signal VC3 is set to 3.3 volts, and the control signal VC4 is set to 1.65 volts (i.e., half of the power supply voltage VDD2), so that the matching circuit 120 does not conduct and at the same time avoid excessive voltage across each of the transistors MP5, MP6, MP7, and MP8. Furthermore, the bias voltage VB1 is set to be the same as the power supply voltage VDD1 (e.g., 1.8 volts), and the bias voltage VB2 is set to be the same as the power supply voltage VDD2 (e.g., 3.3 volts). In this way, the bases of the internal transistors in the matching circuit 130 can receive the corresponding highest potential, thus avoiding leakage current generated by the non-conducting matching circuit 130.

[0045] In the second scenario, the transmitter 100 is applied to the first mode (i.e., the DP mode), but there is no power supply voltage VDD2 in the applied chip environment. In other words, in the second scenario, the power supply voltage VDD1 is powered on, but the power supply voltage VDD2 is not powered on. Under this condition, the power supply voltage VDD1 is about 1.8 volts, the power supply voltage VDD2 is about 1.8 volts, and the amplitude range of the levels on the signal pads PN and PP is about 0 to 1.8 volts. Since it is applied to the first mode, the control signals VC1 and VC2 are set to 0 volts, causing the matching circuit 120 to conduct. On the other hand, the control signal VC3 is set to 1.8 volts, and the control signal VC4 is set to 0.9 volts (i.e., half of the power supply voltage VDD2), so that the matching circuit 120 does not conduct. Furthermore, the bias voltage VB1 is set to be the same as the power supply voltage VDD1 (e.g., 1.8 volts), and the bias voltage VB2 is set to be the same as the power supply voltage VDD2 (which is 1.8 volts at this time). In this way, the bases of the internal transistors in the matching circuit 130 can still receive the corresponding highest potential.

[0046] In the third scenario, the transmitter 100 is applied to the second mode (i.e., HDMI mode). In the third scenario, both the power supply voltage VDD1 and the power supply voltage VDD2 are powered on. Under this condition, the power supply voltage VDD1 is approximately 1.8 volts, the power supply voltage VDD2 is approximately 3.3 volts, and the amplitude range of the levels on the signal pads PN and PP is approximately 2.3 - 3.3 volts. Since it is applied to the second mode, the control signals VC3 and VC4 are set to 1.65 volts (i.e., half of the power supply voltage VDD2), enabling the matching circuit 130 to conduct. On the other hand, the control signal VC2 is set to 3.3 volts (i.e., the same as the power supply voltage VDD2), and the control signal VC1 is set to 1.65 volts to prevent the matching circuit 120 from conducting and to avoid excessive voltage across each of the transistors MP1 and MP3. Furthermore, the bias voltage VB1 is set to the same level as the signal pad PP (which can also be the signal pad PN), and the bias voltage VB2 is set to the same as the power supply voltage VDD2. In this way, the base of the internal transistor in the matching circuit 120 can receive the bias voltage VB1 higher than the power supply voltage VDD1, thereby increasing the threshold voltage of the internal transistor and reducing the leakage current generated by the internal transistor.

[0047] In the fourth scenario, the transmitter 100 is not powered on (e.g., the transmitter 100 is in the shutdown state). In other words, in the fourth scenario, neither the power supply voltage VDD1 nor the power supply voltage VDD2 is powered on. When the transmitter 100 is not powered on, there may be signals coupled from the receiver 101 on the signal pads PP and PN. Under this condition, the highest level of the signal pad PP or PN can be 3.3 volts. To avoid excessive voltage across any of the internal transistors in the transmitter 100, when the transmitter 100 is not powered on, the voltage generation circuit 140 can set the control signal VC2, the control signal VC4, the bias voltage VB1, and the bias voltage VB2 to the same level as the signal pad PP (or PN), and set the control signals VC1 and VC3 to half of the level of the signal pad PP (or PN).

[0048] The voltage settings for the above four scenarios can be summarized in the following table, and the levels of the relevant signals can be set by the voltage generation circuit 140.

[0049]

[0050]

[0051] Figure 3A Drawn according to some embodiments of the present application Figure 2Schematic diagram of the voltage generator 142 therein. The voltage generator 142 includes a voltage selector 301, a voltage selector 302, a voltage selector 303, a voltage selector 304, and a voltage selector 305. The voltage selector 301 outputs half of the power supply voltage VDD2 as the signal S1 when the power supply voltage VDD2 is powered on, and outputs half of the level of the signal pad PP (or signal pad PN) (i.e., VPAD in the above table) as the signal S1 when the power supply voltage VDD2 is not powered on. The voltage selector outputs a preset low voltage (for example, but not limited to, a low level or 0 volts in the above table) or the signal S1 as the control signal VC1 according to the selection signal SEL1. For example, the level of the selection signal SEL1 is set to be the same as the power supply voltage VDD1 in the first mode and is set to the preset low voltage in the second mode. In the first mode, the voltage selector 302 can output the preset low voltage as the control signal VC1 according to the selection signal SEL1. Alternatively, in the second mode, the voltage selector 302 can output the signal S1 as the control signal VC1 according to the selection signal SEL1.

[0052] The voltage selector 303 outputs the power supply voltage VDD2 as the signal S2 when the power supply voltage VDD2 is powered on, and outputs the level of the signal pad PP (or signal pad PN) (i.e., VPAD in the above table) as the signal S2 when the power supply voltage VDD2 is not powered on. The voltage selector 304 outputs a preset low voltage or the signal S2 as the control signal VC2 according to the selection signal SEL2. In some embodiments, the level of the selection signal SEL2 is set to be the same as the power supply voltage VDD1 in the first mode and is set to the preset low voltage in the second mode. The voltage selector 305 outputs the power supply voltage VDD1 as the bias voltage VB1 when the power supply voltage VDD1 is powered on, and outputs the level of the signal pad PP (or signal pad PN) as the bias voltage VB1 when the power supply voltage VDD1 is not powered on.

[0053] In some embodiments, each of the voltage selector 301, the voltage selector 303, and the voltage selector 305 can be implemented by a voltage comparison circuit, where the voltage comparison circuit can compare two received voltages and output the one with the higher level of the two voltages as the corresponding output. In some embodiments, the aforementioned voltage comparator circuit can be implemented by two cross-coupled P-type transistors, but the present application is not limited thereto. In some embodiments, each of the voltage selector 302 and the voltage selector 304 can be implemented by a multiplexer, where the multiplexer can generate a corresponding output according to the corresponding selection signal. The implementation manners of the above multiple circuits are only examples, and the present application is not limited thereto.

[0054] Figure 3B Drawn according to some embodiments of the present applicationSchematic diagram of the voltage generator 144 in Figure 2 . The voltage generator 144 includes a voltage selector 311, a voltage selector 312, a voltage selector 313, and a voltage selector 314. The voltage selector 311 outputs half of the power supply voltage VDD2 as the signal S3 when the power supply voltage VDD2 is powered on, and outputs half of the level of the signal pad PP (or signal pad PN) as the signal S3 when the power supply voltage VDD2 is not powered on. The voltage selector 312 outputs the signal S3 or a preset high voltage (which may be the same as the power supply voltage VDD2) as the control signal VC3 according to the selection signal SEL3. The level of the selection signal SEL3 is set to be the same as the power supply voltage VDD2 in the first mode and is set to be the same as the aforementioned preset low voltage in the second mode. For example, when the level of the selection signal SEL3 is the same as the power supply voltage VDD2, the voltage selector 312 outputs the aforementioned preset high voltage as the control signal VC3. Alternatively, when the selection signal SEL3 is set to the aforementioned preset low voltage, the voltage selector 312 outputs the signal S3 as the control signal VC3.

[0055] The voltage selector 313 outputs the signal S3 as the control signal VC4 when the power supply voltage VDD2 is powered on, and outputs the level VPAD of the signal pad PP (or signal pad PN) as the control signal VC4 when the power supply voltage VDD2 is not powered on. In other words, the voltage selector 313 can output the signal S3 or the level VPAD of the signal pad PP (or signal pad PN) as the control signal VC4 according to the power supply voltage VDD2. The voltage selector 314 outputs the power supply voltage VDD2 as the bias voltage VB2 when the power supply voltage VDD2 is powered on, and outputs the level VPAD of the signal pad PP (or signal pad PN) as the bias voltage VB2 when the power supply voltage is not powered on.

[0056] In some embodiments, each of the voltage selector 311 and the voltage selector 314 can be implemented by the aforementioned voltage comparison circuit. In some embodiments, each of the voltage selector 312 and the voltage selector 313 can be implemented by the aforementioned multiplexer. The implementation manners of the above-mentioned multiple circuits are only examples, and the present application is not limited thereto. In some embodiments, the transmitter 100 may include a plurality of voltage dividing circuits (not shown), which can generate a half level of the power supply voltage VDD2 (for example, 0.5×VDD2 in Figure 3B ) according to the power supply voltage VDD2, and can generate a half level of the level VPAD (for example, 0.5×VPAD in Figure 3B ) according to the level VPAD of the signal pad PP (or signal pad PN). Figure 3A or Figure 3B In Figure 3B , and can generate a half level of the level VPAD (for example, 0.5×VPAD in Figure 3B ) according to the level VPAD of the signal pad PP (or signal pad PN). Figure 3A or Figure 3B In Figure 3B .

[0057] ​In summary, the transmitters provided by some embodiments of the present application are compatible with multiple different power supply voltages and multiple modes corresponding to different data transmission protocols, and can provide corresponding overvoltage and leakage current protection in each mode. In addition, the transmitters provided by some embodiments of the present application can set each voltage to be applicable to different modes by setting in the chip adjustment circuit, without adjusting the components outside the chip. Thus, the area consumption of the components outside the chip can be reduced and the convenience of product application can be improved.

[0058] Although the embodiments of the present application are as described above, these embodiments are not intended to limit the present application. Those skilled in the art of the present technology can change the technical features of the present application according to the explicit or implicit content of the present application. All such changes may fall within the scope of patent protection sought by the present application. In other words, the scope of patent protection of the present application is defined by the scope of the patent application in this specification.

Claims

1. A transmitter, characterized in that, Comprising: An input pair circuit that generates a first output signal and a second output signal based on a first input signal and a second input signal, and outputs the first output signal via a first signal pad and the second output signal via a second signal pad; A first matching circuit that is powered by a first power supply voltage and selectively conducts according to a first control signal and a second control signal, and operates as a load of the input pair circuit in a first mode, and provides a first terminal resistance value to the first signal pad and the second signal pad; A second matching circuit that is powered by a second power supply voltage and selectively conducts according to a third control signal and a fourth control signal, and operates as a load of the input pair circuit in a second mode, and provides a second terminal resistance value to the first signal pad and the second signal pad; And A voltage generation circuit that generates the first control signal, the second control signal, the third control signal, the fourth control signal, a first bias voltage, and a second bias voltage based on a level of a corresponding signal pad among the first signal pad and the second signal pad, the first power supply voltage, the second power supply voltage, and a plurality of selection signals, wherein the first matching circuit further performs a first overvoltage and leakage protection in the second mode according to the first bias voltage, and the second matching circuit further performs a second overvoltage and leakage protection in the first mode according to the second bias voltage.

2. The transmitter according to claim 1, wherein When the transmitter is not powered on, the voltage generation circuit sets the level of each of the second control signal, the fourth control signal, the first bias voltage, and the second bias voltage to be the same as the level of the corresponding signal pad, and sets the level of each of the first control signal and the third control signal to be half of the level of the corresponding signal pad.

3. The emitter according to claim 1, characterized in that, The first mode and the second mode correspond to different data transmission protocols, and the first power supply voltage is lower than the second power supply voltage.

4. The transmitter according to claim 1, characterized in that, The first matching circuit includes: A first transistor that receives the first power supply voltage and selectively conducts according to the first control signal; A first resistor coupled to the first signal pad; A second transistor coupled between the first transistor and the first resistor and selectively conducts according to the second control signal; A third transistor that receives the first power supply voltage and selectively conducts according to the first control signal; A second resistor coupled to the second signal pad; and A fourth transistor coupled between the third transistor and the second resistor and selectively conducts according to the second control signal, wherein a base of each of the first transistor, the second transistor, the third transistor, and the fourth transistor further receives the first bias voltage.

5. The transmitter according to claim 1, wherein The second matching circuit includes: A first transistor that receives the second power supply voltage and selectively conducts according to the third control signal; A first resistor coupled to the second signal pad; A second transistor, coupled between the first transistor and the first resistor, and selectively conducting according to the fourth control signal; A third transistor, receiving the second power supply voltage, and selectively conducting according to the third control signal; A second resistor, coupled to the first signal pad; and A fourth transistor, coupled between the third transistor and the second resistor, and selectively conducting according to the fourth control signal, wherein a base of each of the first transistor, the second transistor, the third transistor, and the fourth transistor further receives the first bias voltage.

6. The transmitter according to claim 1, characterized in that, In the first mode, when both the first power supply voltage and the second power supply voltage are powered on, the voltage generation circuit sets the levels of both the first control signal and the second control signal to a preset low voltage, sets the first bias voltage to be the same as the first power supply voltage, sets the levels of both the third control signal and the second bias voltage to be the same as the second power supply voltage, and sets the level of the fourth control signal to half of the second power supply voltage.

7. The transmitter according to claim 1, characterized in that, In the first mode, when the first power supply voltage is powered on and the second power supply voltage is not powered on, the voltage generation circuit sets the levels of both the first control signal and the second control signal to a preset low voltage, sets the first bias voltage to be the same as the first power supply voltage, sets the levels of both the third control signal and the second bias voltage to be the same as the first power supply voltage, and sets the level of the fourth control signal to half of the first power supply voltage.

8. The emitter according to claim 1, characterized in that, In the second mode, the voltage generation circuit sets the levels of the first control signal, the third control signal, and the fourth control signal to half of the second power supply voltage, sets the level of the second control signal and the second bias voltage to be the same as the second power supply voltage, and sets the first bias voltage to the level of the corresponding signal pad.

9. The transmitter according to claim 1, characterized in that, The voltage generation circuit includes: A first voltage selector, outputting half of the second power supply voltage as a first signal when the second power supply voltage is powered on, and outputting half of the level of the corresponding signal pad as the first signal when the second power supply voltage is not powered on; A second voltage selector, outputting a preset low voltage or the first signal as the first control signal according to a first selection signal among the plurality of selection signals, wherein the level of the first selection signal is set to be the same as the first power supply voltage in the first mode and set to the preset low voltage in the second mode; A third voltage selector, outputting the second power supply voltage as a second signal when the second power supply voltage is powered on, and outputting the level of the corresponding signal pad as the second signal when the second power supply voltage is not powered on; A fourth voltage selector that outputs the preset low voltage or the second signal as the second control signal according to a second selection signal among the plurality of selection signals, wherein the level of the second selection signal is set to be the same as the first power supply voltage in the first mode and is set to the preset low voltage in the second mode; and A fifth voltage selector that outputs the first power supply voltage as the first bias voltage when the first power supply voltage is powered on and outputs the level of the corresponding signal pad as the first bias voltage when the first power supply voltage is not powered on.

10. The transmitter according to claim 1, characterized in that, The voltage generation circuit includes: A first voltage selector that outputs half of the second power supply voltage as a first signal when the second power supply voltage is powered on and outputs half of the level of the corresponding signal pad as the first signal when the second power supply voltage is not powered on; A second voltage selector that outputs the first signal or a preset high voltage as the third control signal according to a first selection signal among the plurality of selection signals, wherein the level of the first selection signal is set to be the same as the second power supply voltage in the first mode and is set to a preset low voltage in the second mode; A third voltage selector that outputs the first signal as the fourth control signal when the second power supply voltage is powered on and outputs the level of the corresponding signal pad as the fourth control signal when the second power supply voltage is not powered on; and A fourth voltage selector that outputs the second power supply voltage as the second bias voltage when the second power supply voltage is powered on and outputs the level of the corresponding signal pad as the second bias voltage when the second power supply voltage is not powered on.

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