Signal processing method, device and FPGA

Abstract

The application provides a signal processing method, device and FPGA, and relates to the technical field of signal processing.The method comprises the following steps: obtaining at least two parallel signals by signal multiplexing on an input signal; performing resampling with different delay times on each of the at least two parallel signals to obtain at least two resampled signals, wherein the different delay times are used to cover periodically and uniformly distributed points in a symbol period corresponding to the input signal; and determining a first target data sequence according to the at least two resampled signals, wherein the delay time of the resampled signal corresponding to the first target data sequence points to a correct sampling time.The method uses a multi-signal parallel and multi-delay resampling mode to attempt to cover all possible available sampling points to realize bit synchronization, reduces the calculation complexity of the bit synchronization step, and thus improves the signal processing efficiency and reduces the demand for hardware resources.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a signal processing method, device and FPGA. Background Art

[0002] In digital communications, the receiver is responsible for recovering the original data from the RF signal. The receiver's signal processing steps include downconversion, decimation filtering, frequency and phase synchronization, matched filtering, demodulation, phase resolution, bit synchronization, and frame synchronization. Timing synchronization involves recovering a bit clock signal synchronized with the transmitter at the receiver to ensure accurate sampling and decision-making of the data stream. This determines the optimal sampling time. Currently, the most common method for bit synchronization is the Gadner loop method.

[0003] However, the existing synchronous Gadner ring method has the problems of complex calculation process and high demand for hardware resources. Summary of the Invention

[0004] The present invention provides a signal processing method, device, and FPGA to address the defects of the existing bit synchronization method in the high computational complexity and large demand for hardware resources. The method adopts multi-channel signal parallelism and multi-delay resampling to attempt to cover all possible available sampling points to achieve bit synchronization, thereby reducing the computational complexity of the bit synchronization step, thereby improving signal processing efficiency and reducing the demand for hardware resources.

[0005] The present invention provides a signal processing method, comprising the following steps:

[0006] Performing signal multiplexing on an input signal to obtain at least two parallel signals, wherein the input signal is obtained by oversampling and matching filtering an in-phase orthogonal signal;

[0007] Resampling each of the at least two parallel signals with different delay times to obtain at least two resampled signals, wherein the different delay times are used to cover periodically evenly distributed points in a symbol period corresponding to the input signal;

[0008] A first target data sequence is determined according to the at least two resampled signals, and the delay time of the resampled signals corresponding to the first target data sequence points to a correct sampling moment.

[0009] According to a signal processing method provided by the present invention, resampling each of the at least two parallel signals with different delay times to obtain at least two resampled signals includes:

[0010] determining at least two delay units, wherein the at least two delay units are configured to generate at least two phase delays uniformly distributed within a symbol period;

[0011] Each of the at least two parallel signals is passed through a corresponding delay unit in the at least two delay units to obtain the at least two resampled signals.

[0012] According to a signal processing method provided by the present invention, the at least two parallel signals include four parallel signals, the at least two delay units include four delay units, and the four delay units include no delay unit, a delay unit for a quarter symbol period, a delay unit for a half symbol period, and a delay unit for a three-quarter symbol period.

[0013] According to a signal processing method provided by the present invention, determining a first target data sequence according to the at least two resampled signals includes:

[0014] Demodulating each of the at least two resampled signals to obtain at least two first data sequences;

[0015] Performing correlation detection on each of the at least two first data sequences and a preset synchronization header to obtain at least two first detection results;

[0016] Determine that a first data sequence corresponding to a first target detection result among the at least two first detection results is the first target data sequence, and the first target detection result is a first detection result among the at least two first detection results indicating that a correlation with the preset synchronization head meets a preset correlation requirement.

[0017] According to a signal processing method provided by the present invention, determining a first target data sequence according to the at least two resampled signals includes:

[0018] performing signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal;

[0019] Performing phase rotation of different angles on each of the at least four multiplexed signals corresponding to each of the resampled signals to obtain at least four rotated signals corresponding to each of the resampled signals;

[0020] determining a second target data sequence corresponding to each resampled signal according to at least four rotated signals corresponding to each resampled signal, wherein a rotation angle of the rotated signal corresponding to the second target data sequence points to a correct restored phase;

[0021] The first target data sequence is determined according to the second target data sequence corresponding to each of the resampled signals.

[0022] According to a signal processing method provided by the present invention, performing phase rotation of each of the at least four multiplexed signals corresponding to each of the resampled signals at different angles to obtain at least four rotated signals corresponding to each of the resampled signals includes:

[0023] Determine the inverse matrices of at least four rotation matrices corresponding to each resampled signal, wherein the inverse matrices of the at least four rotation matrices are used to implement inverse rotations of at least four angles uniformly distributed in the symbol phase space;

[0024] Each of the at least four multiplexed signals corresponding to each of the resampled signals is multiplied by the inverse matrix of the at least four rotation matrices corresponding to each of the resampled signals to obtain at least four rotated signals corresponding to each of the resampled signals.

[0025] According to a signal processing method provided by the present invention, the at least four multiplexed signals corresponding to each resampled signal include four multiplexed signals, and the inverse matrices of the at least four rotation matrices corresponding to each resampled signal include the inverse matrices of four rotation matrices, and the inverse matrices of the four rotation matrices include the inverse matrix of the unit matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0026] According to a signal processing method provided by the present invention, determining a second target data sequence corresponding to each resampled signal according to at least four rotated signals corresponding to each resampled signal includes:

[0027] Demodulating each of the at least four rotated signals corresponding to each of the resampled signals to obtain at least four second data sequences corresponding to each of the resampled signals;

[0028] performing correlation detection on each of the at least four second data sequences corresponding to each of the resampled signals and a preset synchronization header, to obtain at least four second detection results corresponding to each of the resampled signals;

[0029] Determine that a second data sequence corresponding to a second target detection result among the at least four second detection results corresponding to each of the resampled signals is the second target data sequence corresponding to each of the resampled signals, and the second target detection result is a second detection result among the at least four second detection results indicating that the correlation with the preset synchronization head meets a preset correlation requirement.

[0030] According to the signal processing method provided by the application, the first target data sequence is determined according to the second target data sequence corresponding to each resampling signal, and the method comprises the following steps:

[0031] The second target data sequence corresponding to each resampling signal is respectively detected in correlation with a preset synchronization header, so as to obtain at least two third detection results corresponding to the at least two resampling signals;

[0032] The second target data sequence corresponding to a third target detection result in the at least two third detection results is determined as the first target data sequence, and the third target detection result is one third detection result in the at least two third detection results, which indicates that the correlation with the preset synchronization header meets a preset correlation requirement.

[0033] The application further provides a signal processing device, which comprises the following modules:

[0034] A signal multiplexing module is configured to perform signal multiplexing on an input signal to obtain at least two parallel signals, wherein the input signal is obtained by oversampling and matched filtering on a same-phase quadrature signal;

[0035] A signal delay module is configured to perform resampling on each parallel signal in the at least two parallel signals at different delay times to obtain at least two resampling signals, wherein the different delay times are used to cover periodically and uniformly distributed points in a symbol period corresponding to the input signal;

[0036] A sequence selection module is configured to determine a first target data sequence according to the at least two resampling signals, wherein the delay time of the resampling signal corresponding to the first target data sequence points to a correct sampling time.

[0037] The application further provides an FPGA, which comprises a memory, a processor and instructions stored in the memory and running on the processor, and the processor implements the signal processing method according to any one of the above-mentioned embodiments when executing the instructions.

[0038] The signal processing method, device and FPGA provided by the application can cover all possible sampling points by using the parallel multi-signal and multi-delay resampling mode to realize bit synchronization, thereby reducing the calculation complexity of the bit synchronization step, improving the signal processing efficiency and reducing the demand for hardware resources. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to make the technical solutions in the present application or prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without any creative work based on the embodiments in the present application shall fall into the protection scope of the present application.

[0040] Figure 1 is a schematic diagram of a transmitter processing flow provided by the present application.

[0041] Figure 2 is a schematic diagram of a receiver processing flow provided by the present application.

[0042] Figure 3 is a flowchart of a signal processing method provided by the present application.

[0043] Figure 4 is one of flowcharts of a method for obtaining a first target data sequence provided by the present application.

[0044] Figure 5 is another flowchart of a method for obtaining a first target data sequence provided by the present application.

[0045] Figure 6 is a first part of a schematic diagram of a multi-path parallel bit synchronization and phase ambiguity resolution processing flow provided by the present application.

[0046] Figure 7 is a second part of a schematic diagram of a multi-path parallel bit synchronization and phase ambiguity resolution processing flow provided by the present application.

[0047] Figure 8 is a structural schematic diagram of a signal processing device provided by the present application.

[0048] Figure 9 is a structural schematic diagram of an FPGA provided by the present application. DETAILED DESCRIPTION

[0049] In order to make the technical solutions in the present application or prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without any creative work based on the embodiments in the present application shall fall into the protection scope of the present application.

[0050] Firstly, the practical application scene of the signal processing method provided by the application is introduced. Exemplarily, in a quadrature phase shift keying (QPSK) modulation communication implemented based on a field programmable gate array (FPGA), the QPSK modulation communication includes a transmitter and a receiver.

[0051] Figure 1 is a schematic diagram of a transmitter processing flow provided by the application. As shown in Figure 1 , the transmitter processing flow includes: a source-scrambling-encoding-interleaving-framing-phase modulation-shaping filter-interpolation filter-up conversion-DAC digital-to-analog converter. Among them, the target of the transmitter is to convert the original data into a QPSK modulated signal suitable for wireless transmission.

[0052] Figure 2 is a schematic diagram of a receiver processing flow provided by the application. As shown in Figure 2 , the receiver processing flow includes: an analog-to-digital converter (ADC)-down conversion-decimation filter-frequency phase synchronization-matched filter-demodulation-phase ambiguity resolution-bit synchronization-frame synchronization-deinterleaving-decoding-de-scrambling-sink, wherein the frame synchronization step is used to determine the correlation of the synchronization header to determine whether the phase ambiguity resolution and bit synchronization are successfully executed.

[0053] Among them, the target of the receiver is to recover the original data from the radio frequency signal. The timing synchronization step is to determine the best sampling time. The phase ambiguity resolution step is to correct the possible 90° phase rotation (such as 0°, 90°, 180°, 270° ambiguity) of QPSK. The core part of the application mainly includes the bit synchronization and phase ambiguity resolution steps.

[0054] It can be seen that in digital communication, the receiver is responsible for recovering the original data from the radio frequency signal. The timing synchronization step refers to recovering the bit clock signal synchronized with the sending end at the receiving end to ensure correct sampling and decision of the data stream, that is, the function is to determine the best sampling time. At present, the timing synchronization method generally uses Gadner ring, which is a feedback control principle to change the frequency and phase of the clock to realize the adjustment of symbol synchronization. The Gadner ring is relatively complex, and requires a large amount of hardware resources, and its convergence speed may be slow.

[0055] It can be seen that the bit synchronization method used in the prior art has the problems of high computational complexity and large demand for hardware resources.

[0056] In view of this, an embodiment of the present invention provides a signal processing method, which multiplexes an input signal to obtain at least two parallel signals, wherein the input signal is obtained by oversampling and matching filtering an in-phase orthogonal signal; resamples each of the at least two parallel signals with different delay times to obtain at least two resampled signals, wherein the different delay times are used to cover the periodically uniformly distributed points in the symbol period corresponding to the input signal; determines a first target data sequence based on the at least two resampled signals, wherein the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment. This method uses multi-channel signal parallelism and multi-delay resampling to attempt to cover all possible available sampling points to achieve bit synchronization, thereby reducing the computational complexity of the bit synchronization step, thereby improving signal processing efficiency and reducing the demand for hardware resources.

[0057] The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

[0058] Figure 3 The signal processing method provided by the present invention is a flow chart. The signal processing method can be applied to a field programmable gate array (FPGA), which can include logic units, DSP resources, BRAM resources, etc. Figure 3 As shown, the method may include the following steps 101 to 103:

[0059] Step 101: multiplexing input signals to obtain at least two parallel signals, wherein the input signals are obtained by oversampling and matching filtering in-phase and quadrature signals.

[0060] It should be noted that the input signal can be the in-phase and quadrature IQ signals at the receiving end, obtained through oversampling and matched filtering. Matched filtering is used to eliminate noise and optimize the signal-to-noise ratio. Oversampling refers to a sampling rate higher than the symbol rate, typically 4-8 times the symbol rate, to determine the correct sampling point. The oversampled and matched-filtered IQ signals are multiplexed into multiple channels (e.g., two, three, or four channels), each of which can correspond to a possible sampling delay scenario.

[0061] Among them, there are many methods for multiplexing the input signal to obtain at least two parallel signals. For example, the signal can be copied by hardware, that is, through multiple parallel processing units of FPGA (such as DSP units, logic units, etc.). It can also be copied by software, that is, the IQ signal after matched filtering and oversampling is stored in the memory, and then the signal is multiplexed into multiple buffers through memory copy operations. The present invention does not limit the method of multiplexing the input signal to obtain at least two parallel signals.

[0062] In theory, bit synchronization can find a usable sampling point within two paths, so at least two paths are required. However, the more paths there are, the higher the bit synchronization accuracy. In other words, there is theoretically an optimal sampling point, and the more paths there are, the closer the sampling point is to the theoretical optimal point. In practice, the number of paths can be determined based on the communication modulation method used to ensure that the sampling point is close enough to the optimal point to ensure communication.

[0063] Step 102: resampling each of the at least two parallel signals with different delay times to obtain at least two resampled signals, wherein the different delay times are used to cover periodically evenly distributed points in a symbol period corresponding to the input signal.

[0064] It should be noted that the bit synchronization step requires precisely finding the optimal sampling moment for the signal to avoid intersymbol interference. Traditional methods (such as the Gardner loop) rely on feedback loops, resulting in slow convergence and high resource consumption. After obtaining at least two parallel signals, the present invention resamples each parallel signal with different delay times to generate at least two resampled signals, which are used to find the optimal sampling moment for the input signal.

[0065] The method for resampling the input signal with different delay times may adopt a shift register chain, a BRAM circular buffer, and the like. The present invention does not limit the method for resampling each parallel signal with different delay times.

[0066] Step 103: Determine a first target data sequence according to the at least two resampled signals, wherein the delay time of the resampled signals corresponding to the first target data sequence points to a correct sampling moment.

[0067] It should be noted that after obtaining at least two resampled signals, the first target data sequence can be determined in a variety of ways, for example, it can be determined based on peak correlation detection, it can be determined based on synchronization head correlation, or it can be determined based on a comprehensive evaluation of eye opening, etc. The present invention does not limit the method for determining the first target data sequence based on the at least two resampled signals.

[0068] It can be understood that the present invention reduces the computational complexity of the bit synchronization step by simultaneously attempting to cover all possible available sampling points through at least two parallel input signals, avoids the delay of traditional loop adjustment, reduces the demand for hardware resources, and improves signal processing efficiency.

[0069] In some embodiments, step 102 resamples each of the at least two parallel signals with different delay times to obtain at least two resampled signals, which may include: determining at least two delay units, wherein the at least two delay units are used to generate at least two phase delays uniformly distributed within a symbol period; and passing each of the at least two parallel signals through a corresponding delay unit of the at least two delay units to obtain the at least two resampled signals.

[0070] It should be noted that resampling with at least two different delay times can be performed using at least two delay units, i.e., each parallel signal can pass through a corresponding delay unit. For example, for QPSK, the delay unit can be a delay unit with no delay, a delay of T / 4, a delay of T / 2, or a delay of 3T / 4, where T is the symbol period. For other modulation schemes, the delay unit can be a delay unit with no delay or a delay of T / 2. By passing each parallel signal through a delay unit that generates a different delay time, at least two resampled signals can be obtained, and the different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal.

[0071] It is understandable that the delay unit has relatively low complexity. For example, the delay unit can be efficiently implemented in an FPGA through a logic unit, which can improve signal processing efficiency.

[0072] Furthermore, the at least two parallel signals include four parallel signals, the at least two delay units include four delay units, and the four delay units include no delay unit, a quarter symbol period delay unit, a half symbol period delay unit, and a three-quarter symbol period delay unit.

[0073] It should be noted that in QPSK modulation, the delay time can be no delay, delay T / 4, T / 2, or 3T / 4 cycles. Therefore, the oversampled signal can be multiplexed into four parallel branches, each passing through a different delay unit (such as no delay, delay T / 4, T / 2, or 3T / 4, where T is the symbol period) to generate resampled signals with different phase offsets.

[0074] It is understandable that by assigning each signal to a candidate sampling moment, key phase points within the symbol period are covered, and this can be implemented using an FPGA, meaning that delay can be achieved using a shift register, thereby improving signal processing efficiency.

[0075] Figure 4 This is one of the flow charts of the method for obtaining the first target data sequence provided by the present invention. Figure 4 As shown, the step 103 of determining the first target data sequence according to the at least two resampled signals may include:

[0076] Step 201: Demodulate each of the at least two resampled signals to obtain at least two first data sequences;

[0077] Step 202: performing correlation detection on each of the at least two first data sequences and a preset synchronization header to obtain at least two first detection results;

[0078] Step 203: Determine that the first data sequence corresponding to the first target detection result among the at least two first detection results is the first target data sequence, and the first target detection result is a first detection result among the at least two first detection results indicating that the correlation with the preset synchronization head meets the preset correlation requirement.

[0079] It should be noted that demodulating each resampled signal (e.g., QPSK demodulation) can produce at least two first data sequences. A synchronization header optimization method is then used to determine the first target data sequence. A known synchronization header is preset in the frame structure; the preset synchronization header can be a fixed bit sequence. The correlation between each demodulated first data sequence and the synchronization header is calculated, and the data sequence with the highest correlation is selected as the final output. The corresponding delay is then determined as the optimal sampling time, completing the bit synchronization step. Correlation detection can employ methods such as cross-correlation peak detection.

[0080] It can be understood that the present invention uses the synchronization head matching method to determine the optimal sampling point with low complexity, without the need for iterative convergence, and achieves rapid convergence of operations. In addition, correlation detection can be efficiently implemented in FPGA through logic units, thereby improving signal processing efficiency.

[0081] The signal processing method provided by this invention performs parallel processing of multiple resampled oversampled signals at different delays after matched filtering of the IQ signals at the receiving end. After demodulation, the multi-channel parallel sequences are optimized for bit synchronization using correlation with synchronization headers. This solution, through multi-channel delayed resampling and synchronization header optimization, achieves high-speed, low-resource bit synchronization and is particularly suitable for parallel implementation of modulation systems such as QPSK on FPGAs.

[0082] In some embodiments, the input signal not only needs to determine the optimal sampling time, but also has a phase ambiguity problem. Therefore, while performing bit synchronization, phase ambiguity resolution processing is also required to improve signal processing efficiency.

[0083] Figure 5 This is the second flow chart of the method for obtaining the first target data sequence provided by the present invention. Figure 5 As shown, the step 103 of determining the first target data sequence according to the at least two resampled signals may include the following steps 301 to 304:

[0084] Step 301: performing signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal.

[0085] It should be noted that each resampled signal is derived from the in-phase and quadrature IQ signals at the receiver through matched filtering. Matched filtering is used to eliminate noise and maximize the signal-to-noise ratio. The matched filtered IQ signals are multiplexed into multiple channels (e.g., two, three, or four channels), each of which can correspond to a possible phase ambiguity scenario. QPSK's frequency and phase synchronization converges all signals into four corners, so deambiguation involves determining which of the four angles each correct signal represents. Therefore, phase ambiguity resolution requires at least four replicated channels, one for each angle. Correction is achieved by rotating the four parallel signals through the four angles. Other modulation schemes may require more rotation angles, which can be configured as needed.

[0086] There are many methods for multiplexing each resampled signal to obtain at least two multiplexed signals. For example, the signal can be copied by hardware, that is, by using multiple parallel processing units of an FPGA (such as a DSP unit, a logic unit, etc.). Alternatively, the signal can be copied by software, that is, by storing the matched filtered IQ signal in a memory and then multiplexing the signal into multiple buffers through a memory copy operation. The present invention does not limit the method for multiplexing the resampled signals to obtain at least two multiplexed signals.

[0087] Step 302: performing phase rotation of different angles on each of the at least four multiplexed signals corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal.

[0088] It should be noted that after frequency and phase synchronization of the IQ signals, the signals may experience fixed offsets in the constellation diagram due to phase rotation (such as the four common phase ambiguities of 0°, 90°, 180°, and 270° in QPSK modulation). Therefore, after obtaining at least two multiplexed signals, each multiplexed signal can be phase rotated by different angles to obtain at least two rotated signals, which can be used to restore the offset resampled signal.

[0089] There are many ways to perform phase rotation of the multiplexed signal at different angles, such as rotation matrix multiplication, differential encoding / decoding, pilot-assisted method, etc. The present invention does not limit the method of performing phase rotation of each multiplexed signal at different angles.

[0090] Step 303: Determine a second target data sequence corresponding to each resampled signal based on at least four rotated signals corresponding to each resampled signal, wherein the rotation angle of the rotated signal corresponding to the second target data sequence points to a correct restored phase.

[0091] It should be noted that after obtaining at least four rotated signals corresponding to each resampled signal, the second target data sequence corresponding to each resampled signal can be determined in a variety of ways, for example, it can be determined based on peak correlation detection, it can be determined based on synchronization head correlation, or it can be determined based on a comprehensive evaluation of the eye diagram opening, etc. The present invention does not limit the method of determining the second target data sequence corresponding to each resampled signal based on the at least four rotated signals corresponding to each resampled signal.

[0092] Step 304: Determine the first target data sequence according to the second target data sequence corresponding to each of the resampled signals.

[0093] It should be noted that after obtaining the second target data sequence corresponding to each resampled signal, the first target data sequence can be determined using a variety of methods, such that the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment and the phase is correctly recovered. For example, the determination can be based on peak correlation detection, synchronization header correlation, or a comprehensive evaluation of eye opening. The present invention does not limit the method for determining the first target data sequence based on the second target data sequence corresponding to each resampled signal.

[0094] As can be understood, the present invention utilizes parallel multiplexing for bit synchronization while simultaneously attempting all possible phase ambiguity scenarios for phase resolution. This approach, by simultaneously attempting all possible phase ambiguity scenarios using at least two multiplexed signals, reduces the computational complexity of the phase resolution step and avoids the latency associated with traditional iterative algorithms. Compared to traditional methods, performing bit synchronization and phase resolution in parallel reduces computational complexity, minimizes hardware resource usage, and improves signal processing efficiency.

[0095] In some embodiments, step 302 performs phase rotation of different angles on each of the at least four multiplexed signals corresponding to each of the resampled signals to obtain at least four rotated signals corresponding to each of the resampled signals, which may include: determining the inverse matrices of at least four rotation matrices corresponding to each of the resampled signals, where the inverse matrices of the at least four rotation matrices are used to implement inverse rotations of at least four angles uniformly distributed in the symbol phase space; and multiplying each of the at least four multiplexed signals corresponding to each of the resampled signals by the inverse matrix of the at least four rotation matrices corresponding to each of the resampled signals to obtain the at least four rotated signals corresponding to each of the resampled signals.

[0096] It should be noted that through the inverse operation of the rotation matrix, that is, multiplying each multiplexed signal by the inverse matrix of the corresponding rotation matrix, for example: for QPSK, the rotation matrix may be the inverse matrix of the unit matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse of the 270° rotation matrix. For other modulation modes, the rotation matrix may be the inverse of the unit matrix and the 270° rotation matrix, and phase adjustment can be achieved.

[0097] For example, assume that the mathematical expression of the original signal is S=I+jQ, where S represents the complex signal, I represents the in-phase component of the signal, Q represents the quadrature component of the signal, and j represents the imaginary unit. The phase ambiguity is θ∈{0°,90°,180°,270°}, then the rotated signal is ,in, represents the complex signal after phase rotation, Represents the rotation factor, which indicates the phase rotation of the signal S The inverse matrix operation is to multiply each signal by , try to restore the original phase.

[0098] It's understandable that rotation matrix multiplication has low complexity. For example, it can be efficiently implemented using logic resources in an FPGA, making it more resource-efficient than MLE or Kalman filtering. By reducing computational complexity, signal processing efficiency can be improved.

[0099] Furthermore, the at least four multiplexed signals corresponding to each of the resampled signals include four multiplexed signals, and the inverse matrices of the at least four rotation matrices corresponding to each of the resampled signals include the inverse matrices of four rotation matrices, and the inverse matrices of the four rotation matrices include the inverse matrix of the unit matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0100] It should be noted that in QPSK modulation, the phase ambiguity is θ∈{0°, 90°, 180°, 270°}, so the four-way resampled signal can be copied, and the four-way multiplexed signal can be multiplied by the inverse matrix of the unit matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix for phase recovery.

[0101] In some embodiments, step 303 determines the second target data sequence corresponding to each resampled signal based on the at least four rotated signals corresponding to each resampled signal, and may include: demodulating each of the at least four rotated signals corresponding to each resampled signal to obtain at least four second data sequences corresponding to each resampled signal; performing correlation detection on each of the at least four second data sequences corresponding to each resampled signal with a preset synchronization header to obtain at least four second detection results corresponding to each resampled signal; determining that the second data sequence corresponding to the second target detection result among the at least four second detection results corresponding to each resampled signal is the second target data sequence corresponding to each resampled signal, and the second target detection result is a second detection result among the at least four second detection results indicating that the correlation with the preset synchronization header meets a preset correlation requirement.

[0102] It should be noted that by demodulating each rotated signal separately (such as QPSK demodulation), at least four second data sequences can be obtained. After obtaining at least four second data sequences, the at least four second data sequences can be screened to screen out the second target data sequence corresponding to the signal with correct phase rotation as the result output. The sequence screening method can adopt synchronization head correlation detection, cyclic redundancy check method, bit error rate estimation method, etc. The present invention adopts the synchronization head selection method to determine the second target data sequence, and presets a known synchronization head in the frame structure. The preset synchronization head can be a fixed bit sequence. By calculating the correlation between each demodulated second data sequence and the synchronization head, the one with the highest correlation is selected as the final output, and it is determined that the corresponding phase ambiguity has been correctly resolved, thereby completing the phase ambiguity resolution. The correlation can be calculated by using the method of cross-correlation operation peak detection, etc.

[0103] It can be understood that by directly selecting the best phase by utilizing the strong correlation of the synchronization head, no iterative convergence is required, and the rapid convergence of the phase ambiguity solution operation is achieved, thereby improving the signal processing efficiency.

[0104] In some embodiments, step 304 determines the first target data sequence based on the second target data sequence corresponding to each resampled signal, and may include: performing correlation detection on the second target data sequence corresponding to each resampled signal with a preset synchronization header to obtain at least two third detection results corresponding to the at least two resampled signals; determining that the second target data sequence corresponding to the third target detection result among the at least two third detection results corresponding to the at least two resampled signals is the first target data sequence, and the third target detection result is a third detection result among the at least two third detection results indicating that the correlation with the preset synchronization header meets a preset correlation requirement.

[0105] It should be noted that after obtaining the second target data sequence corresponding to each resampled signal, it is necessary to determine the first target data sequence at the optimal sampling time from at least two resampled signals. This can be determined by selecting a synchronization header. A known synchronization header is preset in the frame structure. The preset synchronization header can be a fixed bit sequence. The bit synchronization step can be completed by calculating the correlation between the second target data sequence corresponding to each resampled signal and the synchronization header, selecting the one with the highest correlation as the final output, and determining the corresponding delay as the optimal sampling time. The correlation calculation can be performed using methods such as cross-correlation peak detection.

[0106] It can be understood that the second target data sequence corresponding to each resampled signal is the data sequence with correct phase ambiguity resolution. The strong correlation of the synchronization head is then used to directly select the sequence of the optimal sampling time without iterative convergence, thereby achieving rapid convergence of phase ambiguity resolution operations and bit synchronization operations, and improving signal processing efficiency.

[0107] Figure 6 This is the first part of the schematic diagram of the multi-path parallel bit synchronization and phase ambiguity resolution process provided by the present invention. Figure 7 This is the second part of the schematic diagram of the multi-channel parallel bit synchronization and phase ambiguity resolution process provided by the present invention. Since the multi-channel parallel bit synchronization and phase ambiguity resolution process flow chart is relatively large, it is divided into Figure 6 and Figure 7 Show together. Figure 6 The 1st to 16th output signals are Figure 7 The 1st to 16th input signals are connected accordingly.

[0108] like Figure 6 and Figure 7 As shown in the figure, all possible sampling point offsets and phase ambiguity scenarios are simultaneously attempted through parallel multi-path processing. The optimal sampling moment and correct phase are quickly determined by using resampling with different time delays, rotation matrix inversion, and synchronization header correlation detection, ultimately achieving bit synchronization and phase ambiguity resolution. The overall process includes:

[0109] 1. Input signal processing.

[0110] (1) I / Q signal after matched filtering.

[0111] The baseband signal at the receiving end is matched filtered (to eliminate noise and maximize the signal-to-noise ratio) to obtain clean I (In-phase) and Q (Quadrature) signals.

[0112] (2) N-fold extraction.

[0113] If the signal is oversampled (e.g., 4x oversampled), decimation can be used to reduce the data rate while still maintaining sufficient sampling accuracy. For example: 4x oversampled → 4 samples per symbol remain after decimation.

[0114] 2. Copy into four paths.

[0115] The signal is multiplexed into 4 channels, each corresponding to a different sampling time (for bit synchronization) and phase rotation (for phase ambiguity resolution).

[0116] 3. Perform bit synchronization and phase ambiguity analysis on each channel.

[0117] The first path: the first sampling point without delay, divided into four paths, the first path is multiplied by the 270-degree rotation matrix , the signal is transformed into (Q1, -I1), and the signal is demodulated into (q1, -i1); the second path is multiplied by the 180-degree rotation matrix , the signal is transformed into (-I1, -Q1), the signal is demodulated into (-i1, -q1); the third path is multiplied by the 90-degree rotation matrix , the signal is transformed into (-Q, I), and the signal is demodulated into (-q, i); the fourth path is multiplied by the 0-degree rotation matrix , the signal is transformed into (I1, Q1), and the signal is demodulated into (i1, q1); the synchronization head correlation calculation is performed on (q1, -i1), (-i1, -q1), (-q1, i1) and (i1, q1), and the signal with the correlation greater than the threshold and the largest correlation is selected, otherwise the default first signal is selected to obtain the signal (i1', q1').

[0118] The second path: Delay one sampling period T / 4, that is, the second sampling point, is divided into four paths, and the first path is multiplied by the 270-degree rotation matrix , the signal is transformed into (Q2, -I2), and the signal is demodulated into (q2, -i2); the second path is multiplied by the 180-degree rotation matrix , the signal is transformed into (-I2, -Q2), the signal is demodulated into (-i2, -q2); the third path is multiplied by the 90-degree rotation matrix , the signal is transformed into (-Q2, I2), and the signal is demodulated into (-q2, i2); the fourth path is multiplied by the 0-degree rotation matrix , the signal is transformed into (I2, Q2), and the signal is demodulated into (i2, q2); the synchronization head correlation calculation is performed on (q2, -i2), (-i2, -q2), (-q2, i2) and (i2, q2), and the signal with the correlation greater than the threshold and the largest correlation is selected, otherwise the default first signal is selected to obtain the signal (i2', q2').

[0119] The third path: Delay two sampling cycles T / 4, that is, the third sampling point, is divided into four paths, and the first path is multiplied by the 270-degree rotation matrix , the signal is transformed into (Q3, -I3), and the signal is demodulated into (q3, -i3); the second path is multiplied by the 180-degree rotation matrix , the signal is transformed into (-I3, -Q3), the signal is demodulated into (-i3, -q3); the third path is multiplied by the 90-degree rotation matrix , the signal is transformed into (-Q3, I3), the signal is demodulated into (-q3, i3); the four-way multiplication is 0 degree rotation matrix , the signal is transformed into (I3, Q3), and the signal is demodulated into (i3, q3); the synchronization head correlation calculation is performed on (q3, -i3), (-i3, -q3), (-q3, i3) and (i3, q3). If the correlation is greater than the threshold, the signal with the largest correlation is selected. Otherwise, the default first channel is selected to obtain the signal (i3', q3').

[0120] The fourth path: Delay three sampling cycles T / 4, that is, the fourth sampling point, is divided into four paths, and the first path is multiplied by the 270-degree rotation matrix , the signal is transformed into (Q4, -I4), and the signal is demodulated into (q4, -i4); the second path is multiplied by the 180-degree rotation matrix , the signal is transformed into (-I4, -Q4), the signal is demodulated into (-i4, -q4); the third path is multiplied by the 90-degree rotation matrix , the signal is transformed into (-Q4, I4), the signal is demodulated into (-q4, i4); the fourth path is multiplied by the 0 degree rotation matrix , the signal is transformed into (I4, Q4), and the signal is demodulated into (i4, q4); the synchronization head correlation calculation is performed on (q4, -i4), (-i4, -q4), (-q4, i4) and (i4, q4). If the correlation is greater than the threshold, the signal with the largest correlation is selected. Otherwise, the default first channel is selected to obtain the signal (i4', q4').

[0121] 4. Frame synchronization.

[0122] Perform natural alignment of (i1', q1'), (i2', q2'), (i3', q3'), and (i4', q4') using a period of T. Then, perform synchronization header correlation calculation. Select the signal with the highest correlation greater than the threshold. Otherwise, select the first signal by default, resulting in signal (i'', q''). Select the signal with a synchronization header correlation greater than the threshold to obtain the frame synchronization signal.

[0123] In the above embodiment, each signal path is multiplied by the 0°, 90°, 180°, and 270° inverse rotation matrices to correct for possible phase offsets. Each path is delayed by different sampling points (0, T / 4, T / 2, and 3T / 4) to find the optimal sampling time. A synchronization header correlation calculation calculates the correlation between the demodulated data and the known synchronization header to select the most likely correct path. Signal synchronization is ensured by natural alignment under the new sampling period (T). The start of a data frame is confirmed when the correlation exceeds a threshold.

[0124] As can be understood, parallel processing simultaneously tries all possible phases and sampling points, avoiding the convergence delays associated with traditional iterative methods. Using rotation matrix multiplication, it can be efficiently implemented in FPGAs using DSP, with low complexity and greater resource efficiency than MLE / Kalman filtering. It directly optimizes the synchronization headers by leveraging their strong correlation, eliminating the need for iterative adjustments and achieving rapid synchronization. Furthermore, a modular design allows for independent optimization of the phase ambiguity resolution and bit synchronization modules, making them suitable for FPGA pipeline implementation. Compared to traditional methods (such as MLE and Gardner loops), this approach offers lower computational complexity, faster convergence, and reduced hardware resource usage, making it particularly suitable for high-speed, real-time communication systems.

[0125] Based on the foregoing embodiments, an embodiment of the present invention provides a signal processing device, wherein each module included in the device and each unit included in each module can be implemented by a processor; of course, they can also be implemented by a specific logic circuit; during implementation, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or an FPGA (FPGA), etc.

[0126] The signal processing device provided by the present invention is described below. The signal processing device described below and the signal processing method described above can be referenced to each other.

[0127] Figure 8 Schematic diagram of the structure of the signal processing device provided by the present invention. Figure 8 As shown, the apparatus 400 includes a signal multiplexing module 401, a signal delay module 402, and a sequence selection module 403, wherein:

[0128] A signal multiplexing module 401 is configured to multiplex input signals to obtain at least two parallel signals, wherein the input signals are obtained by oversampling and matching filtering in-phase and quadrature signals;

[0129] a signal delay module 402 configured to resample each of the at least two parallel signals with different delay times to obtain at least two resampled signals, wherein the different delay times are used to cover periodically evenly distributed points in a symbol period corresponding to the input signal;

[0130] The sequence selection module 403 is configured to determine a first target data sequence according to the at least two resampled signals, wherein the delay time of the resampled signals corresponding to the first target data sequence points to a correct sampling moment.

[0131] In some embodiments, the signal delay obtaining module 402 includes a delay generating unit and a delay implementing unit, wherein:

[0132] a delay generating unit, configured to determine at least two delay units, wherein the at least two delay units are configured to generate at least two phase delays uniformly distributed within a symbol period;

[0133] The delay implementation unit is used to pass each parallel signal of the at least two parallel signals through a corresponding delay unit of the at least two delay units to obtain the at least two resampled signals.

[0134] In some embodiments, the at least two parallel signals include four parallel signals, the at least two delay units include four delay units, and the four delay units include no delay unit, a quarter symbol period delay unit, a half symbol period delay unit, and a three-quarter symbol period delay unit.

[0135] In some embodiments, the sequence selection module 403 is specifically used to: demodulate each of the at least two resampled signals to obtain at least two first data sequences; perform correlation detection on each of the at least two first data sequences with a preset synchronization head to obtain at least two first detection results; determine that the first data sequence corresponding to the first target detection result in the at least two first detection results is the first target data sequence, and the first target detection result is a first detection result in the at least two first detection results indicating that the correlation with the preset synchronization head meets the preset correlation requirement.

[0136] In some embodiments, the sequence selection module 403 includes a signal multiplexing unit, a phase rotation unit, a sequence determination unit and a sequence selection unit, wherein:

[0137] The signal multiplexing unit is configured to perform signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal;

[0138] The phase rotation unit is configured to perform phase rotation of different angles on each of the at least four multiplexed signals corresponding to each resampled signal, to obtain at least four rotated signals corresponding to each resampled signal, wherein the phase rotation of different angles is configured to cover all phase ambiguity angles corresponding to the input signal;

[0139] The sequence determination unit is configured to determine a second target data sequence corresponding to each resampled signal based on at least four rotated signals corresponding to each resampled signal, wherein the rotation angle of the rotated signal corresponding to the second target data sequence points to a correct restored phase;

[0140] The sequence selection unit is configured to determine the first target data sequence according to the second target data sequence corresponding to each of the resampled signals.

[0141] In some embodiments, the phase rotation unit is specifically used to: determine the inverse matrices of at least four rotation matrices corresponding to each resampled signal, and the inverse matrices of the at least four rotation matrices are used to implement inverse rotations of at least four angles uniformly distributed in the symbol phase space; multiply each of the at least four multiplexed signals corresponding to each resampled signal by the inverse matrix of the rotation matrix corresponding to the at least four rotation matrices corresponding to each resampled signal, to obtain at least four rotated signals corresponding to each resampled signal.

[0142] In some embodiments, the at least four multiplexed signals corresponding to each of the resampled signals include four multiplexed signals, and the inverse matrices of the at least four rotation matrices corresponding to each of the resampled signals include the inverse matrices of four rotation matrices, and the inverse matrices of the four rotation matrices include the inverse matrix of the unit matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0143] In some embodiments, the sequence determination unit is specifically used to: demodulate each of the at least four rotated signals corresponding to each resampled signal, respectively, to obtain at least four second data sequences corresponding to each resampled signal; perform correlation detection on each of the at least four second data sequences corresponding to each resampled signal, respectively, with a preset synchronization head, to obtain at least four second detection results corresponding to each resampled signal; determine that the second data sequence corresponding to the second target detection result among the at least four second detection results corresponding to each resampled signal is the second target data sequence corresponding to each resampled signal, and the second target detection result is a second detection result among the at least four second detection results indicating that the correlation with the preset synchronization head meets a preset correlation requirement.

[0144] In some embodiments, the sequence selection unit is specifically used to: perform correlation detection on the second target data sequence corresponding to each resampled signal with a preset synchronization header to obtain at least two third detection results corresponding to the at least two resampled signals; determine that the second target data sequence corresponding to the third target detection result in the at least two third detection results corresponding to the at least two resampled signals is the first target data sequence, and the third target detection result is a third detection result in the at least two third detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0145] In an embodiment of the present invention, a multi-channel signal parallel and multi-delay resampling method is used to attempt to cover all possible available sampling points to achieve bit synchronization, thereby reducing the computational complexity of the bit synchronization step, thereby improving signal processing efficiency and reducing the demand for hardware resources.

[0146] Figure 9 This is a schematic diagram of the physical structure of the FPGA provided by the present invention. Figure 9As shown, the FPGA may include: a processor 510, a communications interface 520, a memory 530, and a communications bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other via the communications bus 540. The processor 510 may call logic instructions in the memory 530 to execute a signal processing method, which includes: multiplexing an input signal to obtain at least two parallel signals, wherein the input signal is obtained by oversampling and matching filtering an in-phase orthogonal signal; resampling each of the at least two parallel signals with a different delay time to obtain at least two resampled signals, wherein the different delay times are used to cover periodically evenly distributed points in a symbol period corresponding to the input signal; and determining a first target data sequence based on the at least two resampled signals, wherein the delay time of the resampled signal corresponding to the first target data sequence points to a correct sampling instant.

[0147] Furthermore, the logic instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0148] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0149] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A signal processing method, characterized in that: include: Performing signal multiplexing on an input signal to obtain at least two parallel signals, wherein the input signal is obtained by oversampling and matching filtering an in-phase orthogonal signal; Resampling each of the at least two parallel signals with different delay times to obtain at least two resampled signals, wherein the different delay times are used to cover periodically evenly distributed points in a symbol period corresponding to the input signal; Determine a first target data sequence according to the at least two resampled signals, wherein the delay time of the resampled signals corresponding to the first target data sequence points to a correct sampling moment; The determining of a first target data sequence according to the at least two resampled signals includes: performing signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal; performing a phase rotation of a different angle on each of the at least four multiplexed signals corresponding to each of the resampled signals to obtain at least four rotated signals corresponding to each of the resampled signals, wherein the phase rotation of the different angles is used to cover all possible phase ambiguity angles corresponding to the input signal; determining a second target data sequence corresponding to each resampled signal according to at least four rotated signals corresponding to each resampled signal, wherein a rotation angle of the rotated signal corresponding to the second target data sequence points to a correct restored phase; The first target data sequence is determined according to the second target data sequence corresponding to each of the resampled signals.

2. The signal processing method according to claim 1, wherein: The resampling of each of the at least two parallel signals with different delay times to obtain at least two resampled signals includes: determining at least two delay units, wherein the at least two delay units are configured to generate at least two time delays uniformly distributed within a symbol period; Each of the at least two parallel signals is passed through a corresponding delay unit in the at least two delay units to obtain the at least two resampled signals.

3. The signal processing method according to claim 2, wherein: The at least two parallel signals include four parallel signals, the at least two delay units include four delay units, and the four delay units include no delay unit, a quarter symbol period delay unit, a half symbol period delay unit, and a three-quarter symbol period delay unit.

4. The signal processing method according to claim 1, wherein: The determining of a first target data sequence according to the at least two resampled signals includes: Demodulating each of the at least two resampled signals to obtain at least two first data sequences; Performing correlation detection on each of the at least two first data sequences and a preset synchronization header to obtain at least two first detection results; Determine that a first data sequence corresponding to a first target detection result among the at least two first detection results is the first target data sequence, and the first target detection result is a first detection result among the at least two first detection results indicating that a correlation with the preset synchronization head meets a preset correlation requirement.

5. The signal processing method according to claim 1, wherein: The performing phase rotation of each of the at least four multiplexed signals corresponding to each of the resampled signals at different angles to obtain at least four rotated signals corresponding to each of the resampled signals includes: Determine the inverse matrices of at least four rotation matrices corresponding to each resampled signal, wherein the inverse matrices of the at least four rotation matrices are used to implement inverse rotations of at least four angles uniformly distributed in the symbol phase space; Each of the at least four multiplexed signals corresponding to each of the resampled signals is multiplied by the inverse matrix of the at least four rotation matrices corresponding to each of the resampled signals to obtain at least four rotated signals corresponding to each of the resampled signals. The signal processing method according to claim 5 , wherein: The at least four multiplexed signals corresponding to each resampled signal include four multiplexed signals, and the at least four inverse matrices of the rotation matrices corresponding to each resampled signal include the inverse matrices of four rotation matrices, and the inverse matrices of the four rotation matrices include the inverse matrix of the unit matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

7. The signal processing method according to claim 1, wherein: The determining, according to the at least four rotated signals corresponding to each of the resampled signals, a second target data sequence corresponding to each of the resampled signals, includes: Demodulating each of the at least four rotated signals corresponding to each of the resampled signals to obtain at least four second data sequences corresponding to each of the resampled signals; performing correlation detection on each of the at least four second data sequences corresponding to each of the resampled signals and a preset synchronization header, to obtain at least four second detection results corresponding to each of the resampled signals; Determine that a second data sequence corresponding to a second target detection result among the at least four second detection results corresponding to each of the resampled signals is the second target data sequence corresponding to each of the resampled signals, and the second target detection result is a second detection result among the at least four second detection results indicating that the correlation with the preset synchronization head meets a preset correlation requirement.

8. A signal processing device, characterized in that: include: A signal multiplexing module, configured to multiplex input signals to obtain at least two parallel signals, wherein the input signals are obtained by oversampling and matching filtering in-phase and quadrature signals; a signal delay module, configured to resample each of the at least two parallel signals with different delay times to obtain at least two resampled signals, wherein the different delay times are used to cover periodically evenly distributed points in a symbol period corresponding to the input signal; a sequence selection module, configured to determine a first target data sequence based on the at least two resampled signals, wherein the delay time of the resampled signals corresponding to the first target data sequence points to a correct sampling moment; The sequence selection module includes a signal multiplexing unit, a phase rotation unit, a sequence determination unit and a sequence selection unit, wherein: The signal multiplexing unit is configured to perform signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal; The phase rotation unit is configured to perform phase rotation of different angles on each of the at least four multiplexed signals corresponding to each resampled signal, to obtain at least four rotated signals corresponding to each resampled signal, wherein the phase rotation of different angles is configured to cover all phase ambiguity angles corresponding to the input signal; The sequence determination unit is configured to determine a second target data sequence corresponding to each resampled signal based on at least four rotated signals corresponding to each resampled signal, wherein the rotation angle of the rotated signal corresponding to the second target data sequence points to a correct restored phase; The sequence selection unit is configured to determine the first target data sequence according to the second target data sequence corresponding to each of the resampled signals.

9. An FPGA comprising a memory, a processor, and instructions stored in the memory and executed on the processor, wherein: When the processor executes the instructions, the signal processing method according to any one of claims 1 to 7 is implemented.

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