Vertically stacked 2T0C DRAM (Dynamic Random Access Memory) unit based on oxide semiconductor ring gate transistor and preparation

Abstract

The invention discloses a vertically-stacked 2T0C DRAM (Dynamic Random Access Memory) unit based on an oxide semiconductor ring gate transistor and a preparation method of the vertically-stacked 2T0C DRAM unit. According to the 2T0C DRAM unit, a first metal interconnection layer, a read transistor layer, a second metal interconnection layer, an isolation layer, a write transistor layer and a third metal interconnection layer are sequentially stacked on a substrate from bottom to top, a read transistor and a write transistor are oxide semiconductor transistors of a vertical ring gate structure, and the two transistors are vertically stacked. Compared with a planar transistor, the DRAM unit has more excellent electrical performance, the working voltage and the characteristic size of the DRAM unit are effectively reduced, and the integration density is improved. By adopting the ring gate structure, the gate control capability can be effectively improved, the same charging current as that of a planar transistor can be realized under a relatively low power supply voltage, and the charge leakage in a holding state is reduced, so that the DRAM gives consideration to both ultra-fast writing and ultra-long data holding time. And meanwhile, the vertically stacked structure reduces the area overhead of the DRAM unit and reduces the wiring difficulty.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a vertical stacked 2T0C DRAM cell based on an oxide semiconductor gate-all-around transistor and a preparation method thereof. Background Art

[0002] DRAM (Dynamic Random Access Memory) is the main memory in the current computer architecture. Due to the need for continuous data refreshing and write-back operations, it faces serious power consumption and efficiency problems. The charge in the DRAM storage node is mainly gradually released through the leakage current of the write transistor, resulting in a short data retention time of the DRAM. To improve the data retention time of the stored data, amorphous oxide semiconductor (AOS) with a wide bandgap and ultra-low leakage current has now become the key development direction of DRAM. The wide bandgap characteristic of the oxide semiconductor can greatly suppress the off-state current and reduce the frequency of the DRAM data refreshing and write-back operations. At the same time, the oxide semiconductor has the characteristics of low thermal budget and low stress, providing the basis for 3D stacking. However, due to the high thermal budget of the silicon-based process and the poor stability of the capacitor process in the 1T1C structure, vertical stacking cannot be carried out. Therefore, the amorphous oxide semiconductor has become an ideal material for preparing low-power DRAM. Currently, various micro-nano processing technologies can be used to shorten the channel length of the oxide semiconductor device, reduce the density of interface defect states, and increase the operating current. However, due to the low mobility of the material, there is a large gap between the on-state current and the silicon-based transistor. At the same time, most of the current 2T0C DRAM structures still remain in a simple planar structure, resulting in problems such as a large feature size of the 2T0C DRAM, an excessive driving voltage, and poor gate control under short channels.

[0003] Therefore, DRAM using planar structure transistors needs to turn to gate-all-around transistor DRAM to further improve the gate control ability to suppress the short-channel effect and obtain an ideal subthreshold swing to reduce the operating voltage. At the same time, in terms of structure, it turns to 3D stacked DRAM to further improve the integration density and reduce the size of the 2T0C DRAM cell. The 2T0C DRAM stacked with gate-all-around oxide semiconductor transistors can simultaneously achieve high operation speed, high data retention time, and high integration density. Summary of the Invention

[0004] In order to realize a 2T0C DRAM cell with high operation speed, high data retention time, and high integration density, the present invention provides a vertical stacked 2T0C DARM cell based on an oxide semiconductor gate-all-around transistor and a preparation method thereof.

[0005] In the present invention, oxide semiconductor surround gate transistors are used as the write transistor and the read transistor of the 2T0C DRAM cell to improve the gate control ability, thereby achieving excellent off-state current and on-state current, and optimizing the DRAM retention time and operation speed. At the same time, the oxide semiconductor surround gate transistors are vertically stacked to improve the integration density and reduce the wiring difficulty. The specific technical solutions are as follows:

[0006] A 2T0C DRAM cell with vertically stacked surround gate oxide semiconductor transistors, comprising a substrate and a first metal interconnect layer, a read transistor layer, a second metal interconnect layer, an isolation layer, a write transistor layer, and a third metal interconnect layer that are sequentially stacked on the substrate from bottom to top. Among them, the read transistor in the read transistor layer and the write transistor in the write transistor layer are both oxide semiconductor transistors with a vertical surround gate structure, that is, the oxide semiconductor channel direction of the transistor is perpendicular to the substrate surface, the gate dielectric surrounds the channel, and the source-drain contacts are located on the top and bottom surfaces of the channel; the contact electrodes at both ends of the read transistor channel are respectively connected to the first metal interconnect layer and the second metal interconnect layer, the gate of the read transistor is connected to the source of the write transistor through a via hole in the isolation layer, and the drain of the write transistor is located on the top surface of its channel and is connected to the third metal interconnect layer.

[0007] In the above 2T0C DRAM cell, the via hole in the isolation layer is connected to the source of the write transistor through an interconnect electrode provided on the isolation layer; the first metal interconnect layer is used as the read bit line (when the contact electrode at the lower end of the read transistor channel is defined as the source) or the read word line (when the contact electrode at the lower end of the read transistor channel is defined as the drain), and the corresponding second metal interconnect layer is used as the read word line or the read bit line; the third metal interconnect layer is used as the write bit line, and the gate of the write transistor is connected to the write word line provided in the write transistor layer. That is to say, the gate of the write transistor TW is connected to the write word line WWL, the drain of the write transistor TW is connected to the write bit line WBL; the drain of the read transistor TR is connected to the read word line RWL, the source of the read transistor TR is connected to the read bit line RBL; the gate of the read transistor TR and the source of the write transistor TW are interconnected, thereby realizing the 2T0C memory function.

[0008] In the oxide semiconductor transistor with the vertical surround gate structure, the oxide semiconductor channel material includes but is not limited to In2O3, ZnO, SnO2, ITO, IGZO, IWO, and IZO, etc. The overall process temperature of the present invention may not be higher than 300 °C, and the substrate can use rigid substrates such as glass substrates, silicon substrates, silicon carbide substrates, diamond substrates, or polymer flexible substrates such as polyimide.

[0009] The materials of the isolation layer and the interlayer isolation structure include but are not limited to silicon oxide (SiO2), silicon nitride (SiN x) Insulating materials with stable structures and good heat dissipation, such as aluminum nitride (AlN) vacuum isolation, can also achieve isolation in the interconnect layer through a vacuum structure. The filling material for the through-holes in the isolation layer and the interconnect materials in each layer include, but are not limited to, materials with low resistivity and high thermal conductivity such as Cu, W, Au, Ag, Mo, Pt, etc.

[0010] The present invention also provides a method for preparing a 2T0C DRAM cell with the above-mentioned vertically stacked gate-all-around oxide semiconductor transistors, including the following steps:

[0011] 1) Clean the substrate, and then prepare a first metal interconnect layer on the substrate;

[0012] 2) Prepare an oxide semiconductor transistor with a first-layer vertical gate-all-around structure as the read transistor, wherein the contact electrode located at the bottom surface of the channel of the read transistor is connected to the first metal interconnect layer;

[0013] 3) Prepare a second metal interconnect layer and connect the contact electrode located at the top surface of the channel of the read transistor;

[0014] 4) Deposit an isolation layer, and prepare an interconnection through-hole between the gate of the read transistor and the source of the write transistor in the isolation layer;

[0015] 5) Prepare a second-layer vertical gate-all-around structure oxide semiconductor transistor as the write transistor on the isolation layer;

[0016] 6) Prepare a third metal interconnect layer and the gate interconnection of the second-layer vertical gate-all-around structure oxide semiconductor transistor.

[0017] In some specific embodiments of the present invention, in step 5), first prepare an interconnect electrode connected to the interconnection through-hole, and then prepare an oxide semiconductor transistor with a vertical gate-all-around structure, so that the electrode at the bottom surface of the transistor channel is connected to the interconnect electrode.

[0018] In some specific embodiments of the present invention, when preparing the transistors in steps 2) and 5), first use chemical vapor deposition to prepare a low-κ dielectric layer, and then use inductively coupled plasma etching to open holes in the low-κ dielectric layer; first use physical vapor deposition to prepare the contact electrode at the bottom surface of the channel in the hole, then use atomic layer deposition to prepare the gate and the gate dielectric layer, and use physical vapor deposition or atomic layer deposition to prepare the oxide semiconductor channel; finally, prepare the contact electrode at the top surface of the channel by physical vapor deposition.

[0019] The present invention uses oxide semiconductor gate-all-around transistors as the read and write transistors of a 2T0C DRAM, and vertically stacks and interconnects them in structure, having the following technical advantages:

[0020] 1) Amorphous oxide semiconductors have a large bandgap and a low dielectric constant, enabling extremely low off-state currents and having good short-channel immunity;

[0021] 2) Using a gate-all-around structure helps improve the gate electrostatic control ability, reduce the power supply voltage, increase the write current of the transistor and reduce the off-state leakage current, achieving an ultra-fast operation speed and an extremely long data retention time;

[0022] 3) Low process thermal budget and low mechanical stress help achieve a vertically stacked gate-all-around structure, thereby effectively reducing the operating voltage and feature size of DRAM cells and increasing the integration density; at the same time, the vertically stacked structure reduces the area overhead of DRAM cells and simplifies the wiring difficulty. Description of the Drawings

[0023] Figure 1 Schematic cross-sectional view of the vertically stacked 2T0C DRAM cell structure based on an oxide semiconductor gate-all-around transistor prepared in an embodiment of the present invention. Here, 1 is the substrate, 2 is the read bit line, 3 is the read word line, 4 is the write word line, 5 is the write bit line, 6 is the interconnect electrode, 7 is the interconnect via, and 8 and 9 are the read transistor TR and the write transistor TW, respectively.

[0024] Figure 2 Schematic process step diagram of preparing a vertically stacked 2T0C DRAM cell based on an oxide semiconductor gate-all-around transistor in an embodiment of the present invention. Here, 1 is the substrate, 2 is the read bit line, 3 is the read word line, 4 is the write word line, 5 is the write bit line, 6 is the interconnect electrode, 7 is the interconnect via, 10 is the low-κ dielectric layer, 11 is the source, 12 is the gate, 13 is the high-κ dielectric layer, 14 is the oxide semiconductor channel, and 15 is the drain. Detailed Embodiments

[0025] The following describes, with reference to the drawings, a method for preparing a vertically stacked 2T0C DRAM cell based on an oxide semiconductor gate-all-around transistor provided by the present invention through an embodiment. In the following description, many details are elaborated to fully understand the present invention, but the present invention can be implemented in many other ways different from the description. In summary, the present invention is not limited by the following disclosed embodiments.

[0026] A vertically stacked 2T0C DRAM cell based on an oxide semiconductor vertical gate-all-around device, the structure of which is as Figure 1As shown: A first metal interconnect layer, a read transistor layer, a second metal interconnect layer, an isolation layer, a write transistor layer, and a third metal interconnect layer are sequentially stacked on a substrate 1. The read transistor 8 of the DRAM cell is located in the read transistor layer. The read bit line 2 is disposed on the first metal interconnect layer, and the read word line 3 is disposed on the second metal interconnect layer of the read transistor; the write transistor 9 of the DRAM cell is located in the write transistor layer. The write word line 4 is connected to the gate of the write transistor. The write bit line 5 is located on the third metal interconnect layer. The source of the write transistor is interconnected with the gate of the read transistor through a via hole 7 in the isolation layer to form a storage node of the 2T0C DRAM.

[0027] The manufacturing process flow of the 2T0C DRAM cell is referred to Figure 2 , including:

[0028] The first step: Substrate cleaning

[0029] Select a single-crystal silicon substrate 1 and clean the substrate 1 with standard RCA. First, use RCA-1 to clean the oil stains and organic substances on the substrate 1, and after cleaning, dry it with high-purity nitrogen.

[0030] The second step: Interconnection of the read bit line

[0031] Include process steps such as exposure and physical vapor deposition to complete the interconnection of the read bit line 2 on the substrate 1.

[0032] The third step: Preparation of the read transistor

[0033] Prepare the first-layer oxide semiconductor vertical gate-all-around transistor as the read transistor. Use chemical vapor deposition to deposit SiO2 by chemical vapor deposition on the basis of the second step to form a low-κ dielectric layer 10; use inductively coupled plasma etching with plasma enhancement to open holes in the low-κ dielectric layer 10, and use physical vapor deposition to deposit the source 11, such as Figure 2 shown in (a) of Figure 2 shown in (b) of

[0034] The fourth step: Interconnection of the read word line

[0035] Include process steps such as exposure and physical vapor deposition to complete the interconnection of the read word line 3, as Figure 2 shown in (c) of

[0036] The fifth step: Formation of the interconnection via hole

[0037] Deposit a low-dielectric constant dielectric by chemical vapor deposition as the isolation layer; use inductively coupled plasma etching with plasma enhancement to form a via hole; electroplate metal to fill the via hole, and use chemical mechanical polishing and other process steps to complete the interconnection via hole 7, such asFigure 2 as shown in (d) of

[0038] Step 6: Fabricate the write transistor

[0039] Fabricate the interconnect electrode 6 and the second-layer oxide semiconductor vertical ring gate transistor on the isolation layer as the read transistor. The fabrication method is the same as that of the read transistor, as Figure 2 shown in (e) of

[0040] Step 7: Interconnect the word line and the write bit line

[0041] Complete the interconnection of the word line 4 and the write bit line 5 through process steps including exposure, physical vapor deposition of metal, etc., as Figure 2 shown in (f) of

Claims

1. A vertically stacked 2T0C DRAM cell of a gate-all-around oxide semiconductor transistor, comprising a substrate and a first metal interconnect layer, a read transistor layer, a second metal interconnect layer, an isolation layer, a write transistor layer, and a third metal interconnect layer that are sequentially stacked on the substrate from bottom to top, wherein, The read transistor located in the read transistor layer and the write transistor located in the write transistor layer are both oxide semiconductor transistors with a vertical gate-all-around structure, that is, the oxide semiconductor channel direction of the transistor is perpendicular to the substrate surface, the gate dielectric surrounds the channel, and the source-drain contacts are located on the top and bottom surfaces of the channel; the contact electrodes at both ends of the read transistor channel are respectively connected to the first metal interconnect layer and the second metal interconnect layer, and the gate of the read transistor is connected to the source of the write transistor through a via hole in the isolation layer, and the drain of the write transistor is located on the top surface of its channel and is connected to the third metal interconnect layer.

2. The 2T0C DRAM cell according to claim 1, wherein, The via hole in the isolation layer is connected to the source of the write transistor through an interconnect electrode provided on the isolation layer.

3. The 2T0C DRAM cell according to claim 1, characterized in that, The first metal interconnect layer is a read word line or a read bit line, and correspondingly, the second metal interconnect layer is a read bit line or a read word line; the third metal interconnect layer is a write bit line, and the gate of the write transistor is connected to a write word line provided in the write transistor layer.

4. The 2T0C DRAM cell according to claim 1, characterized in that, The channel material of the oxide semiconductor transistor is selected from: In2O3, ZnO, SnO2, ITO, IGZO, IWO, and IZO.

5. The 2T0C DRAM cell according to claim 1, characterized in that, The substrate is a glass substrate, a silicon substrate, a silicon carbide substrate, a diamond substrate, or a polymer flexible substrate.

6. The 2T0C DRAM cell according to claim 1, characterized in that, The isolation layer and the isolation structures in each layer are insulating materials with good heat dissipation.

7. The 2T0C DRAM cell according to claim 1, wherein The filling material of the via hole in the isolation layer and the interconnect materials in each interconnect layer are materials with low resistivity and high thermal conductivity.

8. The method for manufacturing a 2T0C DRAM cell according to any one of claims 1 to 7, comprising the following steps: 1) Cleaning the substrate, and then preparing the first metal interconnect layer on the substrate; 2) Preparing a first layer of oxide semiconductor transistor with a vertical gate-all-around structure as the read transistor, wherein the contact electrode located at the bottom surface of the read transistor channel is connected to the first metal interconnect layer; 3) Preparing the second metal interconnect layer and connecting the contact electrode located on the top surface of the read transistor channel; 4) Depositing the isolation layer, and preparing an interconnect via hole between the gate of the read transistor and the source of the write transistor in the isolation layer; 5) Preparing a second layer of oxide semiconductor transistor with a vertical gate-all-around structure as the write transistor on the isolation layer; 6) Preparing the third metal interconnect layer and interconnecting the gate of the second layer of oxide semiconductor transistor with a vertical gate-all-around structure.

9. The preparation method according to claim 8, characterized in that, In step 5), first prepare an interconnect electrode connected to the interconnect via hole, and then prepare an oxide semiconductor transistor with a vertical gate-all-around structure, so that the electrode at the bottom surface of the transistor channel is connected to the interconnect electrode.

10. The preparation method according to claim 8, characterized in that, When preparing the transistor in steps 2) and 5), first use chemical vapor deposition to prepare a low-κ dielectric layer, and then use inductively coupled plasma etching to open holes in the low-κ dielectric layer; first use physical vapor deposition to prepare the contact electrode at the bottom surface of the channel in the hole, then use atomic layer deposition to prepare the gate and the gate dielectric layer, and use physical vapor deposition or atomic layer deposition to prepare the oxide semiconductor channel; finally, use physical vapor deposition to prepare the contact electrode on the top surface of the channel.

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