Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and electronic equipment. The invention relates to the technical field of semiconductors. The semiconductor structure comprises a substrate, at least one bit line located on one side of the substrate, and at least one storage unit arranged on the side, away from the substrate, of the bit line. The storage unit comprises a transistor; the transistor comprises a semiconductor column, and the semiconductor column extends in the direction perpendicular to the substrate; the semiconductor column is connected with the bit line; the material of the semiconductor column comprises monocrystalline silicon, and the material of the bit line comprises silicide. According to the embodiment of the invention, the productivity of manufacturing the semiconductor structure can be improved, and the manufacturing cost of the semiconductor structure is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly shrinking, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came into being, the industry has proposed various semiconductor structure designs and process optimizations to meet the requirements of current products. Summary of the Invention

[0004] In view of the deficiencies of the related art, this application provides a semiconductor structure, a manufacturing method thereof, and an electronic device to solve the technical problems of low production capacity and high manufacturing cost existing in the related art.

[0005] In a first aspect, an embodiment of this application provides a semiconductor structure, including a substrate, at least one bit line located on one side of the substrate, and at least one memory cell disposed on a side of the bit line away from the substrate;

[0006] The memory cell includes a transistor; the transistor includes a semiconductor pillar extending in a direction perpendicular to the substrate;

[0007] The semiconductor pillar is connected to the bit line; the material of the semiconductor pillar includes single crystal silicon, and the material of the bit line includes silicide.

[0008] Optionally, multiple bit lines are spaced apart from each other along a second direction and extend along a first direction; the first direction intersects with the second direction and is parallel to the substrate;

[0009] Multiple memory cells are arranged in an array, and each bit line is connected to the semiconductor pillars of the memory cells arranged in the same column along the first direction.

[0010] Optionally, the material of the bit line includes a first metal silicide.

[0011] Optionally, the difference between the lattice constant of the material of the bit line and the lattice constant of the material of the semiconductor pillar is between 0 Å and 0.3 Å.

[0012] Optionally, the first metal silicide includes at least one of nickel disilicide, cobalt disilicide, or titanium disilicide.

[0013] Optionally, the semiconductor structure further includes a capacitor structure; a second metal silicide layer is provided on a side of the semiconductor pillar away from the substrate, and the second metal silicide layer is electrically connected to the capacitor structure.

[0014] Optionally, the material of the semiconductor pillar further includes N-type doping ions, and the doping concentration range of the N-type doping ions is 5×10 17 per cubic centimeter to 1×10 20 per cubic centimeter.

[0015] Optionally, each of the memory cells further includes a gate dielectric layer, a gate, and at least one word line;

[0016] The gate at least partially surrounds the semiconductor pillar, and the gate dielectric layer is disposed between the gate and the semiconductor pillar; the word line is electrically connected to the gates of the memory cells arranged in the same row along a second direction, and the second direction is parallel to the substrate.

[0017] In a second aspect, an embodiment of the present application provides an electronic device including the above semiconductor structure.

[0018] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including:

[0019] Providing a substrate;

[0020] Manufacturing at least one bit line extending along a first direction on one side of the substrate; the first direction is parallel to the substrate;

[0021] Manufacturing an initial semiconductor pillar extending in a direction perpendicular to the substrate on a side of the bit line away from the substrate, and the material of the initial semiconductor pillar includes amorphous silicon;

[0022] Using the bit line as a master, inducing the crystallization of amorphous silicon into single crystal silicon by laser to convert the initial semiconductor pillar into a semiconductor pillar; sequentially forming a gate dielectric layer and a gate to form a transistor of the semiconductor structure.

[0023] Optionally, manufacturing an initial semiconductor pillar extending in a direction perpendicular to the substrate on a side of the bit line away from the substrate includes:

[0024] Manufacturing a first insulating layer covering the bit line and the substrate;

[0025] Manufacturing an insulating stack on a side of the first insulating layer away from the substrate, where the insulating stack includes a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially away from the substrate; patterning the insulating stack and the first insulating layer to obtain an array of first holes, such that the upper surface of a part of the bit line is exposed in the first holes;

[0026] Manufacture the initial semiconductor column within the first hole.

[0027] Optionally, using the bit line as a master, crystallize amorphous silicon into single crystal silicon by laser induction. After converting the initial semiconductor column into a semiconductor column, the method further includes: patterning the third dielectric layer and the second dielectric layer to obtain a transition dielectric structure surrounding the outer periphery of the semiconductor column, and exposing the first dielectric layer;

[0028] Remove the second dielectric layer in the transition dielectric structure to form a first groove;

[0029] Manufacture a gate dielectric layer surrounding the outer periphery of the semiconductor column within the first groove;

[0030] On the side of the first dielectric layer away from the substrate, manufacture a gate surrounding the side of the gate dielectric layer away from the semiconductor column, and at least one word line extending along a second direction.

[0031] Optionally, manufacturing at least one bit line extending along a first direction on one side of the substrate includes:

[0032] Manufacture at least two stacked combined layers on one side of the substrate; each of the combined layers includes a stacked amorphous silicon layer and a first metal layer, and the thickness of the amorphous silicon layer is between 1 times and 4 times the thickness of the first metal layer;

[0033] Anneal the at least two combined layers to convert the at least two combined layers into a first metal silicide layer;

[0034] Pattern the first metal silicide layer to obtain the bit line.

[0035] Optionally, after manufacturing a gate surrounding the side of the gate dielectric layer away from the semiconductor column and at least one word line extending along a second direction on the side of the first dielectric layer away from the substrate, the method further includes:

[0036] Manufacture a second metal layer at the end of the semiconductor column away from the substrate;

[0037] Perform a thermal annealing treatment on the second metal layer to obtain a second metal silicide layer; the second metal silicide layer is used for electrical connection with a capacitor structure.

[0038] The beneficial technical effects brought by the technical solution provided by the embodiments of the present application include:

[0039] The manufacturing method of the semiconductor structure in this application includes: using the bit line as a master template, and inducing the material of the semiconductor pillar to crystallize from amorphous silicon to single crystal silicon by laser, that is, the lattice constant of the bit line in this application is the same as or similar to that of single crystal silicon, so that the semiconductor pillar can be manufactured based on the laser-induced crystallization of amorphous silicon to single crystal silicon. Compared with the scheme of manufacturing the semiconductor pillar based on the epitaxial preparation process, the manufacturing cost can be reduced and the yield can be increased.

[0040] The material of the bit line of the semiconductor structure of this application includes silicide, so that the bit line can be used as a master template, and the semiconductor pillar including amorphous silicon material can be induced to crystallize into single crystal silicon by laser. The process time required to manufacture the semiconductor pillar by the laser-induced method in this application is shorter and the manufacturing efficiency is higher, so that the production capacity can be increased and the manufacturing cost can be reduced; in addition, both the bit line and the semiconductor pillar are made of silicon, and their lattice constants are the same or similar, so that the contact resistance between the two can be reduced.

[0041] Additional aspects and advantages of this application will be given in part in the following description, which will become apparent from the following description, or will be understood through the practice of this application. Brief Description of the Drawings

[0042] The above-mentioned and / or additional aspects and advantages of this application will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0043] Figure 1 It is a top view schematic diagram of a semiconductor structure provided by an embodiment of this application after removing the film layers above the word line;

[0044] Figure 2 It is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of this application perpendicular to the substrate in the first direction;

[0045] Figure 3 It is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of this application perpendicular to the substrate in the second direction;

[0046] Figure 4 It is a schematic flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of this application;

[0047] Figure 5 is Figure 4 a schematic flowchart of each sub-step of step S101 in;

[0048] Figure 6 is Figure 4 a schematic flowchart of each sub-step of step S102 in;

[0049] Figure 7Schematic flow chart of steps S31 to S34 further included after step S103 in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0050] Figures 8 to 37 Schematic diagrams of intermediate structures obtained in each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0051] Description of reference numerals:

[0052] 1 - Substrate; 11 - Initial semiconductor pillar;

[0053] 2 - Semiconductor pillar; 20 - Initial semiconductor pillar; 21 - First source / drain region; 22 - Channel region; 23 - Second source / drain region; 24 - Second metal silicide layer;

[0054] 3 - Bit line; 31 - Amorphous silicon layer; 32 - First metal layer; 33 - First metal silicide layer;

[0055] 4 - Gate dielectric layer;

[0056] 5 - Gate; 51 - Fourth metal layer;

[0057] 6 - Word line;

[0058] 71 - Capacitor structure; 711 - First electrode; 712 - Second electrode; 713 - Dielectric layer; 72 - Metal plug; 73 - Third metal layer;

[0059] 8 - Insulating stack; 81 - First dielectric layer; 82 - Second dielectric layer; 83 - Third dielectric layer; 84 - First hole; 85 - First groove;

[0060] 91 - First insulating layer; 92 - Second isolation layer; 93 - Second insulating layer; 94 - First isolation layer; 95 - Second hole. Detailed implementation manners

[0061] The embodiments of the present application will be described below with reference to the accompanying drawings in the present application. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0062] Those skilled in the art of the present technology can understand that, unless specifically stated otherwise, the singular forms "a", "an", "the" and "said" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application means the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the art of the present technology. The term "and / or" used herein means at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0063] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0064] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. It should be noted that the following embodiments can be referred to, learned from or combined with each other. For the same terms, similar features and similar implementation steps in different embodiments, they will not be described repeatedly.

[0065] An embodiment of the present application provides a semiconductor structure, see Figures 1 to 3 , including a substrate 1, at least one bit line 3 located on one side of the substrate 1, and at least one memory cell disposed on the side of the bit line away from the substrate 1.

[0066] The memory cell includes a transistor; the transistor includes a semiconductor pillar 2, and the semiconductor pillar 2 extends in a direction perpendicular to the substrate 1.

[0067] The semiconductor pillar 2 is connected to the bit line 3; the material of the semiconductor pillar 2 includes single crystal silicon, and the material of the bit line 3 includes silicide.

[0068] It can be understood that the semiconductor pillar 2 includes a first source / drain region 21, a channel region 22 and a second source / drain region 23 arranged in sequence. The first source / drain region 21 or the second source / drain region 23 is disposed on the side of the channel region 22 close to the substrate 1. In the present application, the first source / drain region 21 is disposed on the side of the channel region 22 close to the substrate 1, and the second source / drain region 23 is disposed on the side of the channel region 22 away from the substrate 1 as an example for specific introduction. In some embodiments, Figure 1A structural schematic diagram of a transistor provided by an embodiment of the present application. Since the material of the bit line 3 includes silicide, the semiconductor column 2 can use the bit line as a master template, and the semiconductor column 2 is induced by laser, so that its material crystallizes from amorphous silicon into single crystal silicon. That is, the lattice constant of the bit line in the present application is the same as or similar to the lattice constant of single crystal silicon. Therefore, the semiconductor column 2 can be manufactured based on the laser-induced crystallization of amorphous silicon into single crystal silicon. Compared with the scheme of manufacturing a semiconductor column based on an epitaxial preparation process, the process time required to manufacture a semiconductor column by the laser-induced method in the present application is shorter and the manufacturing efficiency is higher, so that the production capacity can be increased and the manufacturing cost can be reduced. In addition, the materials of the bit line 3 and the semiconductor column 2 both include silicon, and their lattice constants are the same or similar, so that the contact resistance between the two can be reduced.

[0069] Specifically, the range of the lattice constant of the material of the bit line 3 can be from 4.89 Å to 5.97 Å. In some embodiments, the lattice constant of the material of the bit line can be (Å). For example, the material of the bit line can be nickel disilicide (NiSi2).

[0070] Since the lattice constant of single crystal silicon (c-Si) is The lattice constant of nickel disilicide (NiSi2) is The lattice mismatch between nickel disilicide and single crystal silicon is extremely small, so the formed crystalline silicon is very similar to single crystal silicon, which can improve the device mobility and increase the drive current.

[0071] Specifically, multiple bit lines 3 are spaced apart from each other along the second direction B-B and extend along the first direction A-A; the first direction A-A intersects the second direction B-B and is parallel to the substrate.

[0072] Multiple memory cells are arranged in an array, and each bit line 3 is connected to the semiconductor columns 2 of the memory cells arranged in the same column along the first direction A-A.

[0073] In this embodiment, the material of the bit line 3 includes a first metal silicide.

[0074] Optionally, the difference between the lattice constant of the material of the bit line 3 and the lattice constant of the material of the semiconductor column 2 is between 0 Å and 0.3 Å. In other words, the semiconductor column 2 can be obtained by laser induction using the bit line 3 as a master template, so that the difference between the lattice constant of the material of the bit line 3 and the lattice constant of the material of the semiconductor column 2 is small.

[0075] Specifically, in some embodiments, the first metal silicide may include nickel disilicide, cobalt disilicide.

[0076] Since the lattice constant of cobalt disilicide (CoSi2) is And the lattice constant of single crystal silicon (c-Si) is Therefore, the lattice mismatch between cobalt disilicide and single-crystalline silicon is extremely small. Thus, the formed crystalline silicon is very similar to single-crystalline silicon, which can improve the device mobility and enhance the driving current. In addition, nickel disilicide (NiSi2) has been discussed above and will not be elaborated here.

[0077] Optionally, the semiconductor structure may further include a capacitor structure 71; a second metal silicide layer 24 is provided on a side of the semiconductor pillar 2 away from the substrate 1, and the second metal silicide layer 24 is electrically connected to the capacitor structure 71.

[0078] Wherein, the second metal silicide layer may include cobalt disilicide or titanium disilicide.

[0079] Optionally, the capacitor structure 71 is electrically connected to the second metal silicide layer of the semiconductor pillar 2 through a metal plug 72.

[0080] Specifically, the capacitor structure 71 may include a first electrode 711, a dielectric layer 713, and a second electrode 712 that are sequentially away from the semiconductor pillar 2, and the first electrode 711 is electrically connected to the second metal silicide layer 24 of the semiconductor pillar 2 through a metal plug 72.

[0081] Optionally, a third metal layer 73 may further be provided on an outer surface of the metal plug 72, and the third metal layer 73 wraps the metal plug 72. Wherein, the material of the third metal layer 73 may be titanium nitride (TiN).

[0082] Optionally, the material of the semiconductor pillar 2 may further include N-type doping ions, and the doping concentration range of the N-type doping ions is 5×10 17 per cubic centimeter to 1×10 20 per cubic centimeter.

[0083] Specifically, during the manufacturing process of the semiconductor pillar 2, N-type doping ions may be doped simultaneously in the amorphous silicon formation stage. In some embodiments, the doping concentrations of the doping ions in the second source / drain region 23, the first source / drain region 21, and the channel region 22 may be the same, or the doping concentrations of the doping ions in the second source / drain region 23, the first source / drain region 21, and the channel region 22 may be different. The doping concentrations of the doping ions in the source region 23, the drain region 21, and the channel region 22 may be selected according to actual situations.

[0084] Specifically, each memory cell further includes a gate dielectric layer 4, a gate 5, and at least one word line 6.

[0085] The gate 5 at least partially surrounds the semiconductor pillar 2, and a gate dielectric layer 4 is disposed between the gate 5 and the semiconductor pillar 2; the word line 6 is electrically connected to the gates 5 of the respective memory cells arranged in the same row along the second direction B-B, and the second direction B-B is parallel to the substrate 1.

[0086] It should be noted that in some embodiments, the gate 5 and the word line 6 are sequentially disposed on the outer periphery of the channel region 22 of the semiconductor pillar 2. Figure 2 、 Figure 3 The dashed line in does not exist in the actual product, and is only used to illustrate the positional relationship between the gate 5 and the word line 6.

[0087] It should be noted that the first direction A-A intersects the second direction B-B, and the design angle can be 45°, 60°, 90°, 120° or 145°, etc., and can be designed according to actual needs. In some embodiments, the first direction A-A is perpendicular to the second direction B-B, and the design angle is 90°. Based on the same inventive concept, an embodiment of the present application provides an electronic device, and the electronic device includes the semiconductor structure provided in the above embodiment.

[0088] In this embodiment, since the electronic device adopts any one of the semiconductor structures provided in the foregoing embodiments, the principles and technical effects can be referred to the foregoing embodiments, and will not be elaborated herein.

[0089] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.

[0090] It should be noted that the electronic device is not limited to the above several types. Those skilled in the art can, according to actual application requirements, set any one of the semiconductor structures provided in the foregoing embodiments of the present application in different devices, so as to obtain the electronic device provided in the embodiments of the present application.

[0091] Based on the same inventive concept, an embodiment of the present application provides a manufacturing method based on the above semiconductor structure. The flow schematic diagram of the method is as Figure 4 shown, and the method includes the following steps S100 to S103:

[0092] S100: Provide a substrate 1.

[0093] S101: Fabricate at least one bit line 3 extending along the first direction A-A on one side of the substrate 1; the first direction A-A is parallel to the substrate.

[0094] Optionally, step S101 includes the following steps S11 to S13, referring to Figure 5 the flow schematic diagram shown.

[0095] S11: Fabricate at least two stacked composite layers on one side of the substrate 1; each composite layer includes an amorphous silicon layer 31 and a first metal layer 32, and the thickness of the amorphous silicon layer 31 is between 1 times and 4 times the thickness of the first metal layer 32.

[0096] Optionally, the thickness of the amorphous silicon layer 31 is 2 times the thickness of the first metal layer 32. In practical applications, the thickness range of the first metal layer 32 in each composite layer can be 0.5 nm to 1 nm, and the thickness range of the amorphous silicon layer 31 in each composite layer can be 1 nm to 2 nm.

[0097] In some embodiments, Figure 8 is a schematic cross-sectional structure diagram perpendicular to the substrate along the first direction A-A after fabricating at least two stacked composite layers on one side of the substrate 1; Figure 9 is a schematic cross-sectional structure diagram perpendicular to the substrate along the second direction B-B after fabricating at least two stacked composite layers on one side of the substrate 1.

[0098] It should be noted that Figure 8 、 Figure 9 The two composite layers in are only for illustrative purposes. In practical applications, the composite layers can be set according to actual situations. For example, there can be 10 composite layers.

[0099] In this embodiment, the material of the first metal layer 32 can be nickel metal (Ni). Since the thickness ratio of nickel metal to amorphous silicon (a-Si) in each composite layer is 1:2, at least two composite layers can be converted into nickel disilicide through subsequent thermal annealing treatment to obtain the bit lines of nickel disilicide.

[0100] Of course, the material of the first metal layer 32 can also be cobalt metal (Co). Since the thickness ratio of cobalt metal to amorphous silicon (a-Si) in each composite layer is 1:2, at least two composite layers can be converted into cobalt disilicide through subsequent thermal annealing treatment to obtain the bit lines of cobalt disilicide.

[0101] In this embodiment, the thickness of the amorphous silicon layer 31 in each composite layer can be 2 nm, and the thickness of the first metal layer 32 can be 1 nm, and 10 composite layers can be fabricated. Of course, the thicknesses of the amorphous silicon layer 31 and the first metal layer 32 in each composite layer can both be adjusted according to actual situations and are not limited here.

[0102] S12: Perform annealing treatment on at least two composite layers to convert at least two composite layers into a first metal silicide layer 33.

[0103] In this embodiment, Figure 10 is a schematic cross-sectional structure diagram perpendicular to the substrate along the first direction A-A after performing annealing treatment on at least two composite layers to convert at least two composite layers into a first metal silicide layer 33;Figure 11 Schematic cross-sectional view perpendicular to the substrate along the second direction B-B after annealing at least two combined layers so that the at least two combined layers are converted into a first metal silicide layer.

[0104] Among them, the annealing process can be rapid thermal annealing (RTA).

[0105] Optionally, the first metal silicide layer 33 can be nickel disilicide or cobalt disilicide.

[0106] S13: Pattern the first metal silicide layer 33 to obtain the bit line 3.

[0107] Optionally, step S13 may include: fabricating a second initial insulating layer covering the first metal silicide layer 33; patterning the second initial insulating layer, the first metal silicide layer, and the substrate to obtain the bit line 3 and a second insulating layer 93 on the side of the bit line away from the substrate 1, and making the substrate have trenches (bit line steps).

[0108] Specifically, lithography and etching (e.g., dry etching) can be used to pattern the second initial insulating layer, the first metal silicide layer, and the substrate.

[0109] Among them, the material of the second insulating layer 93 can be silicon nitride.

[0110] In this embodiment, Figure 12 Schematic cross-sectional view perpendicular to the substrate along the first direction A-A after patterning the first metal silicide layer 33 to obtain the bit line 3; Figure 13 Schematic cross-sectional view perpendicular to the substrate along the second direction B-B after patterning the first metal silicide layer 33 to obtain the bit line 3.

[0111] S102: Fabricate an initial semiconductor pillar 20 extending in a direction perpendicular to the substrate 1 on the side of the bit line 3 away from the substrate 1, and the material of the initial semiconductor pillar includes amorphous silicon.

[0112] Optionally, steps S21 to S23 below are included in step S102, referring to the Figure 6 schematic process diagram shown.

[0113] S21: Fabricate a first insulating layer 91 covering the bit line 3 and the substrate 1.

[0114] In this embodiment, Figure 14 Schematic cross-sectional view perpendicular to the substrate along the first direction A-A after fabricating the first insulating layer 91 covering the bit line 3 and the substrate 1; Figure 15 Schematic cross-sectional view perpendicular to the substrate along the second direction B-B after fabricating the first insulating layer 91 covering the bit line 3 and the substrate 1.

[0115] In this embodiment, a second initial insulating layer covering the second insulating layer 93 and the substrate 1 can be fabricated, and planarization (CMP) and etch-back are performed to form bit line isolation. The remaining second initial insulating layer and the second insulating layer serve as the first insulating layer 91.

[0116] Among them, the material of the second initial insulating layer can be trisilicon tetranitride. That is, the remaining trisilicon tetranitride after planarization serves as the first insulating layer 91.

[0117] S22: An insulating stack 8 is fabricated on the side of the first insulating layer 91 away from the substrate 1, and the insulating stack 8 and the first insulating layer are patterned to obtain first holes 84 arranged in an array, such that the upper surfaces of some of the bit lines 3 are exposed within the first holes 84.

[0118] In this embodiment, Figure 16 FIG. is a cross-sectional structural view perpendicular to the substrate along the first direction A-A after the insulating stack 8 is fabricated on the side of the first insulating layer 91 away from the substrate 1; Figure 17 FIG. is a cross-sectional structural view perpendicular to the substrate along the second direction B-B after the insulating stack 8 is fabricated on the side of the first insulating layer 91 away from the substrate 1.

[0119] Among them, the insulating stack 8 can include a first dielectric layer 81, a second dielectric layer 82, and a third dielectric layer 83. Specifically, the material of the first dielectric layer 81 can be silicon oxide (e.g., silicon dioxide), the material of the second dielectric layer 82 can be silicon nitride (e.g., trisilicon tetranitride), and the material of the third dielectric layer 83 can be silicon oxide (e.g., silicon dioxide).

[0120] In this embodiment, Figure 18 FIG. is a cross-sectional structural view perpendicular to the substrate along the first direction A-A after the insulating stack 8 is patterned to obtain first holes 84 arranged in an array, such that the upper surfaces of some of the bit lines 3 are exposed within the first holes 84; Figure 19 FIG. is a cross-sectional structural view perpendicular to the substrate along the second direction B-B after the insulating stack 8 is patterned to obtain first holes 84 arranged in an array, such that the upper surfaces of some of the bit lines 3 are exposed within the first holes 84.

[0121] S23: An initial semiconductor pillar 20 is fabricated within the first holes 84, and the material of the initial semiconductor pillar 20 includes amorphous silicon.

[0122] In this embodiment, Figure 20 FIG. is a cross-sectional structural view perpendicular to the substrate along the first direction A-A after the initial semiconductor pillar 20 is fabricated within the first holes 84; Figure 21 FIG. is a cross-sectional structural view perpendicular to the substrate along the second direction B-B after the initial semiconductor pillar 20 is fabricated within the first holes 84.

[0123] Specifically, an amorphous silicon layer is deposited on the side of the insulating stack 8 away from the substrate 1 and within the first hole 84, and the amorphous silicon layer is planarized to remove the amorphous silicon layer on the side of the insulating stack 8 away from the substrate 1, thereby obtaining the initial semiconductor pillar 20.

[0124] Optionally, N-type doping ions can be doped while forming the amorphous silicon layer. For example, the doping concentration range of the N-type doping ions can be from 5×10 17 per cubic centimeter to 1×10 20 per cubic centimeter.

[0125] S103: Using the bit line 3 as a master template, the amorphous silicon is induced to crystallize into single crystal silicon by laser, so that the initial semiconductor pillar 20 is converted into the semiconductor pillar 2; the gate dielectric layer 4 and the gate 5 are sequentially formed to form the transistor of the semiconductor structure.

[0126] In this embodiment, Figure 22 FIG. is a schematic cross-sectional structure view perpendicular to the substrate along the first direction A-A after using the bit line 3 as a master template and inducing the amorphous silicon to crystallize into single crystal silicon by laser, so that the initial semiconductor pillar 20 is converted into the semiconductor pillar 2; Figure 23 FIG. is a schematic cross-sectional structure view perpendicular to the substrate along the second direction B-B after using the bit line 3 as a master template and inducing the amorphous silicon to crystallize into single crystal silicon by laser, so that the initial semiconductor pillar 20 is converted into the semiconductor pillar 2.

[0127] In practical applications, the material of the bit line 3 can be a material with a lattice constant similar to that of single crystal silicon. By way of example, the material of the bit line 3 can be nickel disilicide or cobalt disilicide.

[0128] Since the lattice constant of single crystal silicon (c-Si) is and the lattice constant of nickel disilicide (NiSi2) is the lattice mismatch between nickel disilicide and single crystal silicon is extremely small, so the formed crystalline silicon is very similar to single crystal silicon, thereby being able to improve the device mobility and boost the drive current.

[0129] Since the lattice constant of cobalt disilicide (CoSi2) is while the lattice constant of single crystal silicon (c-Si) is therefore, the lattice mismatch between cobalt disilicide and single crystal silicon is extremely small, so the formed crystalline silicon is very similar to single crystal silicon, thereby being able to improve the device mobility and boost the drive current.

[0130] Optionally, after the above step S103, the manufacturing method of the semiconductor structure may further include the following steps S31 to S34, referring to Figure 7 the flow schematic diagram shown.

[0131] S31: Pattern the third dielectric layer 83 and the second dielectric layer 82 to obtain a transition dielectric structure surrounding the outer periphery of the semiconductor pillar 2, and expose the first dielectric layer 81; the insulating stack includes a first dielectric layer 81, a second dielectric layer 82, and a third dielectric layer 83 that are successively away from the substrate 1.

[0132] In this embodiment, Figure 24 FIG. is a schematic cross-sectional structure perpendicular to the substrate along the first direction A-A after patterning the third dielectric layer 83 and the second dielectric layer 82 to obtain a transition dielectric structure surrounding the outer periphery of the semiconductor pillar 2 to expose the first dielectric layer 81; Figure 25 FIG. is a schematic cross-sectional structure perpendicular to the substrate along the second direction B-B after patterning the third dielectric layer 83 and the second dielectric layer 82 to obtain a transition dielectric structure surrounding the outer periphery of the semiconductor pillar 2 to expose the first dielectric layer 81.

[0133] Among them, the transition dielectric structure includes the patterned third dielectric layer 83 and the patterned second dielectric layer 82.

[0134] For example, a photolithography etching process can be used to pattern the third dielectric layer 83 and the second dielectric layer 82.

[0135] S32: Remove the second dielectric layer 82 in the transition dielectric structure to form a first groove 85.

[0136] In this embodiment, Figure 26 FIG. is a schematic cross-sectional structure perpendicular to the substrate along the first direction A-A after removing the second dielectric layer 82 in the transition dielectric structure to form the first groove 85; Figure 27 FIG. is a schematic cross-sectional structure perpendicular to the substrate along the second direction B-B after removing the second dielectric layer 82 in the transition dielectric structure to form the first groove 85.

[0137] Among them, the first groove 85 surrounds the semiconductor pillar 2 and the opening faces the side of the substrate 1.

[0138] For example, a wet etching or dry etching process can be used to remove the second dielectric layer 82 in the transition dielectric structure to form the first groove 85.

[0139] S33: Fabricate a gate dielectric layer 4 surrounding the outer periphery of the semiconductor pillar 2 in the first groove 85.

[0140] Among them, the material of the gate dielectric layer 4 can be a high-K dielectric layer (HK layer), for example, hafnium silicon oxynitride (HfSiON).

[0141] S34: On the side of the first dielectric layer 81 away from the substrate 1, fabricate a gate 5 surrounding the side of the gate dielectric layer 4 away from the semiconductor pillar 2, and a plurality of word lines 6 spaced apart from each other along the first direction A-A and extending along the second direction B-B.

[0142] Optionally, before step S34, it may further include: fabricating a fourth metal layer 51 on the side of the first dielectric layer 81 away from the substrate 1 and surrounding the side of the gate dielectric layer 4 away from the semiconductor pillar 2. The material of the fourth metal layer 51 may be titanium nitride (TiN).

[0143] Among them, the materials of the gate 5 and the word lines 6 may include tungsten. By embedding titanium nitride between the tungsten and the gate dielectric layer 4, the gate depletion phenomenon can be weakened.

[0144] In this embodiment, Figure 28 is a schematic cross-sectional structure diagram perpendicular to the substrate along the first direction A-A after fabricating the gate dielectric layer 4, the fourth metal layer 51, the gate 5, and the word lines 6; Figure 29 is a schematic cross-sectional structure diagram perpendicular to the substrate along the second direction B-B after fabricating the gate dielectric layer 4, the fourth metal layer 51, the gate 5, and the word lines 6.

[0145] It should be noted that in this embodiment, the gate 5 and the word lines 6 are sequentially arranged on the outer periphery of the semiconductor pillar 2, Figure 28 , Figure 29 the dotted lines in [] do not exist in the actual product, but are only for illustrating the positional relationship between the gate 5 and the word lines 6.

[0146] Optionally, after the above step S34, the manufacturing method of the semiconductor structure may further include:

[0147] S41: Fabricate a second metal layer at one end of the semiconductor pillar 2 away from the substrate 1.

[0148] S42: Perform a thermal annealing treatment on the second metal layer to obtain a second metal silicide layer 24; the second metal silicide layer 24 is used for electrical connection with the capacitor structure 71.

[0149] Among them, the second metal layer may be cobalt metal or titanium metal. Correspondingly, the second metal silicide layer 24 may include cobalt disilicide or titanium disilicide. Taking the second metal layer as cobalt metal as an example, cobalt can be annealed under the condition of 750 degrees Celsius to 900 degrees Celsius to obtain cobalt disilicide.

[0150] Optionally, before the above step S41, the manufacturing method of the semiconductor structure further includes: fabricating a first isolation layer 94 covering the semiconductor pillar 2, the third dielectric layer 83, the first dielectric layer 81, and the word lines 6; patterning the first isolation layer 94 to obtain a second hole 95 exposing the semiconductor pillar 2 and the side of the third dielectric layer 83 away from the substrate 1.

[0151] Step S41 specifically is to fabricate a second metal layer inside the second hole 95 at the end of the semiconductor pillar 2 away from the substrate 1.

[0152] Among them, the material of the first isolation layer 94 can be silicon dioxide.

[0153] In this embodiment, Figure 30 is a schematic cross-sectional structure diagram perpendicular to the substrate along the first direction A-A after fabricating the first isolation layer 94 covering the semiconductor pillar 2, the third dielectric layer 83, the first dielectric layer 81, and the word line 6; Figure 31 is a schematic cross-sectional structure diagram perpendicular to the substrate along the second direction B-B after fabricating the first isolation layer 94 covering the semiconductor pillar 2, the third dielectric layer 83, the first dielectric layer 81, and the word line 6.

[0154] In this embodiment, Figure 32 is a schematic cross-sectional structure diagram perpendicular to the substrate along the first direction A-A after patterning the first isolation layer 94 to obtain the second hole 95 exposing the side of the semiconductor pillar 2 and the third dielectric layer 83 away from the substrate 1; Figure 33 is a schematic cross-sectional structure diagram perpendicular to the substrate along the second direction B-B after patterning the first isolation layer 94 to obtain the second hole 95 exposing the side of the semiconductor pillar 2 and the third dielectric layer 83 away from the substrate 1.

[0155] That is to say, the second hole 95 can expose the source end (i.e., the top surface of the semiconductor pillar on the side away from the substrate). In practical applications, the second hole 95 can be formed by processes such as photolithography and etching.

[0156] In this embodiment, Figure 34 is a schematic cross-sectional structure diagram perpendicular to the substrate along the first direction A-A after thermally annealing the second metal layer to obtain the second metal silicide layer 24; Figure 35 is a schematic cross-sectional structure diagram perpendicular to the substrate along the second direction B-B after thermally annealing the second metal layer to obtain the second metal silicide layer 24.

[0157] Optionally, after thermally annealing the second metal layer to obtain the second metal silicide layer 24, the manufacturing method of the semiconductor structure further includes: fabricating a second isolation layer 92 on the side of the first isolation layer 94 away from the substrate 1 and inside the second hole 95, and planarizing the second isolation layer 92.

[0158] Among them, the material of the second isolation layer 92 can be silicon dioxide.

[0159] In this embodiment, Figure 36Schematic cross-sectional structure diagram perpendicular to the substrate along the first direction A-A after manufacturing the second isolation layer 92 on the side of the first isolation layer 94 away from the substrate 1 and within the second hole 95 and planarizing the second isolation layer 92; Figure 37 Schematic cross-sectional structure diagram perpendicular to the substrate along the second direction B-B after manufacturing the second isolation layer 92 on the side of the first isolation layer 94 away from the substrate 1 and within the second hole 95 and planarizing the second isolation layer 92.

[0160] Optionally, after planarizing the second isolation layer 92, it may further include: manufacturing a metal plug 72 and a capacitor structure 71.

[0161] In this embodiment, Figure 2 Schematic cross-sectional structure diagram perpendicular to the substrate along the first direction after manufacturing the metal plug 72 and the capacitor structure 71; Figure 3 Schematic cross-sectional structure diagram perpendicular to the substrate along the second direction after manufacturing the metal plug 72 and the capacitor structure 71.

[0162] Among them, the capacitor structure 71 is electrically connected to the second metal silicide layer 24 of the semiconductor pillar 2 through the metal plug 72. Specifically, the capacitor structure 71 may include a first electrode 711, a dielectric layer 713, and a second electrode 712 that are sequentially away from the semiconductor pillar 2, and the first electrode 711 is electrically connected to the second metal silicide layer 24 of the semiconductor pillar 2 through the metal plug 72.

[0163] Optionally, a third metal layer 73 may be further provided on the outer surface of the metal plug 72, and the third metal layer 73 wraps the metal plug 72. Among them, the material of the third metal layer 73 may be titanium nitride.

[0164] Both the first electrode 711 and the second electrode 712 may include at least one of titanium nitride and tantalum nitride; the dielectric layer 713 includes stacked zirconia, alumina, and zirconia.

[0165] The beneficial technical effects brought by the technical solution provided in the embodiment of the present application include:

[0166] In the present application, the semiconductor pillar 2 is obtained by using the bit line 3 as a master and inducing the material of the semiconductor pillar 2 to crystallize from amorphous silicon to single crystal silicon by laser. That is, the lattice constant of the bit line 3 in the present application is the same as or similar to that of single crystal silicon. Therefore, the semiconductor pillar 2 can be manufactured based on the laser-induced crystallization of amorphous silicon to single crystal silicon. Compared with the solution of manufacturing the semiconductor pillar 2 based on the epitaxial preparation process, the present application uses the laser-induced method to manufacture the semiconductor pillar, which requires a shorter process time and higher manufacturing efficiency, thereby improving production capacity and reducing manufacturing costs.

[0167] Those skilled in the art can understand that the various operations, methods, steps, measures, and solutions in the processes discussed in this application can be alternated, changed, combined, or deleted. Further, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, those in the prior art that have steps, measures, and solutions in the various operations, methods, and processes disclosed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0168] In the description of this application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the exemplary directions or positional relationships shown in the drawings. It is for the convenience of describing or simplifying the embodiments of this application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to this application.

[0169] The terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0170] In the description of this application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0171] In the description of this specification, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0172] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially in the direction of the arrows, the execution order of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated in this document, in some implementation scenarios of the embodiments of this application, the steps in each process can be executed in other orders according to requirements. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenarios. Some or all of these sub-steps or stages can be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and the embodiments of this application do not limit this.

[0173] The above are only some implementation manners of this application. It should be noted that for those of ordinary skill in the art, without departing from the technical concept of the solution of this application, adopting other similar implementation means based on the technical idea of this application also belongs to the protection scope of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, Comprising a substrate, at least one bit line located on one side of the substrate, and at least one memory cell disposed on the side of the bit line away from the substrate; The memory cell includes a transistor; the transistor includes a semiconductor pillar, and the semiconductor pillar extends in a direction perpendicular to the substrate; The semiconductor pillar is connected to the bit line; the material of the semiconductor pillar includes single crystal silicon, and the material of the bit line includes silicide.

2. The semiconductor structure according to claim 1, characterized in that, Multiple bit lines are spaced apart from each other in a second direction and extend in a first direction; the first direction intersects with the second direction and is parallel to the substrate; Multiple memory cells are arranged in an array, and each bit line is connected to the semiconductor pillars of the memory cells arranged in the same column in the first direction.

3. The semiconductor structure according to claim 1, wherein The material of the bit line includes a first metal silicide.

4. The semiconductor structure according to claim 3, wherein The difference between the lattice constant of the material of the bit line and the lattice constant of the material of the semiconductor pillar is between 0 Å and 0.3 Å.

5. The semiconductor structure according to claim 4, characterized in that, The first metal silicide includes at least one of nickel disilicide, cobalt disilicide or titanium disilicide.

6. The semiconductor structure according to claim 1, wherein It further includes a capacitive structure; a second metal silicide layer is provided on the side of the semiconductor pillar away from the substrate, and the second metal silicide layer is electrically connected to the capacitive structure.

7. The semiconductor structure according to claim 1, wherein The material of the semiconductor column further includes N-type doping ions, and the doping concentration range of the N-type doping ions is 5×10 17 per cubic centimeter to 1×10 20 per cubic centimeter.

8. The semiconductor structure according to claim 1, characterized in that, Each memory cell further includes a gate dielectric layer, a gate and at least one word line; The gate at least partially surrounds the semiconductor pillar, and the gate dielectric layer is disposed between the gate and the semiconductor pillar; the word line is electrically connected to the gates of the memory cells arranged in the same row in the second direction, and the second direction is parallel to the substrate.

9. An electronic device, characterized in that, Comprising the semiconductor structure according to any one of claims 1 to 8.

10. A manufacturing method of a semiconductor structure, characterized in that, Including: Providing a substrate; Fabricating at least one bit line extending in a first direction on one side of the substrate; The first direction is parallel to the substrate; Fabricating an initial semiconductor pillar extending in a direction perpendicular to the substrate on the side of the bit line away from the substrate, and the material of the initial semiconductor pillar includes amorphous silicon; Using the bit line as a master, inducing the crystallization of amorphous silicon into single crystal silicon by laser to convert the initial semiconductor pillar into a semiconductor pillar; sequentially forming a gate dielectric layer and a gate to form the transistor of the semiconductor structure.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein, Fabricating an initial semiconductor pillar extending in a direction perpendicular to the substrate on the side of the bit line away from the substrate, including: Fabricating a first insulating layer covering the bit line and the substrate; Fabricating an insulating stack on the side of the first insulating layer away from the substrate, the insulating stack includes a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially away from the substrate; patterning the insulating stack and the first insulating layer to obtain first holes arranged in an array, so that the upper surfaces of some of the bit lines are exposed in the first holes; Fabricating the initial semiconductor pillar in the first holes.

12. The manufacturing method of the semiconductor structure according to claim 11, characterized in that, After using the bit line as a master and inducing the crystallization of amorphous silicon into single crystal silicon by laser to convert the initial semiconductor pillar into a semiconductor pillar, it further includes: patterning the third dielectric layer and the second dielectric layer to obtain a transition dielectric structure surrounding the outer periphery of the semiconductor pillar and exposing the first dielectric layer; Remove the second dielectric layer in the transition dielectric structure to form a first groove; Fabricate a gate dielectric layer surrounding the outer periphery of the semiconductor pillar within the first groove; On the side of the first dielectric layer away from the substrate, fabricate a gate surrounding the side of the gate dielectric layer away from the semiconductor pillar, and at least one word line extending along a second direction.

13. The manufacturing method of the semiconductor structure according to claim 10, wherein, Fabricate at least one bit line extending along a first direction on one side of the substrate, including: Fabricate at least two stacked composite layers on one side of the substrate; each of the composite layers includes a stacked amorphous silicon layer and a first metal layer, and the thickness of the amorphous silicon layer is between 1 to 4 times the thickness of the first metal layer; Anneal the at least two composite layers to convert the at least two composite layers into a first metal silicide layer; Pattern the first metal silicide layer to obtain the bit line.

14. The method for manufacturing a semiconductor structure according to claim 12, wherein After fabricating a gate surrounding the side of the gate dielectric layer away from the semiconductor pillar, and at least one word line extending along a second direction on the side of the first dielectric layer away from the substrate, further include: Fabricate a second metal layer at the end of the semiconductor pillar away from the substrate; Perform a thermal annealing treatment on the second metal layer to obtain a second metal silicide layer; the second metal silicide layer is used for electrical connection with a capacitor structure.

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