Memory and forming method thereof

Abstract

The invention discloses a memory and a forming method thereof, and the memory comprises a substrate which is provided with one or more projection structures; the floating gate structure is located on the substrate and covers the convex structure, the floating gate structure comprises a first dielectric layer and a first gate layer which are stacked in sequence, and the first dielectric layer covers the top and the side wall of the convex structure and the substrate at the side part of the convex structure in a shape-preserving manner; the control gate structure is located on the floating gate structure, and the control gate structure comprises a second dielectric layer and a second gate layer which are stacked in sequence; and the source-drain doping layer is positioned in the substrate on two sides of the floating gate structure. According to the embodiment of the invention, the writing or erasing speed is increased, the writing or erasing performance is correspondingly improved, the electron tunneling path during writing is different from the electron tunneling path during erasing, and the probability that the first dielectric layer is damaged is correspondingly reduced, so that the service life of the first dielectric layer is prolonged; and the performance of the memory is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a memory and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three major types: logic, memory, and analog circuits, among which storage devices account for a quite large proportion in integrated circuit products. With the development of semiconductor technology and the more extensive application of storage devices, it is necessary to form the storage devices and other devices on a chip simultaneously to form an embedded semiconductor storage device. For example, when embedding the storage device in a central processing unit, it is necessary to make the storage device compatible with the embedded central processing unit platform and maintain the specifications and corresponding electrical properties of the original storage device.

[0003] Generally, it is necessary to make the storage device compatible with an embedded standard logic device. For an embedded semiconductor device, it is usually divided into a logic area and a storage area. The logic area usually includes logic devices, and the storage area includes storage devices. With the development of storage technology, various types of semiconductor memories have emerged, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), One-time Programmable Read Only Memory (OTPROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and Flash.

[0004] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's law, making integrated circuits develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0005] Currently, the performance of memories still needs to be improved. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a memory and a method for forming the same to improve the performance of the memory.

[0007] To solve the above problems, embodiments of the present invention provide a memory, including: a substrate having one or more convex structures; a floating gate structure located on the substrate and covering the convex structures, the floating gate structure including a first dielectric layer and a first gate layer stacked in sequence, the first dielectric layer conformally covering the top and side walls of the convex structures, and the substrate on the side of the convex structures; a control gate structure located on the floating gate structure, the control gate structure including a second dielectric layer and a second gate layer stacked in sequence; and source / drain doping layers located in the substrate on both sides of the floating gate structure.

[0008] Correspondingly, embodiments of the present invention further provide a method for forming a memory, including: providing a substrate having one or more convex structures; forming a floating gate structure covering the convex structures on the substrate, the floating gate structure including a first dielectric layer and a first gate layer stacked in sequence, the first dielectric layer conformally covering the top and side walls of the convex structures, and the substrate on the side of the convex structures; forming a control gate structure on the floating gate structure, the control gate structure including a second dielectric layer and a second gate layer stacked in sequence; and forming source / drain doping layers in the substrate on both sides of the floating gate structure.

[0009] Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

[0010] The memory provided by the embodiments of the present invention includes a substrate having one or more convex structures, a floating gate structure located on the substrate and covering the convex structures, the floating gate structure including a first dielectric layer and a first gate layer stacked in sequence, the first dielectric layer conformally covering the top and side walls of the convex structures, and the substrate on the side of the convex structures. When writing or erasing, under the condition of the same voltage, the electric field intensity at the corner positions of the convex structures is relatively large, and electrons can more easily enter the floating gate structure from the substrate or enter the substrate from the floating gate structure, which is beneficial to improving the writing or erasing speed and correspondingly improving the writing or erasing performance. Moreover, since the substrate has convex structures, electrons enter the floating gate structure through the top corner positions of the convex structures during writing, and electrons enter the substrate through the bottom corner positions of the convex structures during erasing. Therefore, the electron tunneling paths during writing and erasing are different, correspondingly reducing the probability of damage to the first dielectric layer, which is beneficial to improving the service life of the first dielectric layer and further beneficial to improving the performance of the memory.

[0011] In the method for forming a memory provided by an embodiment of the present invention, in the step of providing the substrate, the substrate has one or more protruding structures, and a floating gate structure covering the protruding structures is formed on the substrate. The floating gate structure includes a first dielectric layer and a first gate layer stacked in sequence. The first dielectric layer conformally covers the top and side walls of the protruding structures, as well as the substrate on the side of the protruding structures, so that when writing or erasing, under the condition of the same voltage, the electric field strength at the corner position of the protruding structure is relatively large, and electrons can more easily enter the floating gate structure from the substrate or enter the substrate from the floating gate structure, thereby facilitating the improvement of the writing or erasing speed and correspondingly improving the writing or erasing performance. Moreover, since the substrate has a protruding structure, electrons enter the floating gate structure through the top corner position of the protruding structure during writing, and electrons enter the substrate through the bottom corner position of the protruding structure during erasing. Therefore, the electron tunneling path during writing is different from the electron tunneling path during erasing, correspondingly reducing the probability of damage to the first dielectric layer, thereby facilitating the improvement of the service life of the first dielectric layer and further facilitating the improvement of the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic structural diagram of a memory;

[0013] Figure 2 is Figure 1 a partial structural schematic diagram in area A;

[0014] Figure 3 is a schematic structural diagram of an embodiment of the memory of the present invention;

[0015] Figure 4 is Figure 3 a partial structural schematic diagram in area B;

[0016] Figures 5 to 17 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the memory of the present invention. DETAILED DESCRIPTION

[0017] Currently, the performance of memories still needs to be improved. With reference to a memory, the reasons for the need to improve the performance of memories are analyzed. Figure 1 is a schematic structural diagram of a memory, Figure 2 is Figure 1 a partial structural schematic diagram in area A.

[0018] Refer to Figure 1, the memory includes: a substrate 10; a floating gate structure 20 located on the substrate 10, the floating gate structure 20 includes a first dielectric layer 21 located on the substrate 10, a tunneling layer 22 located on the side of the first dielectric layer on the substrate 10, and a first gate layer 23 covering the first dielectric layer 21 and the tunneling layer 22, the thickness of the first dielectric layer 21 is greater than the thickness of the tunneling layer 22; a control gate structure 30 located on the floating gate structure 20, the control gate structure 30 includes a second dielectric layer 31 and a second gate layer 32 stacked in sequence; source-drain doping layers 40 located in the substrate 10 on both sides of the floating gate structure 20.

[0019] It has been found through research that in order to increase the electron tunneling speed, that is, to improve the write and erase performance, it is usually necessary to increase the operating voltage of the memory or reduce the thickness of the tunneling layer 22. If the operating voltage of the memory is increased, it is often necessary to increase the size of the peripheral devices that supply power to the memory, resulting in a relatively large size of the peripheral devices, and thus the size of the memory is also relatively large. If the thickness of the tunneling layer 22 is reduced, it is easy to make the electron tunneling difficult to control, thus making it difficult to control the write and erase of the memory. Moreover, if the thickness of the tunneling layer 22 is small, it is also easy to increase the probability of damage to the tunneling layer 22, thereby shortening the service life of the memory.

[0020] To solve the above technical problems, an embodiment of the present invention provides a memory, including: a substrate having one or more protruding structures; a floating gate structure located on the substrate and covering the protruding structures, the floating gate structure includes a first dielectric layer and a first gate layer stacked in sequence, the first dielectric layer conformally covers the top and side walls of the protruding structures, and the substrate on the side of the protruding structures; a control gate structure located on the floating gate structure, the control gate structure includes a second dielectric layer and a second gate layer stacked in sequence; source-drain doping layers located in the substrate on both sides of the floating gate structure.

[0021] The memory provided by the embodiment of the present invention includes a substrate, the substrate has one or more convex structures, a floating gate structure located on the substrate and covering the convex structures, the floating gate structure includes a first dielectric layer and a first gate layer stacked in sequence, the first dielectric layer conformally covers the top and side walls of the convex structures, and the substrate on the side of the convex structures, so that when writing or erasing, under the condition of the same voltage, the electric field intensity at the corner position of the convex structures is relatively large, and electrons can more easily enter the floating gate structure from the substrate or enter the substrate from the floating gate structure, thereby facilitating the improvement of the writing or erasing speed and correspondingly improving the writing or erasing performance; moreover, since the substrate has convex structures, when writing, electrons enter the floating gate structure through the top corner position of the convex structures, and when erasing, electrons enter the substrate through the bottom corner position of the convex structures. Therefore, the electron tunneling path during writing is different from the electron tunneling path during erasing, correspondingly reducing the probability of damage to the first dielectric layer, thereby facilitating the improvement of the service life of the first dielectric layer and further facilitating the improvement of the performance of the memory.

[0022] In order to make the above objects, features and advantages of the embodiments of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0023] Figure 3 It is a schematic structural diagram of an embodiment of the memory of the present invention; Figure 4 is Figure 3 A partial structural diagram in region B.

[0024] Among them, in order to clearly show the structure of the memory, Figure 4 the first gate layer, the second dielectric layer and the second gate layer are omitted.

[0025] Referring to Figures 3 to 4 , in this embodiment, the memory includes: a substrate 100, the substrate 100 has one or more convex structures 101; a floating gate structure 110, located on the substrate 100 and covering the convex structures 101, the floating gate structure 110 includes the first dielectric layer 111 and the first gate layer 112 stacked in sequence, the first dielectric layer 111 conformally covers the top and side walls of the convex structures 101, and the substrate 100 on the side of the convex structures 101; a control gate structure 120, located on the floating gate structure 110, the control gate structure 120 includes the second dielectric layer 121 and the second gate layer 122 stacked in sequence; source-drain doping layers 160, located in the substrate 100 on both sides of the floating gate structure 110.

[0026] The substrate 100 is used to provide a process platform for the formation of the memory.

[0027] In this embodiment, the substrate 100 is used to form a non-volatile memory. As an example, the substrate 100 is used to form an EEPROM memory.

[0028] In this embodiment, the substrate 100 includes a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0029] The memory includes a substrate 100 having one or more protruding structures 101, and a floating gate structure 110 located on the substrate 100 and covering the protruding structures 101. The floating gate structure 110 includes the first dielectric layer 111 and the first gate layer 112 stacked in sequence. The first dielectric layer 110 conformally covers the top and side walls of the protruding structure 101 and the substrate 100 on the side of the protruding structure 101, so that when writing or erasing, under the condition of the same voltage, the electric field intensity at the corner position of the protruding structure 101 is relatively large, and electrons can more easily enter the floating gate structure 110 from the substrate 100 or enter the substrate 100 from the floating gate structure 110, thereby facilitating the improvement of the writing or erasing speed and correspondingly improving the writing or erasing performance; moreover, since the substrate 100 has a protruding structure 101, electrons enter the floating gate structure 110 through the top corner position of the protruding structure 101 during writing, and electrons enter the substrate 100 through the bottom corner position of the protruding structure 101 during erasing. Therefore, the electron tunneling path during writing is different from the electron tunneling path during erasing, correspondingly reducing the probability of damage to the first dielectric layer 111, thereby facilitating the improvement of the service life of the first dielectric layer 111 and further facilitating the improvement of the performance of the memory.

[0030] In this embodiment, the substrate 100 includes a storage unit area i, and the substrate 100 in the storage unit area i has one or more protruding structures 101.

[0031] The storage unit area i refers to the part of the substrate 100 used for storing data, which is usually used to form storage units. The storage unit area i usually has a specific storage unit structure and circuit design to meet the requirements of data storage.

[0032] As an example, the number of the storage unit areas i is multiple.

[0033] In this embodiment, the shape of the protruding structure 101 includes one or both of a rectangle and a trapezoid.

[0034] It should be noted that the trapezoid mentioned herein refers to a trapezoid with an upper base smaller than the lower base, that is, the length of the top of the convex structure 101 is smaller than the length of its bottom.

[0035] As an example, the shape of the convex structure 101 includes a rectangle.

[0036] The shape of the convex structure 101 including a rectangle is beneficial to making the included angle θ4 at the corner position of the top of the convex structure 101 and the included angle θ3 at the corner position of the bottom both close to 90°, thereby being beneficial to achieving a better effect of increasing the electric field strength at the corner position of the convex structure 101.

[0037] It should be noted that along the normal direction of the top surface of the substrate 100, the height h1 of the convex structure 101 should not be too small nor too large. If the height h1 of the convex structure 101 is too small, it is likely to cause great difficulty in forming a convex structure 101 that meets the requirements; if the height h1 of the convex structure 101 is too large, that is, there is a large distance between the top of the convex structure 101 and the top of the side substrate 100, it is likely to increase the difficulty of forming the floating gate structure 110. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the height h1 of the convex structure 101 is 500 angstroms to 1000 angstroms.

[0038] It should also be noted that along the direction perpendicular to the side wall of the convex structure 101, the width w2 of the convex structure 101 should not be too small nor too large. If the width w2 of the convex structure 101 is too small, it is likely to increase the difficulty of forming the convex structure 101; if the width w2 of the convex structure 101 is too large, it is likely to make the width of the formed floating gate structure 110 larger, thus making the size of the memory larger. Therefore, in this embodiment, along the direction perpendicular to the side wall of the convex structure 101, the width w2 of the convex structure 101 is 0.2 micrometers to 0.4 micrometers.

[0039] In this embodiment, there are multiple convex structures 101.

[0040] There are multiple convex structures 101, that is, the substrate 100 of a single memory cell region i has multiple convex structures 101, which is beneficial to increasing the number of corners, thereby being beneficial to further increasing the electron tunneling path, and further reducing the probability of damage to the first dielectric layer 111.

[0041] It should be noted that in a single memory cell region i, when the number of the convex structures 101 is greater than or equal to 2, it is likely to achieve a better effect of further increasing the electron tunneling path, thereby being beneficial to further improving the writing or erasing speed and extending the service life of the first dielectric layer 111. Therefore, as an example, the number of the convex structures 101 is greater than or equal to 2.

[0042] It should also be noted that in a single memory cell region i, the distance w1 between adjacent protruding structures 101 should not be too large. If the distance w1 between adjacent protruding structures 101 is too large, it is likely that the width of the floating gate structure 110 will be relatively large, thereby making the size of the memory relatively large. Therefore, as an example, the distance w1 between adjacent protruding structures 101 is less than or equal to 0.2 micrometers.

[0043] For this reason, in this embodiment, by reasonably setting the width w2 of the protruding structure 101 and the distance w1 between adjacent protruding structures 101, it is easy to increase the number of corners and improve the process stability while making the size of the memory relatively small.

[0044] In this embodiment, the memory further includes: a buried layer 103, which is located in the substrate 100 at the bottom of the protruding structure 101. There is a spacing between the buried layer 103 and the source / drain doping layer 160 on one side of the floating gate structure 110, and the doping ion type of the buried layer 103 is the same as that of the source / drain doping layer 160.

[0045] The buried layer 103 serves as an electron-enriched region and is used to provide more electrons for electron tunneling, thereby facilitating further improvement of the write or erase speed.

[0046] Since the doping ion type of the source / drain doping layer 160 is the same as that of the buried layer 103, there is a spacing between the source / drain doping layer 160 on one side of the floating gate structure 110 and the buried layer 103, which is convenient for reducing the probability of punch through between the buried layer 103 and the source / drain doping layer 160.

[0047] As an example, the doping ions in the buried layer 103 are N-type ions. The N-type ions may include P ions, As ions or Sb ions. In other embodiments, the doping ions in the buried layer are P-type ions, and the P-type ions may include B ions, Ga ions or In ions.

[0048] It should be noted that the spacing w3 between the buried layer 103 and the source / drain doping layer 160 on one side of the floating gate structure 110 should not be too small. If the spacing w3 between the buried layer 103 and the source / drain doping layer 160 on one side of the floating gate structure 110 is too small, it is likely that the effect of reducing punch through between the buried layer 103 and the source / drain doping layer 160 will be poor. Therefore, in this embodiment, the spacing w3 between the buried layer 103 and the source / drain doping layer 160 on one side of the floating gate structure 110 is greater than or equal to 0.2 micrometers.

[0049] In this embodiment, the memory further includes: a well region 104, which is located in the substrate 100.

[0050] The doping ion type of the well region 104 is opposite to that of the buried layer 103.

[0051] As an example, the doping ions in the buried layer 103 are N-type ions. Correspondingly, the doping ions in the well region 104 are P-type ions.

[0052] The floating gate structure 110 can capture and store electrons, and after power-off, the electrons stored in the floating gate structure 110 will not be lost, thus realizing information storage.

[0053] The first dielectric layer 111 serves as the tunnel oxide layer of the memory, which is used to achieve electrical isolation between the first gate layer 112 and the substrate 100, so that electrons can enter the first gate layer 112 via the first dielectric layer 111 by means of the tunneling effect.

[0054] In this embodiment, the material of the first dielectric layer 111 is silicon oxide. In other embodiments, the material of the first dielectric layer can also be other suitable dielectric materials such as silicon oxynitride.

[0055] In this embodiment, the material of the first gate layer 112 includes polysilicon. Polysilicon is a commonly used material for the floating gate structure 110 in the memory, thus having the characteristic of low process cost.

[0056] It should be noted that along the normal direction of the top surface of the substrate 100, the thickness h2 of the first dielectric layer 111 should not be too small or too large. If the thickness h2 of the first dielectric layer 111 is too small, the probability of electrons stored in the first gate layer 112 entering the substrate 100 increases, thus increasing the probability of electron loss, and further affecting the storage performance of the memory; if the thickness h2 of the first dielectric layer 111 is too large, it is likely that the effect of reducing the difficulty of electrons entering the floating gate structure 110 from the substrate 100 or from the floating gate structure 110 into the substrate 100 is not good, so that the effect of improving the write or erase speed is not good, and it is easy to cause the overall height of the memory to be too high, which is not conducive to further reducing the size of the memory. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the thickness h2 range of the first dielectric layer 111 is 80 angstroms to 150 angstroms.

[0057] The control gate structure 120 is configured to allow electrons to enter the floating gate structure 110 or be pulled out of the floating gate structure 110 during data writing or erasing. When reading the memory, by applying an operating voltage to the control gate structure 120, the on / off state of the channel region at the bottom of the floating gate structure 110 is controlled using the charged state of the floating gate structure 110.

[0058] The second gate layer 122 is configured to be electrically connected to an external circuit structure. The second dielectric layer 121 is used for electrical isolation between the floating gate structure 110 and the second gate layer 122.

[0059] In this embodiment, the material of the second dielectric layer 121 is a dielectric material. As an example, the second dielectric layer 121 has an ONO (Oxide-Nitride-Oxide) structure, that is, the second dielectric layer 121 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0060] The ONO structure can further increase the dielectric constant of the second dielectric layer 121 while reducing the thickness of the second dielectric layer 121, thereby enabling the memory to have a higher breakdown electric field and lower leakage characteristics. In other embodiments, the second dielectric layer can also be a single-layer structure, and the second dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0061] In this embodiment, the material of the second gate layer 122 includes polysilicon. Polysilicon is a commonly used material for the control gate structure 120 in the memory, thus having the characteristic of low process cost.

[0062] In this embodiment, the memory further includes: a select gate structure 130 located on the substrate 100 at the side of the protrusion structure 101 and the floating gate structure 110. The select gate structure 130 includes, from bottom to top, a first dielectric layer 111, a first gate layer 112, a second dielectric layer 121, and a second gate layer 122 stacked in sequence.

[0063] The select gate structure 130 is configured to determine the storage unit area i to be edited.

[0064] In this embodiment, the memory further includes: a sidewall 140 located on the sidewalls of the floating gate structure 110, the control gate structure 120, and the select gate structure 130.

[0065] The sidewall 140 is used to protect the sidewalls of the floating gate structure 110, the control gate structure 120, and the select gate structure 130, and can also be used to define the position of the source / drain doping layer 160.

[0066] Specifically, the sidewall 140 can be a single-layer structure or a laminated structure; the material of the sidewall 140 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0067] When the device is operating, the source-drain doped layer 160 is used as a source electrode or a drain electrode to provide a carrier source.

[0068] Correspondingly, as an example, the doped ions in the source-drain doped layer 160 are N-type ions. The N-type ions can include P ions, As ions, or Sb ions. In other embodiments, the doped ions in the source-drain doped layer are P-type ions, and the P-type ions can include B ions, Ga ions, or In ions.

[0069] Correspondingly, in this embodiment, the source-drain doped layer 160 is located in the substrate on both sides of the select gate structure 130 and the floating gate structure 110.

[0070] In this embodiment, the memory further includes: a lightly doped region 150, which is located in the substrate 100 on both sides of the floating gate structure 110 and the control gate structure 120.

[0071] The lightly doped region 150 is used to reduce the probability of punch-through occurring between the source-drain doped layers 160.

[0072] Specifically, the type of doped ions in the lightly doped region 150 is the same as the type of doped ions in the source-drain doped layer 160.

[0073] Correspondingly, in this embodiment, the source-drain doped layer 160 is located in the lightly doped region 150.

[0074] Since the lightly doped region 150 is located in the substrate 100 on both sides of the floating gate structure 110 and the control gate structure 120, and the type of doped ions in the source-drain doped layer 160 is the same as the type of doped ions in the lightly doped region 150; correspondingly, in this embodiment, there is also a spacing between the lightly doped region 150 on one side of the floating gate structure 110 and the buried layer 103.

[0075] Correspondingly, the present invention also provides a method for forming a memory. Figures 5 to 17 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the memory of the present invention.

[0076] Refer to Figures 5 to 8 , provide a substrate 500, and the substrate 500 has one or more raised structures 501.

[0077] Among them, Figure 5 is a schematic structural diagram after forming an initial buried layer and a well region, Figure 6 is a schematic structural diagram after forming a mask layer,Figure 7 is Figure 6 A schematic structural diagram after forming the raised structure and the buried layer; Figure 8 is Figure 7 A partial structural schematic diagram in region B.

[0078] The substrate 500 is used to provide a process platform for the subsequent formation of the memory.

[0079] In this embodiment, the substrate 500 is used to form a non-volatile memory. As an example, the substrate 500 is used to form an EEPROM memory.

[0080] In this embodiment, the substrate 500 includes a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0081] In the step of providing the substrate 500, the substrate 500 has one or more raised structures 501. Subsequently, a floating gate structure covering the raised structures 501 is formed on the substrate 500. The floating gate structure includes a first dielectric layer and a first gate layer stacked in sequence. The first dielectric layer conformally covers the top and sidewalls of the raised structures, as well as the substrate 500 on the sides of the raised structures. Such that during writing or erasing, under the condition of the same voltage, the electric field intensity at the corner positions of the raised structures 501 is relatively large, and electrons can more easily enter the floating gate structure from the substrate 500 or enter the substrate 500 from the floating gate structure, thereby facilitating the improvement of the writing or erasing speed and correspondingly improving the writing or erasing performance; moreover, since the substrate 500 has raised structures, electrons enter the floating gate structure through the top corner positions of the raised structures 501 during writing, and electrons enter the substrate 500 through the bottom corner positions of the raised structures 501 during erasing. Therefore, the electron tunneling path during writing is different from the electron tunneling path during erasing, correspondingly reducing the probability of damage to the first dielectric layer, thereby facilitating the improvement of the service life of the first dielectric layer and further facilitating the improvement of the performance of the memory.

[0082] In this embodiment, the substrate 500 includes a storage unit area I, and the substrate 500 in the storage unit area I has one or more raised structures 501.

[0083] The storage unit area I refers to the part of the substrate 500 used for storing data, which is usually used to form storage units. The storage unit area I usually has a specific storage unit structure and circuit design to meet the requirements of data storage.

[0084] As an example, the number of the storage unit areas I is multiple.

[0085] In this embodiment, the steps of providing the substrate 500 include: referring to Figure 5 , providing an initial substrate 505; referring to Figures 6 to 8 in combination, in some regions, removing a part of the thickness of the initial substrate 505 so that the initial substrate 505 has a convex structure 501, and the remaining initial substrate 505 serves as the substrate 500, that is, in some regions, removing a part of the thickness of the initial substrate 505 to obtain a substrate 500 having a convex structure 501.

[0086] After providing the initial substrate 505, in some regions, removing a part of the thickness of the initial substrate 505 so that the initial substrate 505 has a convex structure 501 is beneficial to reducing the difficulty of forming the convex structure 501.

[0087] Specifically, the steps of removing a part of the thickness of the initial substrate 505 include: as Figure 6 shown, forming a patterned mask layer 502 on the initial substrate 505; using the mask layer 502 as a mask to remove a part of the thickness material of the initial substrate 505 that is not covered by the mask; as Figure 7 shown, the forming method further includes: removing the mask layer 502.

[0088] Forming a patterned mask layer 502 on the initial substrate 505 and using the mask layer 502 as a mask to remove a part of the thickness material of the initial substrate 505 that is not covered by the mask is beneficial to reducing the probability of damage to the initial substrate 505 during the process of removing a part of the thickness of the initial substrate 505.

[0089] In this embodiment, the process of removing a part of the thickness of the initial substrate 505 includes a dry etching process and a wet etching process.

[0090] As an example, after the dry etching process, a wet etching process is performed.

[0091] The dry etching process has an anisotropic etching characteristic, and its longitudinal etching rate is greater than the lateral etching rate, and the process controllability is relatively high. Using the dry etching process to perform patterning on the initial substrate 505 is beneficial to improving the dimensional accuracy, morphological accuracy, and position accuracy of the convex structure 501.

[0092] The wet etching process is convenient for removing the residues on the initial substrate 505 after the dry etching process.

[0093] Specifically, the process parameters of the dry etching process include: the process gas includes: O2, HBr, and CF4. The flow rate range of O2 is from 100 standard milliliters per minute to 150 standard milliliters per minute, the flow rate range of HBr is from 100 standard milliliters per minute to 150 standard milliliters per minute, the flow rate range of CF4 is from 100 standard milliliters per minute to 150 standard milliliters per minute, the pressure range of the reaction chamber is from 10 millitorr to 80 millitorr, and the process time range is from 30 seconds to 60 seconds.

[0094] It should be noted that the flow rate of the process gas should not be too small or too large. If the flow rate of the process gas is too small, it is likely to result in too low an etching rate, thus affecting the process efficiency; if the flow rate of the process gas is too large, it is likely to reduce the process stability, thus increasing the probability of damage to the initial substrate 505. Therefore, in this embodiment, the flow rate range of O2 is from 100 standard milliliters per minute to 150 standard milliliters per minute, the flow rate range of HBr is from 100 standard milliliters per minute to 150 standard milliliters per minute, and the flow rate range of CF4 is from 100 standard milliliters per minute to 150 standard milliliters per minute.

[0095] It should also be noted that the pressure of the reaction chamber should not be too small or too large. Whether the pressure of the reaction chamber is too small or too large, it is likely to increase the difficulty of controlling the dry etching process. Therefore, in this embodiment, the pressure range of the reaction chamber is from 10 millitorr to 80 millitorr.

[0096] In addition, the process time should not be too short or too long. If the process time is too short, it is likely that the thickness of the removed initial substrate 505 is small, thus making it difficult for the height of the convex structure 501 to meet the design requirements; if the process time is too long, it is likely that the thickness of the removed initial substrate 505 is large, thus also making it difficult for the height of the convex structure 501 to meet the design requirements. Therefore, in this embodiment, the process time range is from 30 seconds to 60 seconds.

[0097] In this embodiment, the shape of the convex structure 501 includes one or both of a rectangle and a trapezoid.

[0098] It should be noted that the trapezoid refers to a trapezoid with an upper base smaller than the lower base, that is, the length of the top of the convex structure 501 is smaller than the length of its bottom.

[0099] As an example, the shape of the convex structure 501 includes a rectangle.

[0100] The shape of the convex structure 501 including a rectangle is conducive to making the included angle θ1 at the corner position of the top of the convex structure 501 and the included angle θ2 at the corner position of the bottom both close to 90°, thereby being conducive to achieving a better effect of increasing the electric field strength at the corner position of the convex structure 501.

[0101] It should be noted that, along the normal direction of the top surface of the substrate 500, the height H1 of the protrusion structure 501 should not be too small or too large. If the height H1 of the protrusion structure 501 is too small, it is likely to make it difficult to form a protrusion structure 501 that meets the requirements; if the height H1 of the protrusion structure 501 is too large, that is, there is a large distance between the top of the protrusion structure 501 and the top of the substrate 500 on its side, it is likely to increase the difficulty of forming the subsequent floating gate structure. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the height H1 of the protrusion structure 501 is 500 angstroms to 1000 angstroms.

[0102] It should also be noted that, along the direction perpendicular to the side wall of the protrusion structure 501, the width W2 of the protrusion structure 501 should not be too small or too large. If the width W2 of the protrusion structure 501 is too small, it is likely to increase the difficulty of forming the protrusion structure 501; if the width W2 of the protrusion structure 501 is too large, it is likely to make the width of the subsequent formed floating gate structure larger, thereby making the size of the memory larger. Therefore, in this embodiment, along the direction perpendicular to the side wall of the protrusion structure 501, the width W2 of the protrusion structure 501 is 0.2 micrometers to 0.4 micrometers.

[0103] Therefore, in this embodiment, by reasonably setting the width W2 of the protrusion structure 501 and the distance W1 between adjacent protrusion structures 501, it is easy to increase the number of corners and improve the process stability while making the size of the memory smaller.

[0104] In this embodiment, in the step of providing the substrate 500, the protrusion structures 501 are multiple.

[0105] The fact that the protrusion structures 501 are multiple, that is, the substrate 500 of a single memory cell region I has multiple protrusion structures 501, is beneficial to increasing the number of corners, thereby being beneficial to further increasing the electron tunneling path, and further reducing the probability of damage to the subsequently formed first dielectric layer.

[0106] It should be noted that, in a single memory cell region I, when the number of the protrusion structures 501 is greater than or equal to 2, it is likely to make the effect of further increasing the electron tunneling path better, thereby being beneficial to further improving the writing or erasing speed and extending the service life of the first dielectric layer. Therefore, as an example, the number of the protrusion structures 501 is greater than or equal to 2.

[0107] It should also be noted that in a single memory cell region I, the distance W1 between adjacent protruding structures 501 should not be too large. If the distance W1 between adjacent protruding structures 501 is too large, it is likely that the width of the subsequently formed floating gate structure will be relatively large, thereby making the size of the memory relatively large. Therefore, as an example, the distance W1 between adjacent protruding structures 501 is less than or equal to 0.2 micrometers.

[0108] As Figure 7 and Figure 8 shown, in this embodiment, in the step of providing the substrate 500, a buried layer 503 is formed in the substrate 500 at the bottom of the protruding structure 501, and the buried layer 503 contains doped ions.

[0109] The buried layer 503 serves as an electron-enriched region, which is used to provide more electrons for electron tunneling, thereby facilitating further improvement of the writing or erasing speed.

[0110] As an example, the doped ions in the buried layer 503 are N-type ions. The N-type ions may include P ions, As ions, or Sb ions. In other embodiments, the doped ions in the buried layer are P-type ions, and the P-type ions may include B ions, Ga ions, or In ions.

[0111] Specifically, an initial buried layer 503′ is formed in the initial substrate 505 (as Figure 5 shown); in some regions, a part of the initial substrate 505 with a certain thickness is removed to obtain the substrate 500 with the protruding structure 501, including: in some regions, a part of the initial substrate 505 and the initial buried layer 503′ with a certain thickness are removed to make the initial substrate 505 have a protruding structure, and the remaining initial substrate 505 serves as the substrate 500, and a buried layer 503 located in the substrate 500 is formed (as Figure 7 and Figure 8 shown).

[0112] More specifically, the initial buried layer 503′ is formed by doping a preset region of the initial buried layer 503′ in the initial substrate 505 by means of ion implantation.

[0113] Correspondingly, the doped ions of the buried layer 503 are also located in the protruding structure 501.

[0114] In this embodiment, in the step of providing the substrate 500, a well region 504 is also formed in the substrate 500.

[0115] The type of doped ions in the well region 504 is opposite to the type of doped ions in the buried layer 503.

[0116] As an example, the doped ions in the buried layer 503 are N-type ions. Correspondingly, the doped ions in the well region 504 are P-type ions.

[0117] Reference Figures 9 to 14 , a floating gate structure 510 covering the raised structure 501 is formed on the substrate 500. The floating gate structure 510 includes the first dielectric layer 511 and the first gate layer 512 stacked in sequence. The first dielectric layer 511 conformally covers the top and side walls of the raised structure 501, and the substrate on the side of the raised structure 501.

[0118] Wherein, Figure 9 is Figure 8 a partial structural schematic diagram after forming the first dielectric layer, Figure 10 is Figure 9 a partial structural schematic diagram after forming the first gate layer, Figure 11 is Figure 10 a partial structural schematic diagram after forming the second dielectric layer, Figure 12 is Figure 11 a partial structural schematic diagram after forming the second gate layer, Figure 13 is Figure 7 a structural schematic diagram after forming the first dielectric layer, the first gate layer, the second dielectric layer and the second gate layer, Figure 14 is Figure 13 a structural schematic diagram after patterning the first dielectric layer, the first gate layer, the second dielectric layer and the second gate layer.

[0119] The floating gate structure 510 can capture and store electrons, and after power-off, the electrons stored in the floating gate structure 510 will not be lost, thus realizing the storage of information.

[0120] The first dielectric layer 511 serves as the tunneling oxide layer of the memory, and is used to achieve electrical isolation between the first gate layer 512 and the substrate 500, so that electrons enter the first gate layer 512 through the first dielectric layer 511 by means of the tunneling effect.

[0121] In this embodiment, the material of the first dielectric layer 511 is silicon oxide. In other embodiments, the material of the first dielectric layer can also be other suitable dielectric materials such as silicon oxynitride.

[0122] In this embodiment, the material of the first gate layer 512 includes polysilicon. Polysilicon is a commonly used material for the floating gate structure 510 in the memory, thus having the characteristic of low process cost.

[0123] It should be noted that, along the normal direction of the top surface of the substrate 500, the thickness H2 of the first dielectric layer 511 should not be too small or too large. If the thickness H2 of the first dielectric layer 511 is too small, the probability of electrons stored in the first gate layer 512 entering the substrate 500 increases, thereby increasing the probability of electron loss, and further affecting the storage performance of the memory; if the thickness H2 of the first dielectric layer 511 is too large, it is likely that the effect of reducing the difficulty of electrons entering the floating gate structure 510 from the substrate 500 or from the floating gate structure 510 into the substrate 500 is not good, resulting in a poor effect of improving the write or erase speed, and it is likely to cause the overall height of the memory to be too high, which is not conducive to further reducing the size of the memory. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the thickness H2 of the first dielectric layer 511 ranges from 80 angstroms to 150 angstroms.

[0124] Continue to refer to Figures 9 to 14 , a control gate structure 520 is formed on the floating gate structure 510, and the control gate structure 520 includes the second dielectric layer 521 and the second gate layer 522 stacked in sequence.

[0125] The control gate structure 520 is used to allow electrons to enter the floating gate structure 510 or pull electrons out of the floating gate structure 510 during the process of data writing or erasing. When reading the memory, by applying a working voltage on the control gate structure 520, the on / off state of the channel region at the bottom of the floating gate structure 510 is controlled by using the charged state of the floating gate structure 510.

[0126] The second gate layer 522 is used for electrical connection with an external circuit structure. The second dielectric layer 521 is used for electrical isolation between the floating gate structure 510 and the second gate layer 522.

[0127] In this embodiment, the material of the second dielectric layer 521 is a dielectric material. As an example, the second dielectric layer 521 is an ONO structure, that is, the second dielectric layer 521 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0128] The ONO structure can further increase the dielectric constant of the second dielectric layer 521 while reducing the thickness of the second dielectric layer 521, so that the memory has a higher breakdown electric field and lower leakage characteristics. In other embodiments, the second dielectric layer can also be a single-layer structure, and the second dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0129] In this embodiment, the material of the second gate layer 522 includes polysilicon. Polysilicon is a common material for the control gate structure 520 in the memory, thus having the characteristic of low process cost.

[0130] In this embodiment, the steps of forming the floating gate structure 510 and the control gate structure 520 include: As Figure 9 shown, a first dielectric layer 511 is formed on the substrate 500, and the first dielectric layer 511 conformally covers the top and sidewalls of the protruding structure 501, as well as the substrate on the side of the protruding structure 501; As Figure 10 shown, a first gate layer 512 is formed on the first dielectric layer 511; As Figure 11 shown, a second dielectric layer 521 is formed on the first gate layer 512; As Figures 12 to 13 shown, a second gate layer 522 is formed on the second dielectric layer 521; As Figure 14 shown, the first dielectric layer 511, the first gate layer 512, the second dielectric layer 521, and the second gate layer 522 are patterned to form a floating gate structure 510 located on the substrate 500 and covering the protruding structure 501, and a control gate structure 520 stacked on the floating gate structure 510.

[0131] First, a first dielectric layer 511, a first gate layer 512, a second dielectric layer 521, and a second gate layer 522 are sequentially formed on the substrate 500, and then the first dielectric layer 511, the first gate layer 512, the second dielectric layer 521, and the second gate layer 522 are patterned to form a floating gate structure 510 located on the substrate 500 and covering the protruding structure 501, and a control gate structure 520 stacked on the floating gate structure 510, which is beneficial to simplifying the process steps of forming the floating gate structure 510 and the control gate structure 520 and saving process costs.

[0132] Specifically, the process of forming the first dielectric layer 511 is an oxidation process, and the oxidation process includes one or more of a furnace tube dry oxygen oxidation process, a wet oxygen oxidation process, and an in-situ steam generation (ISSG) oxidation process.

[0133] As an example, the first dielectric layer 511 is formed by using an in-situ steam generation oxidation process.

[0134] The first dielectric layer 511 formed by using an in-situ steam generation oxidation process has a uniform thickness and a relatively high density, which is beneficial to improving the quality of the first dielectric layer 511.

[0135] In this embodiment, during the process of forming the floating gate structure 510 and the control gate structure 520, a select gate structure 530 spaced apart from the control gate structure 520 is further formed on the substrate 500 on the side of the protruding structure 501 and the floating gate structure 510. The select gate structure 530 includes a first dielectric layer 511, a first gate layer 512, a second dielectric layer 521, and a second gate layer 522 stacked in sequence from top to bottom.

[0136] The select gate structure 530 is used to determine the storage cell region I to be edited.

[0137] Specifically, during the patterning of the first dielectric layer 511, the first gate layer 512, the second dielectric layer 521, and the second gate layer 522, a select gate structure 530 spaced apart from the control gate structure 520 is formed on the substrate 500 on the side of the protruding structure 501 and the floating gate structure 510.

[0138] During the patterning of the first dielectric layer 511, the first gate layer 512, the second dielectric layer 521, and the second gate layer 522, forming a select gate structure 530 spaced apart from the control gate structure 520 on the substrate 500 on the side of the protruding structure 501 and the floating gate structure 510 is beneficial to simplifying the process steps of forming the select gate structure 530 and saving process costs.

[0139] Reference Figure 15 Referring to

[0140] In this embodiment, after forming the floating gate structure 510 and the control gate structure 520 and before forming the source / drain doping layer, the forming method further includes: forming lightly doped regions 550 in the substrate 500 on both sides of the floating gate structure 510 and the control gate structure 520.

[0141] The lightly doped regions 550 are used to reduce the probability of punch-through between the source / drain doping layers.

[0142] As an example, the doping ions in the lightly doped regions 550 are N-type ions. In other embodiments, the doping ions in the lightly doped regions may also be P-type ions.

[0143] Reference Figure 16 Referring to

[0144] The sidewall 540 is used to protect the sidewalls of the floating gate structure 510, the control gate structure 520, and the select gate structure 530, and can also be used to define the position of the subsequent source-drain doping layer.

[0145] Specifically, the sidewall 540 can be a single-layer structure or a stacked structure; the material of the sidewall 540 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride.

[0146] As an example, after forming the lightly doped region 550 and before forming the source-drain doping layer, the sidewall 540 is formed.

[0147] Reference Figure 17 , source-drain doping layers 560 are formed in the substrate 500 on both sides of the floating gate structure 510.

[0148] During device operation, the source-drain doping layer 560 is used as a source or drain to provide a carrier source.

[0149] Specifically, the doping ion type of the source-drain doping layer 560 is the same as that of the lightly doped region 550.

[0150] Correspondingly, in this embodiment, in the step of forming the source-drain doping layer 560, the source-drain doping layer 560 is located in the lightly doped region 550.

[0151] Correspondingly, in this embodiment, in the step of forming the source-drain doping layer 560, source-drain doping layers 560 are formed in the substrate 500 on both sides of the floating gate structure 510 and the select gate structure 530.

[0152] Correspondingly, in this embodiment, in the step of forming the source-drain doping layer 560, there is a spacing between the source-drain doping layer 560 on one side of the floating gate structure 510 and the buried layer 503, and the doping ion type of the source-drain doping layer 560 is the same as that of the buried layer 503.

[0153] Since the doping ion type of the source-drain doping layer 560 is the same as that of the buried layer 503, there is a spacing between the source-drain doping layer 560 on one side of the floating gate structure 510 and the buried layer 503, which is convenient for reducing the probability of punch-through between the buried layer 503 and the source-drain doping layer 560.

[0154] Correspondingly, as an example, the doping ions in the source-drain doping layer 560 are N-type ions. The N-type ions can include P ions, As ions, or Sb ions. In other embodiments, the doping ions in the source-drain doping layer are P-type ions, and the P-type ions can include B ions, Ga ions, or In ions.

[0155] In this embodiment, a lightly doped region 550 is formed in the substrate 500 on both sides of the floating gate structure 510 and the control gate structure 520; in the step of forming the source / drain doping layer 560, the doping ion type of the source / drain doping layer 560 is the same as that of the lightly doped region 550; correspondingly, there is also a spacing between the lightly doped region 550 on one side of the floating gate structure 510 and the buried layer 503.

[0156] It should be noted that the spacing W3 between the source / drain doping layer 560 on one side of the floating gate structure 510 and the buried layer 503 should not be too small. If the spacing W3 between the source / drain doping layer 560 on one side of the floating gate structure 510 and the buried layer 503 is too small, it is likely that the effect of reducing punch-through between the buried layer 503 and the source / drain doping layer 560 is not good. Therefore, in this embodiment, the spacing W3 between the source / drain doping layer 560 on one side of the floating gate structure 510 and the buried layer 503 is greater than or equal to 0.2 micrometers.

[0157] It should be noted that the memory can be formed by using the formation method described in the foregoing embodiment, or can be formed by using other formation methods. For the specific description of the memory in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not described herein again.

[0158] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A memory, characterized in that, Comprising: A substrate having one or more raised structures; A floating gate structure located on the substrate and covering the raised structures, the floating gate structure comprising a first dielectric layer and a first gate layer stacked in sequence, the first dielectric layer conformally covering the top and sidewalls of the raised structures, and the substrate on the sides of the raised structures; A control gate structure located on the floating gate structure, the control gate structure comprising a second dielectric layer and a second gate layer stacked in sequence; Source / drain doping layers located in the substrate on both sides of the floating gate structure.

2. The memory according to claim 1, characterized in that, The memory further comprises: A select gate structure located on the substrate on the sides of the raised structures and the floating gate structure, the select gate structure comprising a first dielectric layer, a first gate layer, a second dielectric layer and a second gate layer stacked in sequence; The source / drain doping layers are located in the substrate on both sides of the select gate structure and the floating gate structure.

3. A memory according to claim 1, characterized in that, In the normal direction of the top surface of the substrate, the height of the raised structure is 500 angstroms to 1000 angstroms.

4. A memory according to claim 1, characterized in that, In the direction perpendicular to the sidewall of the raised structure, the width of the raised structure is 0.2 micrometers to 0.4 micrometers.

5. A memory according to claim 1, wherein, When there are multiple raised structures, the number of the raised structures is greater than or equal to 2.

6. A memory according to claim 1, characterized in that, When there are multiple raised structures, the distance between adjacent raised structures is less than or equal to 0.2 micrometers.

7. A memory according to claim 1, wherein The shape of the raised structure includes one or both of a rectangle and a trapezoid.

8. A memory according to claim 1, characterized in that, In the normal direction of the top surface of the substrate, the thickness range of the first dielectric layer is 80 angstroms to 150 angstroms.

9. A memory according to claim 1, characterized in that, The memory further comprises: A buried layer located in the substrate at the bottom of the raised structure, there is a spacing between the buried layer and the source / drain doping layer on one side of the floating gate structure, and the doping ion type of the buried layer is the same as that of the source / drain doping layer.

10. A memory according to claim 9, wherein, The doping ions of the buried layer are also located in the raised structure.

11. A memory according to claim 9, wherein, The spacing between the buried layer and the source / drain doping layer on one side of the floating gate structure is greater than or equal to 0.2 micrometers.

12. A method for forming a memory, characterized in that, Comprising: Providing a substrate having one or more raised structures; Forming a floating gate structure on the substrate to cover the raised structures, the floating gate structure comprising a first dielectric layer and a first gate layer stacked in sequence, the first dielectric layer conformally covering the top and sidewalls of the raised structures, and the substrate on the sides of the raised structures; Forming a control gate structure on the floating gate structure, the control gate structure comprising a second dielectric layer and a second gate layer stacked in sequence; Forming source / drain doping layers in the substrate on both sides of the floating gate structure.

13. A method for forming a memory as described in claim 12, characterized in that, The steps of forming the floating gate structure and the control gate structure include: Forming a first dielectric layer on the substrate, the first dielectric layer conformally covering the top and sidewalls of the raised structures, and the substrate on the sides of the raised structures; Forming a first gate layer on the first dielectric layer; Forming a second dielectric layer on the first gate layer; Forming a second gate layer on the second dielectric layer; Patterning the first dielectric layer, the first gate layer, the second dielectric layer and the second gate layer to form a floating gate structure located on the substrate and covering the raised structures, and a control gate structure stacked on the floating gate structure.

14. A method for forming a memory as claimed in claim 12 or 13, characterized in that, During the process of forming the floating gate structure and the control gate structure, a select gate structure spaced apart from the control gate structure is further formed on the substrate on the side of the raised structure and the floating gate structure. The select gate structure includes a first dielectric layer, a first gate layer, a second dielectric layer, and a second gate layer stacked in sequence. In the step of forming the source / drain doping layer, source / drain doping layers are formed in the substrate on both sides of the floating gate structure and the select gate structure.

15. A method for forming a memory as described in claim 13, characterized in that, The process for forming the first dielectric layer is an oxidation process, and the oxidation process includes one or more of a furnace dry oxidation process, a wet oxidation process, and an in-situ steam generation oxidation process.

16. A method for forming a memory as claimed in claim 12 or 13, characterized in that, The step of providing the substrate includes: providing an initial substrate; in a partial region, removing a partial thickness of the initial substrate to obtain a substrate having a raised structure.

17. A method for forming a memory as described in claim 16, wherein, The process for removing a partial thickness of the initial substrate includes a dry etching process and a wet etching process.

18. A method for forming a memory as described in claim 17, wherein, The process parameters of the dry etching process include: the process gas includes: O2, HBr, and CF4. The flow rate range of O2 is from 100 standard milliliters per minute to 150 standard milliliters per minute, the flow rate range of HBr is from 100 standard milliliters per minute to 150 standard milliliters per minute, the flow rate range of CF4 is from 100 standard milliliters per minute to 150 standard milliliters per minute, the pressure range of the reaction chamber is from 10 millitorr to 80 millitorr, and the process time range is from 30 seconds to 60 seconds.

19. A method for forming a memory as described in claim 16, wherein, An initial buried layer is formed in the initial substrate; the step of removing a partial thickness of the initial substrate in a partial region to obtain a substrate having a raised structure includes: in a partial region, removing a partial thickness of the initial substrate and the initial buried layer to make the initial substrate have a raised structure, and the remaining initial substrate serves as the substrate, and a buried layer located in the substrate is formed; In the step of forming the source / drain doping layer, there is a spacing between the source / drain doping layer on one side of the floating gate structure and the buried layer, and the doping ion type of the source / drain doping layer is the same as that of the buried layer.

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