ESSD packaging structure

Abstract

The invention discloses an eSSD packaging structure, which increases the product capacity requirement, and improves the routing reliability while meeting the higher stacking requirement. The display panel includes: a first substrate; a second substrate; a plurality of Nand storage chip assemblies, wherein each Nand storage chip assembly comprises a Nand storage chip and a chip adhesion film; and a control chip. The control chip is attached to the back face of the first substrate and packaged through a first plastic package layer, the two sides of the front face of the first substrate are each provided with two stacked storage chip sets, Nand storage chip assemblies of each stacked chip set are arranged in a staggered mode, connecting welding spots are exposed, the second substrate is located on the upper layer of the stacked storage chip sets, and the second substrate is located on the lower layer of the stacked storage chip sets. The connection and welding of each group of Nand storage chip components are connected with corresponding welding spots right above the second substrate through vertical gold wires, the height areas of the front surface of the first substrate and the bottom surface of the second substrate are packaged through a second plastic packaging layer, the front surface of the second substrate is provided with a plurality of upwards convex solder balls, and the solder balls are used for carrying out connection operation.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and particularly to an eSSD packaging structure. Background Art

[0002] eSSDs usually adopt a stacked packaging technology to achieve higher storage density and performance within a limited space. The stacked packaging technology can achieve this goal by vertically stacking multiple chips, thus effectively solving the space problem. With the change of market demand, whether it is consumer electronics or in-vehicle electronics, the demand for storage capacity is constantly expanding. However, with the progress of technology, the packaging size of eSSDs is constantly shrinking.

[0003] The packaging structure of current eSSD products usually includes multiple NAND flash memory chips and control chips. With the market demand for storage capacity, the packaging quantity of Nand chips has reached the requirements of 8 layers, 16 layers, and even 32 layers, which greatly improves the technical requirements for packaging. In the existing general design, the control chip (hereinafter referred to as CTL) and the Nand storage chip (hereinafter referred to as Nand) are tiled and stacked in a Side by Side manner, and then Stack stacking is performed between Nands. This stacking method limits the stacking space of Nands to a certain extent, and will affect the heat dissipation and the warping problem of a single CO to a certain extent due to the uneven proportion of the plastic encapsulation material on both sides; similarly, with the increase in the number of stacked layers, the risk of wire arc punching during the plastic encapsulation process of the wire bonding also increases. Summary of the Invention

[0004] In view of the above problems, the present invention provides an eSSD packaging structure, which increases the product capacity requirement and improves the reliability of wire bonding while meeting the requirement of higher stacking.

[0005] An eSSD packaging structure, characterized in that it includes:

[0006] A first substrate;

[0007] A second substrate;

[0008] A plurality of Nand storage chip components, each Nand storage chip component includes a Nand storage chip and a chip adhesive film;

[0009] And a control chip;

[0010] The control chip is mounted on the back surface of the first substrate and encapsulated by a first encapsulation layer. On both sides of the front surface of the first substrate, two groups of stacked memory chip groups are respectively arranged. The Nand memory chip components in each group of stacked chip groups are arranged in a staggered manner, and the connection solder joints are all exposed. The second substrate is arranged on the upper layer of the stacked memory chip groups. The connection welding of each Nand memory chip component is connected to the corresponding solder joints directly above on the second substrate through vertical gold wires. The height area between the front surface of the first substrate and the bottom surface of the second substrate is encapsulated by a second encapsulation layer. On the front surface of the second substrate, a plurality of protruding solder balls are provided, and the solder balls are used for connection operations.

[0011] It is further characterized in that:

[0012] A plurality of protruding welding points are arranged on the outer periphery of the first substrate corresponding to the two groups of stacked memory chip groups. The protruding welding points are connected to the control chip through a connection layer in the first substrate. The solder joints at the corresponding positions on the second substrate are connected to the protruding welding points through vertical gold wires. Solder balls are arranged at the solder joint positions on the second substrate corresponding to the protruding welding points;

[0013] The number of stacked chips in each of the two groups of stacked memory chip groups is the same, so that the proportion of encapsulating material at both ends inside the same package structure is the same, and the CO warping problem can be effectively solved;

[0014] The Nand memory chip components in each group of stacked memory chip groups are arranged in a manner of shrinking from bottom to top and from outside to inside, which provides a reliable connection space for the vertical gold wires;

[0015] The number of Nand memory chip components in each group of stacked memory chip groups is not less than 4;

[0016] Preferably, the lower surface of the control chip is exposed outside the first encapsulation layer to ensure reliable and sufficient heat dissipation.

[0017] After adopting the structure of the present invention, the control chip and the Nand memory chips are separately stacked through a double-sided encapsulation form: the control chip is changed to be mounted and encapsulated on the back surface of the first substrate, and then the control chip is wrapped by the first encapsulation layer. Two groups of stacked memory chip groups are arranged on the front surface of the first substrate. In this way, the position originally occupied by the control chip can be used to lay more Nand memory chips flat, thereby increasing the product capacity requirement; at the same time, the Nand memory chips and the control chip are separately encapsulated, which can enhance the heat dissipation effect during operation. Each group of Nand memory chips is connected to the second substrate located above it through vertical gold wires, which avoids the risk of wire punching caused by the arc of wire bonding during encapsulation, thus meeting the requirement of higher stacking and improving the product reliability. Description of the Drawings

[0018] Figure 1Schematic diagram of the structure of the present invention;

[0019] The names corresponding to the numbers in the figure are as follows:

[0020] The first substrate 1, the control chip 2, the chip adhesion film 3, the Nand memory chip 4, the vertical gold wire 5, the second substrate 6, the solder ball 7, the upward convex welding point 8, the first encapsulation layer 9, the second encapsulation layer 10. Specific implementation manner

[0021] An eSSD packaging structure, as shown in Figure 1 : It includes a first substrate 1, a second substrate 6, a plurality of Nand memory chip components, and a control chip 2;

[0022] Each Nand memory chip component includes a Nand memory chip 4 and a chip adhesion film 3;

[0023] The control chip 2 is mounted on the back surface of the first substrate 1 and encapsulated by the first encapsulation layer 9. Two sets of stacked memory chip groups are respectively arranged in the two side regions on the front surface of the first substrate 1. The Nand memory chip components of each stacked chip group are arranged in a staggered manner and all expose the connection solder joints. The second substrate 6 is arranged on the upper layer of the stacked memory chip group. The connection welding of each Nand memory chip 4 is connected to the corresponding solder joint directly above on the second substrate 6 through the vertical gold wire 5. The height region between the front surface of the first substrate 1 and the bottom surface of the second substrate 6 is encapsulated by the second encapsulation layer 10. A plurality of upward convex solder balls 7 are arranged on the front surface of the second substrate 6, and the solder balls 7 are used for connection operations.

[0024] During specific implementation, a plurality of upward convex welding points 8 are arranged on the outer periphery of the first substrate 1 corresponding to the two sets of stacked memory chip groups. The upward convex welding points 8 are connected to the control chip 2 through the connection layer in the first substrate 1. The solder joints at the corresponding positions on the second substrate 6 are connected to the upward convex welding points 8 through the vertical gold wire 5. Solder balls 7 are arranged at the solder joint positions on the second substrate 6 corresponding to the upward convex welding points 8.

[0025] In a specific embodiment, the number of stacked chip components in each of the two sets of stacked memory chip groups is 4, and they are symmetrically arranged. The chip adhesion film 3 of the Nand memory chip component located at the bottom layer adheres to the upper surface of the first substrate. The chip adhesion films 3 of the Nand memory chip components located at non-bottom layers are respectively attached to the upper surfaces of the Nand memory chips 4 in the lower layer, so that the proportion of the encapsulation material at both ends inside the same packaging structure is the same, and the CO warping problem can be effectively solved;

[0026] The Nand memory chip components in each stacked memory chip group are arranged in a manner of shrinking from bottom to top and from outside to inside, which provides a reliable connection space for the vertical gold wire 5.

[0027] In a specific embodiment, the lower surface of the control chip 2 is exposed outside the first encapsulation layer 9 to ensure reliable and sufficient heat dissipation.

[0028] The control chip and the NAND memory chips are separately stacked in a double-sided encapsulation form: the control chip is changed to be surface-mounted and encapsulated on the back of the first substrate, and then the control chip is wrapped by the first encapsulation layer. Two groups of stacked memory chip groups are arranged on the front of the first substrate. In this way, the position originally occupied by the control chip can be used to lay more NAND memory chips flat, thereby increasing the product capacity requirement. At the same time, separating the encapsulation of the NAND memory chips and the control chip can enhance the heat dissipation effect during operation. Each group of NAND memory chips is connected to the second substrate above it through vertical gold wires, which avoids the risk of wire punching caused by the arc of wire bonding during encapsulation, thus meeting the requirement of higher stacking and improving the product reliability.

[0029] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0030] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An eSSD packaging structure, characterized in that, It includes: A first substrate; A second substrate; A number of Nand memory chip components, each Nand memory chip component includes a Nand memory chip and a chip adhesive film; And a control chip; The control chip is mounted on the back surface of the first substrate and encapsulated by a first encapsulation layer. Two groups of stacked memory chip groups are respectively arranged in the two side areas of the front surface of the first substrate. The Nand memory chip components of each group of stacked chip groups are arranged in a staggered manner and all expose connection solder joints. The second substrate is arranged on the upper layer of the stacked memory chip groups. The connection welding of each group of Nand memory chip components is connected to the corresponding solder joints directly above the second substrate through vertical gold wires. The height area between the front surface of the first substrate and the bottom surface of the second substrate is encapsulated by a second encapsulation layer. A number of protruding solder balls are arranged on the front surface of the second substrate, and the solder balls are used for connection operations.

2. The eSSD package structure according to claim 1, wherein: A number of protruding welding points are arranged on the outer periphery of the first substrate corresponding to the two groups of stacked memory chip groups. The protruding welding points are connected to the control chip through a connection layer in the first substrate. The corresponding solder joints of the second substrate are connected to the protruding welding points through vertical gold wires. Solder balls are arranged at the solder joint positions of the second substrate corresponding to the protruding welding points.

3. The eSSD packaging structure according to claim 1, wherein: The number of stacked chips in each of the two groups of stacked memory chip groups is the same.

4. An eSSD package structure according to claim 3, wherein: The Nand memory chip components of each group of stacked memory chip groups are arranged in a manner that shrinks from the bottom up and from the outside to the inside, which provides a reliable connection space for the vertical gold wires.

5. An eSSD package structure according to claim 3, characterized in that: The number of Nand memory chip components in each group of stacked memory chip groups is not less than 4.

6. The eSSD package structure according to claim 1, wherein: The lower surface of the control chip is exposed outside the first encapsulation layer.

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