Deep groove capacitor and manufacturing method of deep groove capacitor

Abstract

The invention relates to the technical field of integrated passive elements, in particular to a deep groove capacitor and a manufacturing method of the deep groove capacitor, a positive plate and a negative plate of the capacitor are located on the two side walls of a deep groove respectively, and electrode layers and dielectric layers are alternately stacked in the deep groove to form a staggered multi-layer structure. And the adjacent electrode layers are alternately and electrically connected with the positive plate or the negative plate. According to the invention, the highest capacitance density and more excellent ESR (equivalent resistance) and ESL (equivalent inductance) performance in similar capacitors can be realized. The appearance size of the capacitor can be reduced, the integration level of the device is improved, and the increasingly stringent miniaturization requirement of the advanced packaging technology is met. And extremely high working frequency and ultra-wide decoupling bandwidth can be realized, and increasingly high requirements of an integrated circuit on power supply integrity can be met. And the design is flexible, and capacitors with different capacitance values can be flexibly produced for various application scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated passive components, and particularly relates to a deep trench capacitor and a manufacturing method thereof. Background Art

[0002] In the field of integrated circuits, the problem of coupling noise in complex circuits has received increasing attention from researchers, designers, and manufacturers. With the expansion of the scale of integrated circuits, the increase in interconnect density, the enhancement of performance, and the improvement of operating frequency, if the noise problem cannot be effectively solved, the integrated circuit chip system may not operate properly or even fail completely. Decoupling capacitors are one of the main means to cope with coupling noise and are also one of the most commonly used integrated passive components in integrated circuits. Due to the characteristic that capacitors present high impedance to low-frequency signals and conduct high-frequency signals, in high-frequency applications, decoupling capacitors can filter out high-frequency noise in the power supply or signal waveforms. At the same time, the energy storage characteristic of capacitors enables them to stabilize the working voltage in the power distribution network, thereby reducing operating errors or failures caused by voltage fluctuations.

[0003] Currently, capacitor elements for integrated circuit decoupling are mainly divided into two categories: discrete type and integrated type. Discrete capacitors are mainly ceramic capacitors, such as common 0402 and 0201 capacitors. Ceramic capacitors have a relatively high unit capacitance density. However, since they are discrete devices, their installation and placement are subject to greater limitations, which easily introduce a relatively large loop inductance. At the same time, it is difficult to maintain a sufficiently close distance to the decoupling target in a miniaturized circuit system, thus affecting the decoupling effect. Integrated capacitors include MOS capacitors and MiM capacitors, etc., which are usually compatible with standard CMOS processes and offer more flexible designs. However, due to structural and principle limitations, it is difficult for integrated capacitors to simultaneously have a sufficiently high capacitance density and stable and accurate capacitance values. Deep trench integrated capacitors, on the other hand, can simultaneously solve multiple key problems such as high capacitance density, design flexibility, and integration compatibility with the process.

[0004] When the deep trench capacitor was first proposed, the substrate and the filler were used as the two electrode plates of the capacitor, and the oxide insulating layer covering the trench was used as the dielectric layer. This structure has limited improvement in capacitance density and is prone to introducing noise into the substrate. Summary of the Invention

[0005] One of the objectives of the present invention is to provide a deep trench capacitor and a deep trench capacitor that can achieve the highest capacitance density in the same type of design, as well as more excellent equivalent series resistance (ESR) and equivalent series inductance (ESL) performance, can reduce the form factor of the capacitor, improve the integration of the device, and meet the increasingly stringent miniaturization requirements of advanced packaging technologies.

[0006] Another objective of the present invention is to provide a manufacturing method for a deep trench capacitor, which is simple to prepare, has a simplified structure, and reduces costs.

[0007] One of the solutions adopted to achieve the object of the present invention is that the positive and negative plates of the capacitor are respectively located on the two side walls of the deep groove, and the electrode layer and the dielectric layer are alternately stacked in the deep groove to form an interleaved multi-layer structure, and adjacent electrode layers are alternately electrically connected to the positive or negative plate.

[0008] Both the electrode layer and the dielectric layer only cover the bottom of the deep groove and there is no coverage on the side walls. Further, a contact hole array is provided and filled with a conductive material. Any contact hole can lead out the corresponding positive or negative lead-out port and be connected to the functional circuit as required. The electrode layer and the electrode plate have a conductive function, and the dielectric layer has an insulating function.

[0009] Preferably, only a part of each electrode layer is conductive and is electrically connected to the electrode plate on the side in contact with the conductive region.

[0010] Preferably, the electrode layer and the dielectric layer are alternately stacked 10 - 60 layers.

[0011] Preferably, each electrode layer is only electrically connected to the positive or negative plate and is insulated from the junction of the negative or positive electrode.

[0012] Another solution adopted to achieve the object of the present invention is a manufacturing method of a deep groove capacitor, including the following steps:

[0013] Step a: Perform ion implantation on a specified area of the silicon substrate;

[0014] Step b: Perform deep silicon etching on the silicon substrate to produce a deep groove structure with the ion implantation area as the two side walls;

[0015] Step c: Prepare an amorphous silicon thin film at the bottom of the deep groove, and control the conductivity of its partial area by ion implantation and contact with one side wall of the deep groove structure to form an electrode layer.

[0016] Step d: Deposit an insulating material on the surface of the amorphous silicon thin film to prepare a dielectric layer, and continue to prepare an amorphous silicon thin film on the surface of the dielectric layer. Control the conductivity of its partial area by ion implantation and contact with the other side wall of the deep groove structure to form an electrode layer. Repeat this step to alternately stack multiple electrode layers and dielectric layers in the deep groove to form an interleaved multi-layer structure of the electrode layer and the dielectric layer, and adjacent electrode layers are alternately connected to the two side walls of the deep groove;

[0017] Step e: Backfill the remaining cavity part in the deep groove with silicon material;

[0018] Step f: Anneal the entire structure to activate the implanted ions;

[0019] Step g, perform CMP (Chemical Mechanical Polishing) planarization and prepare the ILD (Inter Layer Dielectric) layer;

[0020] Step h, prepare the contact hole array of the electrode plate by lithography, development, and etching of the ILD layer;

[0021] Step i, sputter a conductive material to fill the contact hole array and perform CMP to remove the excess conductive material on the surface; any contact hole can lead out the corresponding positive or negative lead port and be connected to the functional circuit as required.

[0022] Preferably, in step a, p-type doping of the silicon substrate is achieved by ion implantation. The ion implantation region conducts electricity to form the positive and negative plates of the capacitor, and the implanted ion species is gallium ions.

[0023] Preferably, in step b, the hard mask used in the deep silicon etching process is retained and removed after step e is completed.

[0024] The hard mask used in the deep silicon etching process in step b is not removed after the deep trench is formed to prevent material deposition in the area outside the deep trench in subsequent steps.

[0025] Preferably, in step c, p-type doping is achieved by ion implantation, so that a part of the amorphous silicon region conducts electricity and acts as the electrode layer. This electrode layer is only electrically connected to one side of the electrode plate, and the amorphous silicon region not implanted with ions acts as the isolation region between the other side of the electrode plate and the conductive region of the electrode layer. The manufacturing of the electrode layer and the dielectric layer in step c should be realized by a directional deposition process to avoid depositing materials on the sidewalls of the deep trench. Suitable processes include but are not limited to plasma enhanced chemical vapor deposition process and high density plasma enhanced chemical vapor deposition process. Preferably, in step d, the insulating material includes at least one of silicon oxynitride SiONx, alumina, hafnium dioxide, zirconium dioxide, and titanium dioxide, and the conductive material includes at least one of titanium nitride, tungsten, and titanium.

[0026] Preferably, in step f, the annealing temperature is 800 - 1000 °C.

[0027] The present invention has the following advantages and beneficial effects:

[0028] The deep trench capacitor of the present invention can achieve the highest capacitance density in the same type of design, as well as more excellent equivalent series resistance (ESR) and equivalent series inductance (ESL) performance. It can reduce the size of the capacitor, improve the integration of the device, and meet the increasingly stringent miniaturization requirements of advanced packaging technology.

[0029] The deep trench capacitor of the present invention can achieve an extremely high operating frequency and an ultra-wide decoupling bandwidth, and can meet the increasingly high requirements for power integrity in integrated circuits. It has flexible design and can be flexibly produced with different capacitance values for various application scenarios. The capacitor is easy to connect with external functional circuits, greatly simplifies the connection process between the capacitor and external functional circuits, reduces costs, and simplifies the structure.

[0030] For the deep trench capacitor of the present invention, due to the three-dimensional property of the deep trench itself, the capacitance occupies a small area on the silicon, which can effectively reduce the production cost in future mass production.

[0031] The manufacturing method of the present invention has a simple process and is easy to implement, facilitating industrial production. Description of the Drawings

[0032] Figure 1 It is a schematic flow chart of a manufacturing method of a deep trench capacitor provided in Embodiment 2 of the present invention;

[0033] Figure 2 It is a schematic flow chart of a manufacturing method of a deep trench capacitor provided in Embodiment 3 of the present invention;

[0034] Figure 3 It is a schematic structural diagram after ion implantation in a specific area on a silicon wafer provided in Embodiment 3 of the present invention;

[0035] Figure 4 It is a schematic structural diagram after making a deep trench structure on a silicon wafer provided in Embodiment 3 of the present invention;

[0036] Figure 5 In it, a - e is a schematic flow chart of preparing an electrode layer and a dielectric layer provided in Embodiment 3 of the present invention;

[0037] Figure 6 It is a schematic structural diagram after backfilling the deep trench cavity provided in Embodiment 3 of the present invention;

[0038] Figure 7 It is a schematic structural diagram after removing the hard mask provided in Embodiment 3 of the present invention;

[0039] Figure 8 It is a schematic structural diagram after the preparation of the ILD layer provided in Embodiment 3 of the present invention;

[0040] Figure 9 It is a schematic structural diagram after the preparation of the contact hole array provided in Embodiment 3 of the present invention;

[0041] Figure 10 It is a schematic structural diagram of the deep trench capacitor obtained after sputtering tungsten metal on the contact hole array provided in the embodiment of the present invention;

[0042] In the figure, 110 is a silicon wafer; 120 is a sidewall; 1201 is a positive electrode plate; 1202 is a negative electrode plate; 130 is a hard mask; 140 is an electrode layer; 150 is a dielectric layer; 160 is a backfill layer; 170 is an ILD layer; 180 is a filled conductive material. Detailed implementation manners

[0043] For a better understanding of the present invention, the following embodiments are further descriptions of the present invention, but the content of the present invention is not limited to the following embodiments only.

[0044] Embodiment 1

[0045] As Figure 10 shown, a deep trench capacitor, the positive electrode plate 1201 and the negative electrode plate 1202 of the capacitor are respectively located on both sidewalls 120 of the deep trench, and the two sides of the sidewall 120 are the positive electrode plate 1201 and the negative electrode plate 1202 respectively. The electrode layer 140 and the dielectric layer 150 are alternately stacked in the deep trench to form an interleaved multi-layer structure. Each electrode layer 140 is electrically conductive in a partial area, and one side electrode plate in contact with the conductive area is electrically connected thereto. Adjacent electrode layers 140 are alternately electrically connected to the positive electrode plate 1201 or the negative electrode plate 1202. The electrode layer 140 and the electrode plate both have a conductive function, and the dielectric layer 150 has an insulating function. The electrode layer 140 and the dielectric layer 150 only cover the bottom of the deep trench, and there is no coverage on the sidewall 120. A contact hole array is provided and filled with a conductive material. Any contact hole can lead out a corresponding positive or negative lead-out port and be connected to a functional circuit as required.

[0046] The electrode layer 140 and the dielectric layer 150 are alternately stacked for 10 - 60 layers. In this embodiment, it is preferably alternately stacked for 10 layers, and the number of layers can also be set as required in other embodiments.

[0047] Each electrode layer 140 is only electrically connected to one electrode plate, and an isolation area is provided near the junction with the other electrode plate to block its electrical connection. During the stacking process, the electrode layer 140 is alternately electrically connected to the positive electrode plate 1201 and the negative electrode plate 1202 to form an alternating arrangement of positive and negative electrode layers inside the deep trench. That is, each electrode layer 140 is only electrically connected to the positive electrode plate 1201 or the negative electrode plate 1202, and the electrical connection is blocked at the junction with the negative electrode 1202 or the positive electrode 1201.

[0048] Embodiment 2

[0049] As Figure 1 shown, a manufacturing method of a deep trench capacitor includes the following steps:

[0050] Step a: Perform ion implantation on a specified area of a silicon substrate;

[0051] Step b: Perform deep silicon etching on the silicon substrate to fabricate a deep trench structure with the ion implantation regions as the two sidewalls;

[0052] Step c: Prepare an amorphous silicon thin film at the bottom of the deep trench, and control the conductivity of some regions thereof by ion implantation and contact with one sidewall of the deep trench structure to form an electrode layer.

[0053] Step d: Deposit an insulating material on the surface of the amorphous silicon thin film to prepare a dielectric layer, and continue to prepare an amorphous silicon thin film on the surface of the dielectric layer. Control the conductivity of some regions thereof by ion implantation and contact with the other sidewall of the deep trench structure to form an electrode layer. Repeat this step to alternately stack multiple electrode layers and dielectric layers in the deep trench to form a multi-layer structure with alternating electrode layers and dielectric layers, and adjacent electrode layers are alternately connected to the two sidewalls of the deep trench;

[0054] Step e: Backfill the remaining cavity part in the deep trench with silicon material;

[0055] Step f: Anneal the entire structure to activate the implanted ions;

[0056] Step g: Perform CMP (Chemical Mechanical Polishing) planarization and ILD (Inter Layer Dielectric) layer preparation;

[0057] Step h: Prepare a contact hole array for the electrode plate by lithography, development, and etching of the ILD layer;

[0058] Step i: Sputter a conductive material to fill the contact hole array and perform CMP to remove the excess conductive material on the surface. Any contact hole can lead out the corresponding positive or negative lead port and be connected to the functional circuit as required.

[0059] In step a, p-type doping of the silicon substrate is achieved by ion implantation. The ion implantation regions conduct electricity to form the positive and negative plates of the capacitor, and the implanted ion species is gallium ions.

[0060] In step b, the hard mask used in the deep silicon etching process is retained and removed after step e is completed.

[0061] The hard mask used in the deep silicon etching process in step b is not removed after the deep trench is formed to prevent material deposition in regions outside the deep trench in subsequent steps.

[0062] In step c, p-type doping is achieved by ion implantation, enabling some regions of amorphous silicon to conduct electricity and act as the electrode layer. This electrode layer is electrically connected to only one side of the electrode plate, and the amorphous silicon regions not subjected to ion implantation act as the isolation region between the other side of the electrode plate and the conductive region of the electrode layer. In step c, the fabrication of the electrode layer and the dielectric layer should be realized through a directional deposition process to avoid depositing materials on the sidewalls of the deep trench. Suitable processes include, but are not limited to, plasma-enhanced chemical vapor deposition process and high-density plasma-enhanced chemical vapor deposition process. Preferably, in step d, the insulating material includes at least one of silicon oxynitride SiONx, alumina, hafnium dioxide, zirconium dioxide, and titanium dioxide, and the conductive material includes at least one of titanium nitride, tungsten, and titanium.

[0063] In step f, the annealing temperature is 800 - 1000 °C.

[0064] Example 3

[0065] As Figure 2 shown, a method for manufacturing a deep trench capacitor includes the following steps:

[0066] Step S101: Ion implantation is performed on a designated area of the silicon wafer 110;

[0067] After completing the ion implantation of the designated area of the silicon wafer 110, the ion-implanted area becomes conductive and acts as the positive electrode plate 1201 and the negative electrode plate 1202 of the capacitor. Finally, the ion-implanted area on the silicon wafer 110 as shown in Figure 3 is obtained as the sidewall 120 of the deep trench.

[0068] The form of ion implantation in this step can be p-type doping.

[0069] Step S102: Deep silicon etching is performed on the silicon wafer 110 to fabricate a deep trench structure with the ion-implanted area as the sidewall 120, and the hard mask used in the process is retained.

[0070] First, a hard mask 130 is deposited on the surface of the smooth silicon wafer 110, and then a photoresist is coated on the hard mask 130. The pattern is transferred to the hard mask 130 through the photolithography and development steps. Deep silicon etching can be performed using, for example, the Bosch process to etch the required deep trench in the silicon wafer 110. After the deep trench is prepared, the hard mask 130 is retained to protect the area outside the deep trench from the influence of deposited materials in subsequent manufacturing steps. The etching position of the deep trench should be the ion-implanted area to enable the ion-implanted area to become the sidewall 120 of the deep trench after etching is completed. Figure 4 The structure after the deep trench is prepared is shown as follows.

[0071] Step S103: Prepare an amorphous silicon thin film at the bottom of the deep groove, and control its conductive region by means of ion implantation to form the electrode layer 140a. Then deposit an insulating material on the amorphous silicon thin film to complete the preparation of the dielectric layer 150, and continue to prepare an amorphous silicon thin film on the surface of the dielectric layer 150. Control the conductivity of its partial region by means of ion implantation to form the preparation of the electrode layer 140b, and repeat the foregoing steps to stack dozens of layers.

[0072] As Figure 5 Shown in a - e of is a schematic flow chart of preparing the electrode layer 140 and the dielectric layer 150 in the deep groove, that is, the electrode layer 140 and the dielectric layer 150 are alternately prepared at the bottom of the deep groove. First, prepare the electrode layer 140a at the bottom of the deep groove, and the material of the electrode layer 140a is amorphous silicon. Then, realize the p - type doping of the electrode layer 140a through the ion implantation process. Figure 5 The shaded part of 140a in b is the ion implantation region. After ion implantation, the conductive shaded area in the electrode layer 140a realizes the electrical connection between the electrode layer 140a and one side electrode plate, and the non - shaded area not subjected to ion implantation realizes the electrical insulation between the electrode layer 140a and the other side electrode plate. Both the electrode layer 140a and the dielectric layer 150 are only prepared at the bottom of the deep groove without the phenomenon of step coverage.

[0073] After the preparation of the electrode layer 140a is completed, continue to deposit an insulating material on the electrode layer 140a to prepare the dielectric layer 150.

[0074] After the preparation of the dielectric layer 150 is completed, continue to prepare the electrode layer 140b on the dielectric layer 150. The difference between the electrode layer 140b and the electrode layer 140a is that they realize electrical connection with different side electrode plates.

[0075] Then repeat the alternating preparation of the electrode layer 140 and the dielectric layer 150. For the electrode layer 140, the electrode layers 140 connected to the positive electrode plate 1201 and the negative electrode plate 1202 should be alternately prepared to realize the alternating arrangement of the positive and negative electrode layers 140. The stacking layers of the electrode layer 140 and the dielectric layer 150 range from several layers to dozens of layers, which are specifically determined according to the capacitance value of the designed capacitor and the process requirements.

[0076] The insulating material in this step may include: insulating silicon oxides such as silicon oxynitride SiONx, aluminum oxide Al2O3, hafnium dioxide HfO2, zirconium dioxide ZrO2 or titanium dioxide TiO2, metal oxides or mixed materials, etc. Its requirements are to have good adhesion with the electrode plate layer material, have a relatively high relative dielectric constant, and have good compatibility with the preparation process. In this embodiment, silicon nitride is preferably selected, and in other embodiments, appropriate insulating materials can also be selected according to needs.

[0077] To meet the requirement that the electrode layer and the dielectric layer are prepared from bottom to top only in the deep trench without any step coverage, a directional deposition process can be used. The PECVD (plasma chemical vapor deposition) process or the HDP (High Density Plasma) process can be used for filling.

[0078] Step S104: Backfill the deep trench cavity with silicon material.

[0079] As Figure 6 shown, after the electrode layer 140 and the dielectric layer 150 are prepared, there is still some empty space in the deep trench. This space is backfilled with silicon material to form the backfill layer 160.

[0080] Step S105: Remove the hard mask 130.

[0081] The schematic diagram of the structure after this step is as Figure 7 shown, where the hard mask 130 remaining after the deep silicon etching in step S102 is removed.

[0082] Step S106: Anneal at 800 - 1000 °C to activate the impurity ions.

[0083] Step S107: CMP planarization and preparation of the ILD layer 170.

[0084] In this step, the ILD layer 170 is prepared by depositing silicon dioxide, and planarization is achieved through CMP. Finally, the ILD layer 170 as shown in Figure 8 is obtained.

[0085] Step S108: Prepare the contact hole array of the electrode plate 140 and fill it with a conductive material.

[0086] The contact hole array of each electrode plate 140 is prepared by lithography, development, and etching of the ILD layer 170. The prepared contact hole array is as Figure 9 shown, Figure 9 and the depressions on the ILD layer 170 in

[0087] are the contact hole arrays. After that, a conductive material is sputtered to fill the contact hole array, and the excess material is removed through the CMP process. The conductive material includes tungsten, or other alternative metallic elements or alloys such as copper, titanium nitride, and aluminum. Tungsten is preferably used in this embodiment, and other suitable conductive materials can also be selected according to requirements in other embodiments.

[0088] Figure 10The figure shows a schematic diagram of the structure after the contact holes are filled with a conductive material, and 180 is the filled conductive material. Any contact hole can lead to the corresponding positive or negative lead port and be connected to the functional circuit as required.

[0089] In this embodiment, the novel deep trench capacitor can achieve a capacitance density approximately three times that of the traditional deep trench capacitor under the same process conditions through theoretical verification; in terms of application, compared with the traditional deep trench capacitor, the novel deep trench capacitor has a smaller minimum repeating unit structure. This gives it better flexibility in design and allows it to achieve different capacitance values for various complex application scenarios. The higher capacitance density allows the novel deep trench capacitor to reduce the number of parallel repeating units, reducing the size of the capacitor, thereby resulting in better equivalent series resistance (ESR) and equivalent series inductance (ESL) performance. Thanks to the design of the internal structure of the deep trench, the capacitor only requires a pair of positive and negative plates and both the positive and negative plates can be exposed on the silicon wafer surface. This enables the capacitor to be directly connected to the functional circuit after the contact holes are prepared and filled, without the need to connect the contact holes through the damascene process level. This greatly simplifies the capacitor structure and reduces the equivalent series resistance (ESR) and equivalent series inductance (ESL).

[0090] The above is the preferred implementation manner of the present invention. Of course, the scope of the rights of the present invention cannot be limited thereby. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and changes can be made, and these improvements and changes are also regarded as the protection scope of the present invention.

Claims

1. A deep groove capacitor, characterized in that: The positive and negative plates of the capacitor are respectively located on the two side walls of the deep groove. The electrode layers and the dielectric layers are alternately stacked in the deep groove to form an interleaved multi-layer structure, and adjacent electrode layers are alternately electrically connected to the positive or negative plate.

2. The deep trench capacitor according to claim 1, wherein: Only a partial area of each electrode layer is conductive and is electrically connected to the electrode plate on the side in contact with the conductive area.

3. The deep trench capacitor according to claim 1, characterized in that: The electrode layers and the dielectric layers are alternately stacked 10 - 60 layers.

4. The deep groove capacitor according to claim 1, characterized in that: Each electrode layer is only electrically connected to the positive or negative plate and is insulated from the junction of the negative or positive electrode.

5. A manufacturing method of a deep groove capacitor, characterized in that, It includes the following steps: Step a: Perform ion implantation on a specified area of the silicon substrate. Step b: Perform deep silicon etching on the silicon substrate to fabricate a deep groove structure with the ion implantation area as the two side walls. Step c: Prepare an amorphous silicon thin film at the bottom of the deep groove, and control the conductivity of its partial area by ion implantation and make it contact one side wall of the deep groove structure to form an electrode layer. Step d: Deposit an insulating material on the surface of the amorphous silicon thin film to prepare a dielectric layer, continue to prepare an amorphous silicon thin film on the surface of the dielectric layer, control the conductivity of its partial area by ion implantation and make it contact the other side wall of the deep groove structure to form an electrode layer, repeat this step, alternately stack multiple electrode layers and dielectric layers in the deep groove to form an interleaved multi-layer structure of electrode layers and dielectric layers, and adjacent electrode layers are alternately connected to the two side walls of the deep groove. Step e: Backfill the remaining cavity part in the deep groove with silicon material. Step f: Anneal the whole structure to activate the implanted ions. Step g: Perform CMP planarization and ILD layer preparation. Step h: Prepare a contact hole array of the electrode plate by photolithography, development, and etching of the ILD layer. Step i: Sputter a conductive material to fill the contact hole array and perform CMP to remove the excess conductive material on the surface. Any contact hole can lead out a corresponding positive or negative lead-out port and be connected to a functional circuit as required.

6. The manufacturing method of the deep trench capacitor according to claim 5, characterized in that: In step a, p-type doping of the silicon substrate is achieved by ion implantation, and the ion implantation area becomes conductive to form the positive and negative plates of the capacitor.

7. The manufacturing method of the deep trench capacitor according to claim 5, characterized in that: In step b, the hard mask used in the deep silicon etching process is retained and removed after step e is completed.

8. The manufacturing method of the deep trench capacitor according to claim 5, characterized in that: In step c, p-type doping is achieved by ion implantation, making a partial area of the amorphous silicon conductive to act as an electrode layer. This electrode layer is only electrically connected to one side electrode plate, and the non-ion-implanted amorphous silicon area acts as an isolation area between the other side electrode plate and the conductive area of the electrode layer.

9. The manufacturing method of the deep trench capacitor according to claim 5, characterized in that: In step d, the insulating material includes at least one of silicon oxynitride SiONx, alumina, hafnium dioxide, zirconium dioxide, and titanium dioxide. In step i, the conductive material includes at least one of titanium nitride, tungsten, and titanium.

10. The manufacturing method of the deep trench capacitor according to claim 5, characterized in that: In step f, the annealing temperature is 800 - 1000 °C.

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