Transistor triggered silicon controlled rectifier

Abstract

The present disclosure relates to semiconductor structures, and more particularly to transistor triggered silicon controlled rectifiers (SCRs) and methods of manufacture. The structure comprises a vertical silicon controlled rectifier; and a trigger device adjacent to the vertical silicon controlled rectifier, the trigger device and the vertical silicon controlled rectifier sharing a diffusion region within the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to transistor-triggered silicon controlled rectifiers (SCRs) and manufacturing methods therefor. Background Art

[0002] SCRs are used for electrostatic discharge (ESD) protection of integrated circuits (ICs) to prevent sudden currents caused by, for example, contact, electrical short circuits, or dielectric breakdown. Due to the high current handling capacity per unit area of SCRs, ESD devices utilizing SCRs can protect ICs from faults. These devices are most commonly used in high-performance analog and radio frequency (RF) designs of chips with large signal swings, low leakage, and low capacitance. The RF performance may be affected due to the poor harmonics and capacitive loading of SCRs. Summary of the Invention

[0003] In one aspect of the present disclosure, a structure includes: a vertical silicon controlled rectifier; and a trigger device adjacent to the vertical silicon controlled rectifier, the trigger device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate.

[0004] In one aspect of the present disclosure, a structure includes: a vertical silicon controlled rectifier including a diffusion region in a semiconductor substrate of a first dopant type; a lateral trigger device sharing the diffusion region with the vertical silicon controlled rectifier, the diffusion region being a source region for the lateral trigger device; and a body contact of a second dopant type connected to ground and tied to the semiconductor substrate.

[0005] In one aspect of the present disclosure, a method includes: forming a vertical silicon controlled rectifier; and forming a trigger device adjacent to the vertical silicon controlled rectifier, the trigger device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate. Brief Description of the Drawings

[0006] In the following detailed description, the present disclosure is described with reference to the indicated plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.

[0007] Figure 1 A transistor-triggered silicon controlled rectifier (SCR) and a corresponding manufacturing process according to an aspect of the present disclosure are shown.

[0008] Figure 2 A transistor-triggered SCR and a corresponding manufacturing process according to an additional aspect of the present disclosure are shown.

[0009] Figure 3 A top view of a transistor taken along line A-A according to an aspect of the present disclosure is shown. Figure 1 is shown.

[0010] Figure 4 A top view of a transistor taken along line A-A according to an additional aspect of the present disclosure Figure 1 is shown.

[0011] Figures 5A - 5D A cross-sectional view of steps in a manufacturing process of an SCR triggered by a transistor according to a further aspect of the present disclosure Figure 1 is shown. DETAILED DESCRIPTION

[0012] The present disclosure relates to semiconductor structures, and more particularly to transistor-triggered silicon controlled rectifiers (SCRs) and manufacturing methods. In an embodiment, the transistor-triggered SCR can be a vertical bipolar transistor having a lateral trigger transistor. The trigger transistor can be an NMOS or a PMOS, and the SCR can be a PNPN or an NPNP. Advantageously, the structures described herein exhibit a reduced trigger voltage and a faster switching time.

[0013] The structures of the present disclosure can be fabricated in a variety of different ways using a variety of different tools. However, generally, methods and tools are used to form structures having micron and nanometer scale dimensions. Methods (i.e., techniques) for fabricating the structures of the present disclosure have been adopted in accordance with integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned on top of the wafer by a lithography process. Specifically, the fabrication of the structures uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by lithographic imaging; and (iii) selectively etching the film with respect to the mask. Additionally, as is known in the art, a pre-clean process can be used to clean any contaminants on the etched surface. Additionally, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0014] Figure 1 A transistor-triggered silicon controlled rectifier (SCR) and a corresponding manufacturing process according to an aspect of the present disclosure are shown. Figure 1 The structure 10 includes a transistor 18 and an SCR 20 located above a p-well 14 in a semiconductor substrate 12. The p-well 14 can be formed by a conventional ion implantation process known in the art using a p-type dopant (e.g., boron (B)), and thus, no further explanation is required to fully understand the present disclosure. The p-well 14 can be disposed within or defined by a deep n-well 15 for isolating the p-well 14. A deep trench isolation structure 16 can also be used to isolate the p-well 14, such as isolating the transistor 18 and the SCR 20.

[0015] The semiconductor substrate 12 can be composed of any suitable semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other group III / V or II / VI compound semiconductors. The semiconductor substrate 12 can also include any suitable single crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). In additional embodiments, the semiconductor substrate 12 can be a bulk substrate including the semiconductor materials described herein, or can include semiconductor-on-insulator technology known in the art. In semiconductor-on-insulator technology, the semiconductor substrate 12 will be the top semiconductor layer known in the art located above the insulator material and the processing substrate.

[0016] In an embodiment, the structure 10 includes a transistor 18 and an SCR 20. The transistor 18 can be a lateral NMOS transistor; while the SCR 20 can be a vertical PNPN SCR. In an embodiment, the transistor 18 can be a trigger device for the SCR 20.

[0017] The transistor 18 includes a gate structure 22 and N+ diffusion regions 24a (N+ source region) and 24b (N+ drain region) shown in more detail with reference Figure 3 and Figure 4 thereof. The gate structure 22 can be any conventional gate structure, such as a polysilicon gate structure or a metal gate structure. In a polysilicon configuration, the gate structure 22 can have a partially or fully silicided region on the top surface. The gate structure 22 can be grounded or placed at a different bias. The N+ diffusion regions 24a, 24b (N+ source region and N+ drain region) can be disposed within the p-well 14, e.g., directly fixed to the p-well 14. The N+ diffusion regions 24a, 24b can include a fully or partially silicided region on the top surface.

[0018] The vertical SCR 20 includes a P+ emitter 30, an N+ base region 32, and the N+ diffusion region 24a. As described herein, the N+ diffusion region 24a is shared by the transistor 18 and the SCR 20. Additionally, the SCR 20 includes a p+ collector region 14a located within the p-well 14 and between the base region 32 and the N+ diffusion region 24a. Thus, the SCR 20 is a PNPN device.

[0019] The N+ base region 32 can be laterally isolated from the N+ diffusion region 24a by sidewall spacers 28. In an embodiment, the sidewall spacers 28 can be an oxide material, a nitride material, or a combination thereof. The base region 32 can include an outer base region 32a (e.g., an N+ tap region) that is in direct contact with the base region 32. The N+ tap region 32a can be isolated from the P+ emitter 30 by an insulator material 33. Additionally, the base region 32a and the P+ body contact 26 can include a fully or partially silicided region on the top surface.

[0020] The P+ emitter 30 can include a polysilicon material, and the base region 32 can include, for example, n-doped SiGe. The n-doped SiGe can be epitaxially grown on the semiconductor substrate 12 by in-situ doping. In an embodiment, the in-situ doping can be an n-type dopant, such as arsenic (As), phosphorus (P), and antimony (Sb), and other suitable examples.

[0021] The P+ body contact 26 can be disposed in the P-well 14 and adjacent to the gate structure 22. The P+ body contact 26 can include a fully or partially silicided region on the top surface. In an embodiment, the P+ body contact 26 is grounded (GND); that is, the P+ body contact 26 is not floating.

[0022] The outer base region 32a, the P+ emitter 30, the N+ diffusion region 24a, and the P+ body contact 26 are connected to a wiring structure 34. In an embodiment, the P+ body contact 26 is connected to ground (GND). In another embodiment, the N+ diffusion region 24a is connected to the cathode, and the P+ emitter 30 is connected to the anode. In an embodiment, the gate structure 22 can also be fixed to the anode of the device.

[0023] Figure 2 A transistor-triggered SCR according to an additional aspect of the present disclosure is shown. Figure 2 The structure 10a includes a lateral PMOS transistor and a vertical NPNP SCR.

[0024] In an embodiment, the structure 10a includes an n-well 15 in the semiconductor substrate 12. The n-well 15 can be formed by a conventional ion implantation process known in the art using an n-type dopant (such as arsenic (As), phosphorus (P), and antimony (Sb), and other suitable examples). The deep trench isolation structure 16 can be used to isolate the n-well 15, such as the transistor 18 and the SCR 20. The semiconductor substrate 12 can be composed of any suitable semiconductor material having any suitable single crystal orientation, as has been disclosed herein. In another embodiment, the semiconductor substrate 12 can be a bulk substrate or can include semiconductor-on-insulator technology known in the art.

[0025] Still referring to Figure 2, transistor 18 can be a triggering device for SCR 20. Transistor 18 includes a gate structure 22 and P+ diffusion regions 24'a and a P+ diffusion region (not shown in this view). The gate structure 22 can be any conventional gate structure, such as a polysilicon gate structure or a metal gate structure. In a polysilicon configuration, the gate structure 22 can have a partially or fully silicided region on the top surface. The gate structure 22 can be grounded or placed at a different bias. The P+ diffusion region 24a (e.g., P+ source and drain regions) can be disposed within the n-well 15.

[0026] The vertical SCR 20 includes an N+ emitter 30', a P+ base region 32', a collector region 15a within the n-well 15, and the P+ diffusion region 24'a. Thus, SCR 20 is an NPNP device. As described herein, the P+ diffusion region 24'a is shared by the transistor 18 and the SCR 20.

[0027] The P+ base region 32' can be laterally isolated from the P+ diffusion region 24'a by a sidewall spacer 28 (e.g., an oxide material, a nitride material, or a combination thereof). The base region 32' can include an outer base region 32'a (e.g., a P+ tap region) that is in direct contact with the base region 32'. The N+ emitter 30' can include a polysilicon material, and the base region 32' can include, for example, p-doped SiGe epitaxially grown on the semiconductor substrate 12 using in-situ doping (e.g., a p-type dopant). The N+ body contact 26' is fixed to the n-well 15 and is adjacent to the gate structure 22.

[0028] The outer base region 32'a, the N+ emitter 30', the P+ diffusion region 24'a, and the N+ body contact 26' are connected to a wiring structure 34. In an embodiment, the N+ body contact 26 is connected to ground (GND). In another embodiment, the P+ diffusion region 24'a is connected to the anode, and the N+ emitter 30' and the base region 32' are connected to the cathode.

[0029] Figure 3 and Figure 4 shows different top views of different configurations of the transistor 18 taken along line A-A. Those skilled in the art should recognize that by simply changing the dopant types of the diffusion region 24a, the drain region 24b, and the body contact 26, Figure 1 the top views shown in Figure 3 and Figure 4 can equally represent the structure 10a shown in Figure 2 .

[0030] In Figure 3In [the figure], the transistor 18 includes a single diffusion region 24a (source region) located on one side of the gate structure 22 and a plurality of diffusion regions 24b (drain regions) located on the opposite side of the gate structure 22. In this embodiment, the drain region 24b includes two tabs located at opposite ends of the P+ body contact 26. On the other hand, Figure 4 shows the alternating tabs of the drain region 24b that are interleaved with the P+ body contact 26.

[0031] Figures 5A - 5D shows Figure 1 a cross-sectional view of the steps in the manufacturing process of an SCR triggered by the transistor shown in [the figure]. Those skilled in the art should recognize that Figures 5A - 5D the manufacturing process shown in [the figure] can equally represent Figure 2 the manufacturing process of an SCR triggered by the transistor shown in [the figure] by changing the dopant type.

[0032] As Figure 5A shown, for example, a p-well 14 is formed in the semiconductor substrate 12 using a conventional ion implantation process known in the art. The deep trench isolation structure 16 is formed in the semiconductor substrate 12, surrounding the p-well 14.

[0033] The deep trench isolation structure 16 can be formed by conventional photolithography, etching, and deposition processes. For example, a resist formed over the semiconductor substrate 12 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). Using an etching process with selective chemical action, such as reactive ion etching (RIE), the pattern is transferred from the photoresist layer to the semiconductor substrate 12 to form one or more trenches in the semiconductor substrate 12 through the openings in the resist. After removing the resist by a conventional oxygen ashing process or other known strippers, an insulator material (e.g., SiO2) can be deposited by any conventional deposition process (e.g., CVD process). Any residual material on the surface of the semiconductor substrate 12 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0034] Figure 5B shows the formation of the source region 24a and the body contact 26. Those skilled in the art should understand that the drain region 24b can also be formed simultaneously with the source region 24a. The source region 24a, the drain region 24b, and the body contact 26 can be formed by introducing different dopants with a certain concentration and opposite conductive types into the semiconductor substrate 12.

[0035] In an embodiment, a corresponding patterned implantation mask can be used to define the selected regions exposed for implantation. The implantation mask for selecting the exposed regions used to form the source region 24a and the drain region 24b is stripped after implantation and before the implantation mask for forming the body contact 26 (or vice versa). Similarly, the implantation mask for selecting the exposed regions used to form the body contact 26 is stripped after the implantation is performed. The implantation mask can include a photosensitive material layer, such as an organic photoresist layer, which is applied by a spin coating process, then pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer. Each implantation mask has a thickness and stopping power sufficient to prevent the masked regions from receiving a certain dose of implanted ions. The body contact 26 is doped with a p-type dopant, such as boron (B), and the source region 24a (and the drain region 24b) is doped with an n-type dopant (e.g., arsenic (As), phosphorus (P), and Sb), and other suitable examples. It should be recognized that opposite dopant types can be used to form Figure 2 the structure 10a.

[0036] Still referring to Figure 5B , the gate structure 22 can be formed by conventional gate fabrication processes. For example, a gate dielectric material (e.g., a high-k dielectric material or a low-k dielectric material) can be deposited on the semiconductor substrate 12, and then a polysilicon material is deposited. The gate dielectric material can be formed by conventional atomic layer deposition (ALD) or CVD processes (including plasma-enhanced CVD (PECVD) processes). The polysilicon material can be deposited by a CVD process. After the deposition process, the gate dielectric material and the polysilicon material are patterned using conventional lithography and etching processes known in the art. The gate structure 22 can also include sidewall spacers, including oxides, nitrides, or combinations thereof. The sidewall spacers can be fabricated using conventional deposition processes (e.g., CVD) and subsequent anisotropic etching processes.

[0037] Figure 5C The fabrication of the base region 32 and the sidewall spacers 28 is shown. The base region 32 can be fabricated by using a conventional epitaxial growth process with in-situ doping. In Figure 1 the structure, the doping is an n-type dopant; while in Figure 2 the structure, the doping is a p-type dopant. After conventional patterning processes (e.g., lithography and etching), the sidewall spacers 28 can be formed by the conventional deposition and anisotropic etching processes already disclosed herein.

[0038] Figure 5D The fabrication of the emitter region 30 and the tap region 32a (e.g., the outer base) is shown. The emitter region 30 can be fabricated by using a conventional epitaxial growth process with in-situ doping. In Figure 1 the structure, the doping is a p-type dopant; while inFigure 2 In the structure, the doping is an n-type dopant. After a conventional deposition process for forming the sidewall spacers (insulating material) 33 and a patterning process for exposing a portion of the base region 32, the emitter region 30 can be epitaxially grown in contact with the base region 32.

[0039] Return to reference Figure 1 , a wiring structure 34 is formed using conventional photolithography, etching, and deposition processes. For example, an interlayer dielectric material can be deposited by a conventional deposition method (e.g., CVD). The interlayer dielectric material can be deposited by conventional photolithography and etching processes to form trenches exposing the outer base region 32a, P+ emitter 30, N+ source region 24a, and P+ body contact 26. A conductive material is deposited into the trenches to form the wiring structure 34. The conductive material can be aluminum, copper, tungsten, or other known materials. To prevent outward diffusion, the sidewalls of the trenches can be lined with TaN or TiN, as is well known in the art.

[0040] These structures can be used in system-on-a-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0041] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of an original wafer (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having one or both of surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products having a display, a keyboard, or other input devices and a central processor.

[0042] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements to the technologies found in the marketplace, or to enable other ordinary skilled artisans in the technical field to understand the embodiments disclosed herein.

Claims

1. A structure, comprising: A vertical silicon controlled rectifier; And A trigger device adjacent to the vertical silicon controlled rectifier, the trigger device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate.

2. The structure according to claim 1, wherein, The vertical silicon controlled rectifier includes a PNPN device, and the trigger device includes a lateral NMOS transistor.

3. The structure according to claim 2, wherein, The shared diffusion region includes the N+ source region of the NMOS transistor and the N+ contact of the PNPN device.

4. The structure according to claim 3, wherein, The PNPN device includes a P+ emitter, an N+ base, a P+ collector region, and the N+ contact, the N+ contact being shared by the NMOS transistor.

5. The structure according to claim 2, wherein, The NMOS transistor includes a gate structure, the gate structure including silicided polysilicon.

6. The structure according to claim 2, further comprising a P+ body contact connected to ground and fixed to a p-well in the semiconductor substrate.

7. The structure according to claim 1, wherein, The vertical silicon controlled rectifier includes an NPNP device, and the trigger device includes a PMOS transistor.

8. The structure according to claim 7, wherein, The PMOS transistor is a lateral PMOS transistor.

9. The structure according to claim 8, wherein, The shared diffusion region includes the P+ source region of the PMOS transistor and the P+ contact of the NPNP device.

10. The structure according to claim 9, wherein, The NPNP device includes an N+ emitter, a P+ base, an N+ collector region, and the P+ contact, the P+ contact being shared by the PMOS transistor.

11. The structure according to claim 7, wherein, The lateral PMOS transistor includes a gate structure, the gate structure including silicided polysilicon.

12. The structure according to claim 7, further comprising an N+ body contact connected to ground and fixed to an n-well in the semiconductor substrate.

13. The structure according to claim 1, further comprising a body contact of a first dopant type fixed to the semiconductor substrate, the body contact connected to ground and interleaved with a drain region of the trigger device, the drain region having a second dopant type.

14. A structure, comprising: A vertical silicon controlled rectifier including a diffusion region in a semiconductor substrate of a first dopant type; A lateral trigger device sharing the diffusion region with the vertical silicon controlled rectifier, the diffusion region being a source region for the lateral trigger device; And A body contact of a second dopant type connected to ground and fixed to the semiconductor substrate.

15. The structure according to claim 14, wherein The vertical silicon controlled rectifier includes a PNPN device, and the trigger device includes an NMOS transistor, the diffusion region includes an N+ diffusion region, and the body contact includes a P+ body contact fixed to a p-well in the semiconductor substrate.

16. The structure according to claim 15, wherein, The PNPN device includes a P+ emitter, an N+ base, a P+ collector region, and an N+ contact, the N+ contact being shared by the NMOS transistor.

17. The structure according to claim 14, wherein, The vertical silicon controlled rectifier includes an NPNP device, and the trigger device includes a PMOS transistor, the diffusion region includes a P+ diffusion region, and the body contact includes an N+ body contact fixed to an n-well in the semiconductor substrate.

18. The structure according to claim 17, wherein, The NPNP device includes an N+ emitter, a P+ base, an N+ collector region, and a P+ contact, the P+ contact being shared by the PMOS transistor.

19. The structure according to claim 14 further includes a deep trench isolation structure extending into the semiconductor substrate and surrounding the well, and the deep trench isolation structure also isolates the vertical thyristor rectifier and the lateral trigger device.

20. A method includes: forming a vertical thyristor rectifier; and forming a trigger device adjacent to the vertical thyristor rectifier, wherein the trigger device and the vertical thyristor rectifier share a diffusion region within the semiconductor substrate.

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