Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a gate structure between interlayer dielectric layers on a substrate; forming a metal covering layer above the gate structure; treating the substrate surface in an inductively coupled plasma chamber, the treating including oxidizing a surface of the metal capping layer and reducing an oxygen content in a top surface of the interlayer dielectric layer; performing a suppression step in the furnace to prevent SiN from growing on the interlayer dielectric layer; carrying out annealing treatment on the substrate in the smelting furnace; and selectively growing a silicon nitride dielectric cap on the gate structure in the furnace.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements on the various material layers.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems that need to be solved arise. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including the following steps. Form a gate structure between interlayer dielectric layers on a substrate. Form a metal capping layer over the gate structure. Selectively deposit a dielectric capping layer over the metal capping layer by performing an inhibition step in a furnace to prevent growth of the dielectric capping layer material on the interlayer dielectric layer, annealing the substrate in the furnace, and selectively growing the dielectric capping layer over the metal capping layer in the furnace.

[0005] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including the following steps. Form a gate structure between interlayer dielectric layers on a substrate. Selectively deposit a dielectric capping layer including silicon nitride over the gate structure by treating a surface of the substrate to reduce an oxygen content in a top surface of the interlayer dielectric layer, performing an inhibition step in a furnace to prevent growth of the silicon nitride on the interlayer dielectric layer, annealing the substrate in the furnace, and selectively growing the silicon nitride on the gate structure in the furnace.

[0006] Some embodiments of the present disclosure provide a semiconductor device, and include a gate structure, a plurality of gate spacers, and a silicon nitride dielectric capping member. The gate structure is disposed between interlayer dielectric layers on a substrate. The plurality of gate spacers are formed between the interlayer dielectric layer and the gate structure. The silicon nitride dielectric capping member is formed over the gate structure, wherein the silicon nitride dielectric capping member includes a silicon concentration of less than 40%, a nitrogen concentration of less than 45%, and an oxygen concentration of greater than 25%. Brief Description of the Drawings

[0007] Embodiments of the present disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A is a perspective view of a semiconductor device according to some embodiments;

[0009] Figure 1B illustrates, according to some embodiments, along Figure 1A the cross-sectional view taken along the X-X' cross-sectional line;

[0010] Figure 2 illustrates a process flow diagram of an exemplary process for forming a FET in a semiconductor device according to some embodiments;

[0011] Figures 3A to 3H is a cross-sectional view of a semiconductor device according to some embodiments, Figures 3A to 3H illustrating the semiconductor device at various manufacturing stages;

[0012] Figures 3I to 3J is a cross-sectional view of a semiconductor device according to some embodiments, Figures 3I to 3J illustrating the semiconductor device at various manufacturing stages;

[0013] Figure 4 illustrates a process flow diagram of an exemplary process for forming a FET in a semiconductor device according to some embodiments;

[0014] Figure 5 illustrates a block diagram of an exemplary dielectric gate overlay according to some embodiments;

[0015] Figure 6 illustrates a flow chart of an exemplary self-navigate deposition (SND) process configured to form an exemplary dielectric gate overlay according to some embodiments;

[0016] Figures 7A to 7D is a graphical schematic diagram providing the various process stages of an exemplary SND process according to some embodiments;

[0017] Figure 8 is a graphical schematic diagram providing an exemplary chemical reaction that occurs during the SND process according to some embodiments;

[0018] Figures 9A to 9D illustrates a chemical composition diagram of an exemplary semiconductor structure after forming a dielectric gate overlay using the SND process according to some embodiments;

[0019] Figure 9E A table showing exemplary concentrations of various elements in a dielectric gate capping layer formed over an MG according to some embodiments; and

[0020] Figures 10A to 10C A block diagram illustrating that an SND process configured to form a dielectric gate capping layer according to some embodiments can be applied to transistors having different height ratios between an MG and an ILD layer over an S / D region.

[0021]

Description of Symbols

[0022] 100: Semiconductor device

[0023] 101, 302, 901: Substrate

[0024] 103: Trench

[0025] 105: Isolation region

[0026] 107: Fin

[0027] 109: Virtual gate dielectric

[0028] 111: Virtual gate electrode

[0029] 113: Spacer

[0030] 115: Virtual stack

[0031] 117, 310: Source / drain region / S / D region

[0032] 119: Interlayer dielectric layer / ILD layer

[0033] 200, 400: Process

[0034] 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232: Steps

[0035] 300, 900: Semiconductor structure

[0036] 304: Opening

[0037] 306, 306a, 306b: Spacer layer

[0038] 308: ILD0 layer / ILD layer

[0039] 309, 315: Surface

[0040] 312: Metal gate / MG

[0041] 314, 906: Metal capping layer

[0042] 316,904: Dielectric gate overlay

[0043] 318: ILD1 layer / ILD layer

[0044] 320: Hard mask

[0045] 321,322: Opening

[0046] 324: Silicide contact

[0047] 326: Source / drain contact / MD

[0048] 327,338: IMD layer

[0049] 328,340: ESL

[0050] 330,342: ILD2 layer

[0051] 332,344: VG contact

[0052] 334,346: VD contact

[0053] 336: ILD1 layer

[0054] 422,424,425,428,430,432: Step

[0055] 502: Dielectric gate overlay

[0056] 504,902: MG

[0057] 506,905: Gate spacer

[0058] 508: ILD0 layer

[0059] 600: SND process

[0060] 602: Surface treatment stage

[0061] 604: Inhibition stage

[0062] 606: Annealing treatment stage

[0063] 608: Deposition stage

[0064] 701: Inductively coupled plasma chamber

[0065] 702: Furnace

[0066] 802,804,806: Step

[0067] 903: ILD layer

[0068] 907: Height

[0069] 912: Si content

[0070] 922: Tungsten content

[0071] 932, 934: Concentration

[0072] 940: Table

[0073] 942, 944, 946, 948: Rows

[0074] 1002, 1012, 1022: Dielectric gate overlay

[0075] 1003, 1013, 1023, H1: Height

[0076] 1004, 1014, 1024: MG / Gate region

[0077] 1005, 1015, 1025, H2: Height

[0078] 1006, 1016, 1026: ILD layer

[0079] 1008, 1018, 1028: Gate spacer

[0080] X - X’: Section line Detailed implementation manners

[0081] The following disclosure provides many configurations to implement different embodiments or examples of different features of the provided subject matter. The following describes specific examples of each component and setting to simplify this disclosure. Of course, these are merely exemplary and are not intended to limit this disclosure.

[0082] For the sake of brevity, conventional techniques related to the manufacture of conventional semiconductor devices will not be described in detail herein. In addition, the various steps and processes described herein can be incorporated into a more comprehensive process or technique with additional functions not described in detail herein. Specifically, the various processes in semiconductor device manufacture are well known. Therefore, for the sake of brevity, many conventional processes will only be briefly mentioned herein or will be completely omitted without providing well-known process details. Those of ordinary skill in the art will understand, after reading this disclosure in its entirety, that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products. In addition, it should be noted that the semiconductor device structures include different numbers of components, and a single component shown in the drawings can represent multiple components.

[0083] In addition, spatial relative terms, such as "above", "overlying", "on", "upper", "top", "beneath...", "below", "under", "lower", "bottom". For the convenience of description, the present disclosure may use these terms to describe the relationship between one element or feature and another element or feature in the drawings. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatial relative descriptive terms used in the present disclosure may be interpreted accordingly. When spatial relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on the other element, or there may be intervening elements or layers. When an element or layer is referred to as "on" another element or layer, it is directly on the other element or layer and in contact with the other element or layer.

[0084] In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. Such repetition is for the purpose of simplicity and clarity, and such repetition in itself is not intended to limit the relationship between the various embodiments and / or arrangements described.

[0085] It should be noted that references in the specification to "an embodiment", "one embodiment", "exemplary embodiment", "exemplary", "example", etc. indicate that the embodiment may include a particular feature, structure, or characteristic, but each embodiment does not necessarily include the particular feature, structure, or characteristic. Moreover, such terms do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, the influence of combining other embodiments on such feature, structure, or characteristic will be within the knowledge of those of ordinary skill in the art.

[0086] It should be understood that the terms or phrases herein are for the purpose of description and not for limitation, such that the terms or phrases of this specification should be interpreted by those of ordinary skill in the art in accordance with the teachings herein.

[0087] This document discusses various embodiments in a specific context, namely, a semiconductor structure configured to form a device including fin field-effect transistors (FinFETs). The semiconductor structure can be, for example, a complementary metal-oxide-semiconductor (CMOS) device (including P-type metal-oxide-semiconductor (PMOS) FinFET devices and N-type metal-oxide-semiconductor (NMOS) FinFET devices). Embodiments will now be described with respect to a specific example including a FinFET manufacturing process. However, the embodiments are not limited to the examples provided herein, and these concepts can be implemented in a wide range of embodiments. Thus, various embodiments can be applied to other semiconductor devices / processes, such as planar transistors and the like. In addition, some of the embodiments discussed herein are in the context of devices formed using a back-gate process. In other embodiments, a front-gate process can be used.

[0088] Although the drawings illustrate various embodiments of semiconductor devices, additional features can be added to the drawings of the illustrated semiconductor devices, and some of the features described hereinafter can be replaced, modified, or removed in other embodiments of the semiconductor devices.

[0089] Additional steps can be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages can be replaced or removed. Additional features can be added to the semiconductor device structure. For different embodiments, some of the features described hereinafter can be replaced or removed. Although some of the embodiments are illustrated by steps performed in a specific order, these steps can be performed in another logical order.

[0090] Now refer to Figure 1A , which shows a perspective view of a semiconductor device 100, such as a FinFET device. Figure 1B A cross-sectional view taken along the Figure 1A X-X' sectional line according to some embodiments is shown. In one embodiment, the semiconductor device 100 includes a substrate 101 and a first trench 103. The substrate 101 can be a silicon substrate, but can also be other substrates, such as semiconductor-on-insulator (SOI), strained SOI, and silicon germanium on insulator. The substrate 101 can be a p-type semiconductor, although in other embodiments, the substrate 101 can be an n-type semiconductor.

[0091] In other embodiments, the substrate 101 can be selected as a material that will particularly enhance the performance of the device formed by the substrate 101 (e.g., enhance carrier mobility). For example, in some embodiments, the material of the substrate 101 can be selected as an epitaxially grown semiconductor material layer, such as epitaxially grown silicon germanium, and the epitaxially grown silicon germanium helps to improve some dimensional properties of the device formed by the epitaxially grown silicon germanium. However, although the use of these materials may be able to improve some performance characteristics of the device, the use of these same materials may affect other performance characteristics of the device. For example, the use of epitaxially grown silicon germanium (relative to silicon) can reduce the interface defects of the device.

[0092] A first trench 103 can be formed as an initial step in ultimately forming the first isolation region 105. A mask layer ( Figure 1A not shown separately) and a suitable etching process can be used to form the first trench 103. For example, the mask layer can be a hard mask including silicon nitride formed by a process such as chemical vapor deposition (CVD), but can also be other materials, such as oxides, oxynitrides, silicon carbide, combinations thereof, and other materials, etc. Processes such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or a process of forming uniform silicon oxide and then nitriding can be used. Once formed, the mask layer can be patterned by an appropriate lithography process to expose the portion of the substrate 101 that will be removed to form the first trench 103.

[0093] However, those of ordinary skill in the art will recognize that the foregoing processes and materials for configuring the mask layer are not the only ways to configure to protect portions of the substrate 101 and at the same time expose other portions of the substrate 101. For forming the first trench 103. Any suitable process can be utilized, such as a photoresist that is patterned and developed to expose the portion of the substrate 101 that will be removed to form the first trench 103. All such methods are included within the scope of this embodiment.

[0094] Once the mask layer is formed and patterned, the first trench 103 is formed in the substrate 101. Although the first trench 103 can be formed in the substrate 101 by any suitable process, it can also be formed in the substrate 101 by, for example, a reactive ion etching (RIE) process.

[0095] However, those of ordinary skill in the art will recognize that the above process for forming the first trench 103 is only one possible process and does not represent the only embodiment. On the contrary, any suitable process that can form the first trench 103 can be utilized, and any suitable process including any number of masks and removal steps can be used.

[0096] In addition to forming the first trench 103, the masking and etching processes also form fins 107 from the portions of the substrate 101 that are not removed. The fins 107 can be used to form the channel regions of multi-gate FinFET transistors. Although Figure 1A only three fins 107 formed from the substrate 101 are illustrated, any number of fins 107 can be used.

[0097] Furthermore, the fins 107 can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) can be used to pattern the fins 107. Generally, double patterning or multi-patterning processes combine lithography with self-alignment processes, thereby allowing the fabrication of patterns having a pitch, for example, smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins 107.

[0098] Once the first trench 103 and the fins 107 are formed, the first trench 103 can be filled with a dielectric material, and the dielectric material can be recessed within the first trench 103 to form the first isolation region 105. The dielectric material can be an oxide material or a high-density plasma (HDP) oxide, etc. Optionally, after cleaning and lining the first trench 103, a chemical vapor deposition (CVD) method (e.g., HARP process), a high-density plasma CVD method, or other suitable and known formation methods in the art can be used to form the dielectric material.

[0099] The first trench 103 can be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material and then removing the excess material outside the first trench 103 and the fins 107 through a suitable process, such as chemical mechanical polishing (CMP), etching, or a combination thereof. In one embodiment, the removal process also removes any dielectric material located over the fins 107, removing the dielectric material to expose the surface of the fins 107 to further processing steps.

[0100] When the first trench 103 has been filled with a dielectric material, the dielectric material may be recessed away from the surface of the fin 107. The recessing may be performed to expose at least a portion of the sidewall of the fin 107 adjacent to the top surface of the fin 107. The dielectric material may be recessed by placing the top surface of the fin 107 in an etchant such as HF to perform wet etching, but other etchants such as H2 may also be used. Also, other methods may be used, such as reactive ion etching, dry etching using an etchant such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning.

[0101] However, those of ordinary skill in the art will recognize that the foregoing steps may only be a part of the overall process flow configured to fill and recess the dielectric material. For example, a liner step, a cleaning step, an annealing step, a gap filling step, or a combination thereof may also be utilized to form the first trench 103 and fill the first trench 103 with a dielectric material. All potential processing steps are included within the scope of this embodiment.

[0102] After forming the first isolation region 105, a dummy gate dielectric 109 may be formed over each fin 107, a dummy gate electrode 111 may be formed over the dummy gate dielectric 109, and a spacer 113 may be formed over each fin 107. In one embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art and configured to form a gate dielectric. Depending on the gate dielectric formation technique, the thickness of the dummy gate dielectric 109 on top of the fin 107 may be different from the thickness of the gate dielectric on the sidewall of the fin 107.

[0103] The dummy gate dielectric 109 may include a material such as silicon dioxide or silicon oxynitride. The dummy gate dielectric 109 may be formed of a high dielectric constant (high-k) (e.g., relative dielectric constant greater than about 5) material such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium dioxide (HfO2), hafnium oxynitride (HfON), zirconium dioxide (ZrO2), or a combination thereof. Additionally, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used for the dummy gate dielectric 109.

[0104] The dummy gate electrode 111 may include a conductive or non-conductive material and may be selected from, including, polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or a combination thereof, etc. The dummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputter deposition, or other techniques known in the art and configured to deposit a conductive material. The top surface of the dummy gate electrode 111 may have a non-flat top surface and may be planarized before patterning or gate etching of the dummy gate electrode 111. At this time, ions may be introduced into the dummy gate electrode 111 (for example, ions may be introduced by ion implantation techniques), or ions may not be introduced into the dummy gate electrode 111.

[0105] Once formed, the dummy gate dielectric 109 and the dummy gate electrode 111 may be patterned to form a series of dummy stacks 115 over the fins 107. The dummy stacks 115 define a plurality of channel regions on each side of the fins 107 located below the dummy gate dielectric 109. The dummy stacks 115 may be formed by depositing and patterning a gate mask ( Figure 1A not shown separately) on the dummy gate electrode 111 using, for example, deposition and lithography techniques known in the art. The gate mask may incorporate common mask and sacrificial materials, such as (but not limited to) silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride. A dry etching process may be used to etch the dummy gate electrode 111 and the dummy gate dielectric 109 to form a pattern in the dummy stacks 115.

[0106] Once the dummy stacks 115 are patterned, spacers 113 may be formed. The spacers 113 may be formed on opposite sides of the dummy stacks 115. The spacers 113 may be formed by conformally depositing a layer (as shown for clarity, Figure 1A as) or multiple layers (as Figure 1Bformed by an interlayer spacer layer as shown. One or more interlayer spacer layers may include SiN, nitrogen oxides, SiC, SiON, SiOCN, SiOC, or oxides, etc., and may be formed by methods configured to form such layers, such as chemical vapor deposition (CVD), plasma-enhanced CVD, sputtering, and other methods known in the art. In embodiments having more than one interlayer spacer layer, one or more interlayer spacer layers may be formed using similar materials and in a similar manner, but different from each other, for example, by including materials having different component percentages, different curing temperatures, and porosities. In addition, one or more interlayer spacer layers may include different materials having different etching characteristics or the same material as the dielectric material in the first isolation region 105. Then, one or more interlayer spacer layers may be patterned, for example, by one or more etching processes. One or more interlayer spacer layers are removed from the horizontal surface of the structure. In this way, one or more interlayer spacer layers are formed along the sidewalls of the virtual stack 115 and are collectively referred to as the spacer 113.

[0107] Figure 1A Also shown is the removal of the fin 107 from the region not protected by the virtual stack 115 and the spacer 113 (although Figure 1A the position of the fin 107 is still shown in the figure to show the original position where the fin 107 was located), and the source / drain region 117 is regrown. Depending on the context, the source / drain region may refer to the source or the drain individually or collectively. The removal of the fin 107 from the region not protected by the virtual stack 115 and the spacer 113 can be by reactive ion etching (RIE) using the virtual stack 115 and the spacer 113 as a hard mask or by any other suitable removal process. The removal can be continued until the fin 107 is flush with the surface of the first isolation region 105 (as shown in the figure) or the fin 107 is below the surface of the first isolation region 105.

[0108] Once the aforementioned portion of the fin 107 has been removed, a hard mask (not shown separately) is set and patterned to cover the virtual gate electrode 111 to prevent growth, and the source / drain region 117 can be regrown until it contacts each fin 107. In one embodiment, the source / drain region 117 can be regrown, and in some embodiments, the source / drain region 117 can be regrown to form a stress source, and the stress source applies stress to the channel region of each fin 107 located below the virtual stack 115. In embodiments where the fin 107 includes silicon and the FinFET is a p-type device, the source / drain region 117 can be regrown using a selective epitaxial process with a material such as silicon or a material having a different lattice constant from the channel region (such as silicon). The epitaxial growth process can use precursors such as silane, dichlorosilane, and germane, and can last for about 5 minutes to about 120 minutes, for example, about 30 minutes.

[0109] Once the source / drain regions 117 are formed, dopants can be implanted into the source / drain regions 117 by implanting appropriate dopants to replenish the dopants in the fin 107. For example, p-type dopants such as boron, gallium, or indium can be implanted to form PMOS devices. Alternatively, n-type dopants such as phosphorus, arsenic, or antimony can be implanted to form NMOS devices. The dummy stack 115 and the spacers 113 can be used as masks to implant the dopants. It should be noted that those of ordinary skill in the art will recognize that many other processes, steps, etc. can be used to implant the dopants. For example, those of ordinary skill in the art will recognize that various combinations of spacers and liners can be used to perform multiple implants to form source / drain regions having specific shapes or characteristics suitable for a particular purpose. Any of these processes can be used to implant the dopants, and the foregoing is not intended to limit the present embodiment to the foregoing steps.

[0110] Additionally, at this time, the hard mask covering the dummy gate electrode 111 during the formation of the source / drain regions 117 is removed. In one embodiment, a wet or dry etching process selective to the material of the hard mask can be used to remove the hard mask. However, any suitable removal process can also be used.

[0111] Figure 1A Also illustrated is the formation of an interlayer dielectric (ILD) layer 119 over the dummy stack 115 and the source / drain regions 117 (shown in dashed lines in Figure 1A to more clearly show the structure located below the ILD layer 119). The ILD layer 119 can include a material such as boron phosphorous silicate glass (BPSG), but any suitable dielectric can also be used. A process such as PECVD can be used to form the first ILD layer 119, but alternatively other processes such as LPCVD can also be used. Once the ILD layer 119 is formed, a planarization process such as a chemical mechanical polishing process can be used to planarize the ILD layer 119 and the spacers 113, but any suitable process can also be used.

[0112] Figure 2 A process flow diagram of an exemplary process for configuring to form a FET in a semiconductor device according to some embodiments is illustrated. In conjunction with Figure 2 and Figures 3A to 3His a cross-sectional view of a semiconductor device and illustrates a semiconductor device at various manufacturing stages in some embodiments of the present disclosure according to an exemplary process 200. The process 200 is merely an example and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional steps may be provided before, during, and after the exemplary process 200, and additional embodiments of the exemplary process 200 may move, replace, or remove some of the recited steps. Additional features may be added to the semiconductor device illustrated in the figures, and some of the features described hereinafter may be replaced, modified, or removed in other embodiments of the semiconductor device.

[0113] It should be understood that portions of the semiconductor device may be fabricated by typical semiconductor technology processes, and thus only some processes are briefly described herein. In addition, the exemplary semiconductor device may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic elements, etc., but are simplified for a better understanding of the concepts of the present disclosure. In some embodiments, the exemplary device includes a plurality of semiconductor devices (e.g., transistors) that may be interconnected, and the plurality of semiconductor devices that may be interconnected include PFETs, NFETs, etc. In addition, it should be noted that the operations of the process 200, including any descriptions provided with reference to the figures, are merely exemplary and do not limit beyond what is specifically recited in the appended claims.

[0114] Figures 3A to 3G An enlarged view of an exemplary semiconductor structure 300 at various stages of manufacturing a semiconductor device is illustrated according to some embodiments. In some of the figures, for ease of depicting the drawing, some reference numerals of parts or features may be omitted to avoid obscuring other parts or features.

[0115] In step 202, the exemplary process 200 includes removing at least one dummy gate from the substrate. The dummy gate electrode and / or the gate dielectric may be removed by an appropriate etching process. Refer to Figure 3A, in the embodiment of step 202, the exemplary semiconductor structure 300 includes a substrate 302 having an opening 304 formed by removing a dummy gate. In some embodiments, the substrate 302 may be a semiconductor substrate, such as a silicon substrate. The substrate 302 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. As is known in the art, the substrate 302 may include various doping configurations according to design requirements. For example, different doping profiles (e.g., n-well, p-well) may be formed on the substrate 302 to form different device types (e.g., n-type field effect transistor (NFET), p-type field effect transistor (PFET)). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 302 typically has isolation components (e.g., shallow trench isolation (STI) components) inserted in regions providing different device types. The substrate 302 may further include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 302 may include compound semiconductors and / or alloy semiconductors. In addition, the substrate 302 may optionally include an epi-layer (which may be strained to improve performance), may include a silicon-on-insulator (SOI) structure and / or have other suitable enhancement features.

[0116] The semiconductor structure further includes one or more spacer layers 306. In this example, the one or more spacer layers 306 include a first spacer layer 306a (e.g., an etch stop layer) and a second spacer layer 306b. The one or more spacer layers may include SiO2, SiN, SiOC, nitrides, SiC, SiON, SiOCN, and oxides, etc., and may be formed by methods for forming such layers, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputtering, and other methods known in the art.

[0117] The semiconductor structure further includes an interlayer dielectric layer (ILD0 layer 308) located above the source / drain regions 310. The ILD0 layer 308 may include an oxide or a material such as borophosphosilicate glass (BPSG), but any other suitable dielectric may also be used. The ILD0 layer 308 may be formed using a process such as PECVD, but other processes such as LPCVD may alternatively be used.

[0118] In step 204, the exemplary process 200 includes forming a metal gate in an opening formed by removing a dummy gate above the substrate. Refer to Figure 3B , in the embodiment of step 204, the exemplary semiconductor structure includes an opening 304 formed above the substrate 302 (as Figure 3AThe metal gate (MG) 312 as shown in

[0119] In various embodiments, forming the MG involves step 206 of forming an interfacial layer (IL) in the opening 304 above the substrate 302, and forming a high-k material dielectric layer above the IL. The interfacial layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable processes. In some embodiments, the interfacial layer can include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON).

[0120] The high-k dielectric layer can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant, such as greater than the dielectric constant of thermally grown silicon oxide (˜3.9). The high-k material dielectric layer can include, for example, a high-k dielectric layer of hafnium oxide (HfO2). Alternatively, the high-k gate dielectric layer can include other high-k dielectrics such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0121] In various embodiments, forming the MG can also involve step 208 of forming one or more work function metal layers above the high-k gate dielectric layer. The one or more work function metal layers can be formed by CVD, ALD, and / or other suitable processes. In some embodiments, one or more of the work function metal layers can include one or more first work function metal layers and one or more second work function metal layers, the first work function metal layer including a p-type work function metal for adjusting the threshold voltage of a p-type transistor, and the second work function metal layer including an n-type work function metal for adjusting the threshold voltage of an n-type transistor. The first work function metal layer can include a transition metal such as TiN, TaN, WCN, or any suitable material or combination thereof. The second work function metal layer can include a transition metal such as TiAlC, TaAlC, or any suitable material or combination thereof.

[0122] In various embodiments, forming the MG may also involve step 210 of forming a gate electrode layer. The gate electrode layer may include materials such as TiN or any suitable material or a combination thereof. The gate electrode layer may be formed by CVD, ALD, and / or other suitable processes.

[0123] In step 212, exemplary process 200 includes forming a metal capping layer over the MG. The metal capping layer may include a metal such as tungsten (W) or any suitable material or a combination thereof. The metal capping layer may be formed by CVD, ALD, and / or other suitable processes. Refer to Figure 3C , in an embodiment of step 212, an exemplary semiconductor structure includes a metal capping layer 314 deposited over the MG 312.

[0124] In step 214, exemplary process 200 includes forming a dielectric gate capping layer over the metal capping layer. The dielectric gate capping layer may be formed by selectively depositing a dielectric (such as SiN) on the metal capping layer rather than surrounding the ILD0 layer. The dielectric gate capping layer may serve to protect the MG during subsequent metal drain (MD) formation. The dielectric gate capping layer is formed using a self-navigating deposition (SND) process, which is described in more detail below by Figure 5 and Figure 6 . A semiconductor process of forming a dielectric gate capping layer over a metal capping layer using the SND process has a smaller MG height and a smaller dielectric gate capping layer height compared to when a different deposition process is used to form the dielectric gate capping layer on the metal capping layer. The SND process is an area-selective deposition process where deposition occurs in a selected area. Refer to the exemplary Figure 3D , in an embodiment of step 214, an exemplary semiconductor structure includes a dielectric gate capping layer 316 deposited over the metal capping layer 314, which in turn is formed over the MG 312. However, the dielectric gate capping layer 316 is not formed over the ILD0 layer 308.

[0125] At step 216, exemplary process 200 includes forming a second ILD layer (ILD1 layer) over the ILD0 layer and the dielectric gate capping layer. Refer to Figure 3E, in the embodiment of step 216, an exemplary semiconductor structure includes an ILD1 layer 318 formed over the ILD0 layer 308 and the dielectric gate capping layer 316. The ILD1 layer 318 may comprise or be a material such as silicon nitride (SiN), but other suitable materials may also be used, such as silicon oxide (SiO2), aluminum oxide (AlO), silicon oxycarbide (SiOC), silicon carbide (SiC), zirconium nitride (ZrN), zirconium oxide (ZrO), or a combination thereof, etc. The ILD1 layer 318 may be deposited using, for example, plasma enhanced atomic layer deposition (PEALD), thermal atomic layer deposition (thermal ALD), plasma enhanced chemical vapor deposition (PECVD), or other deposition processes. Any suitable deposition process and process conditions may be utilized.

[0126] At step 218, the exemplary process 200 includes forming a patterned mask that exposes a portion of the ILDl layer. In various embodiments, forming the patterned mask involves forming a hard mask (e.g., hard mask 320 as Figure 3E shown) over the ILD1 layer 318, and patterning the hard mask 320 to expose the portion of the ILD1 layer 318 that extends over the S / D region 310, and then forming an MD over the S / D region 310. The patterned mask may include a photoresist layer. The patterned mask may be formed by photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and / or a combination thereof. In some other embodiments, various imaging enhancement layers may be formed under the photoresist layer to enhance pattern transfer. The imaging enhancement layer may include three layers, which include a bottom organic layer, a middle inorganic layer, and a top organic layer. The imaging enhancement layer may further include an anti-reflective coating (ARC) material, a polymer layer, an oxide derived from tetraethylorthosilicate (TEOS), silicon oxide, or a Si-containing anti-reflective coating (ARC) material, such as an ARC layer containing 42% silicon. In still other embodiments, the patterned mask layer includes a hard mask layer. The hard mask layer includes an oxide material, silicon nitride, silicon oxynitride, amorphous carbon material, silicon carbide, or tetraethylorthosilicate (TEOS).

[0127] At step 220, the exemplary process 200 includes selectively removing the exposed portions of the ILDl layer and the ILD0 layer over the S / D region to form an opening that exposes the underlying source / drain regions. Refer to Figure 3F, in the embodiment of step 220, the exemplary semiconductor structure includes an opening 321 in the ILD1 layer 318 and an opening 322 in the ILD0 layer 308. The ILD1 layer 318 and the ILD0 layer 308 are selectively removed to create the openings 321 and 322 to expose the S / D regions 310. The exposed portions of the ILD layer 318 and the ILD layer 308 can be removed by a suitable etching process, such as wet etching, dry etching process, or a combination thereof. The dielectric gate capping layer 316 and the metal capping layer 314 together protect the MG 312 during the etching process to expose the S / D regions 310.

[0128] At step 222, the exemplary process 200 includes selectively forming a silicide contact on the already exposed source / drain regions. The optional silicide contact can include titanium (e.g., titanium silicide (TiSi)) to reduce the Schottky barrier height of the contact. However, other metals such as nickel, cobalt, erbium, platinum, and palladium can also be used. The silicidation can be performed by blanket deposition of a suitable metal layer followed by an annealing step that causes the metal to react with the underlying exposed silicon of the source / drain regions. Refer to Figure 3G , in the embodiment after completing step 222, the semiconductor structure includes a silicide contact 324 optionally formed on the already exposed source / drain regions 310.

[0129] At step 224, the exemplary process 200 includes filling the openings that contact the source / drain regions with a conductive material to form source / drain contacts (also referred to in this disclosure as metal drain (MD) contacts). The source / drain contacts can include one or more layers. For example, in some embodiments, the source / drain contacts include a liner and a metal fill material (not shown separately) deposited by, for example, CVD, ALD, electroless deposition (ELD), PVD, electroplating, or another deposition technique. The liner (such as a diffusion barrier layer or an adhesion layer, etc.) can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, or nickel, etc. A planarization process such as CMP can be performed to remove the excess liner and conductive material. The remaining liner and conductive material form the source / drain contact located in the opening. Refer again to Figure 3G , in the embodiment after completing step 224, the semiconductor structure further includes a conductive material that fills the opening 322 (as Figure 3F shown) and contacts the source / drain regions 310 to form the source / drain contact (MD 326).

[0130] In step 226, exemplary process 200 includes filling the openings above the source / drain regions and the gate region with an ILD1 material to fill the ILD1 layer, and forming one or more intermetal dielectric (IMD) layers over the ILD1 layer. Each IMD layer may include an etch stop layer (ESL) over the underlying layer and an ILD layer over the ESL. The ESL may be deposited using one or more low-temperature deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Referring again to Figure 3G , in an embodiment after step 226 is completed, the semiconductor structure further includes an ILD1 layer 318 and an IMD layer 327, and the IMD layer 327 includes an ESL 328 and an ILD2 layer 330. In this example, the height of MG 312 is not equal to the height of MD 326.

[0131] The ILD2 layer 330 may be formed of a dielectric material (such as an oxide (e.g., silicon oxide (SiO2))), and may be deposited by any acceptable process (such as CVD, PEALD, thermal ALD, or PECVD, etc.). The ILD2 layer 330 may also be formed by depositing a suitable insulating material (such as PSG, BSG, BPSG, USG, etc.) by any suitable method (such as CVD, PECVD, flowable CVD, etc.). After the ILD2 layer 330 is formed, the ILD2 layer 330 may be cured, for example, by an ultraviolet curing process.

[0132] In step 228, exemplary process 200 includes forming one or more contact VIA (vertical interconnection access) openings configured to connect the metal lines in the IMD layer to the MD contacts or the MG contacts. The contact VIA openings configured for the gate VIA (VG) contacts and the source / drain VIA (VD) contacts are formed by using one or more etching processes. According to some embodiments, the openings configured for the VG contacts and the openings configured for the VD contacts penetrate through the second ILD layer, the ESL, and the first ILD layer. The openings may be formed by any combination of acceptable lithography and suitable etching techniques, such as dry etching processes (such as plasma etching, reactive ion etching (RIE), physical etching (such as ion beam etching (IBE))), wet etching, or a combination thereof, etc. However, any suitable etching process may be used to form the contact VIA openings.

[0133] In step 230, exemplary process 200 includes forming VG contacts and VD contacts. The VG contacts are formed over MG and electrically coupled to MG, and the VD contacts are formed over MD contacts and electrically coupled to MD contacts. The VG contacts and / or VD contacts can be formed by depositing a metal material in the openings. The metal material can be deposited by CVD, ALD, electroless deposition (ELD), PVD, electroplating, or other deposition techniques. The VG contacts and / or VD contacts can be or include tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, their alloys, or combinations thereof, etc. Refer to Figure 3H , in an embodiment after completing steps 228 and 230, the semiconductor structure includes VG contact 332 and VD contact 334.

[0134] At step 232, exemplary process 200 includes performing further process operations. The semiconductor device can be further processed to form various components and regions known in the art. For example, various contacts / vias / lines and multi-layer interconnect components (e.g., metal layers and interlayer dielectrics) can be formed on the substrate through subsequent processing, and are configured to connect various components to form a functional circuit that can include one or more multi-gate devices. In this example, the multi-layer interconnect can include vertical interconnects (such as VIAs or contacts, etc.) and horizontal interconnects (such as metal lines, etc.). Various interconnect components can use various conductive materials, including copper, tungsten, and / or silicides. In one example, a damascene and / or dual damascene process is used to form a copper-related multi-layer interconnect structure. In addition, additional process steps can be implemented before, during, and after process 200, and some of the above process steps can be replaced or removed according to various embodiments of process 200.

[0135] Figure 4 The process flow diagram of an exemplary process 400 configured to form an FET in a semiconductor device according to some embodiments is shown. Process 400 includes steps 202 to 220 as described in process 200, and also includes additional steps. The additional steps of process 400 will be described in conjunction with reference to Figures 3I to 3J , Figures 3I to 3J is a cross-sectional view of a semiconductor device, and shows the semiconductor device at various manufacturing stages according to some embodiments of the present disclosure of exemplary process 400. Process 400 is only an example and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional steps can be provided before, during, and after exemplary process 400, and some of the described steps for additional embodiments of exemplary process 400 can be moved, replaced, or removed. Additional features can be added to the semiconductor device shown in the drawings, and some of the features described later can be replaced, modified, or removed in other embodiments of the semiconductor device.

[0136] It should be understood that parts of the semiconductor device can be fabricated by typical semiconductor technology processes, and thus only some processes will be briefly described herein. Additionally, the exemplary semiconductor device may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic elements, etc., but are simplified for better understanding of the concepts of the present disclosure. In some embodiments, the exemplary device includes a plurality of semiconductor devices (e.g., transistors) that can be interconnected, and the plurality of semiconductor devices that can be interconnected include PFETs, NFETs, etc. Additionally, it should be noted that the operations of process 400, including any descriptions provided with reference to the accompanying drawings, are merely exemplary and do not limit the scope beyond what is specifically recited in the appended claims.

[0137] Figures 3I to 3J An enlarged view of an exemplary semiconductor structure at various stages of fabricating a semiconductor device in accordance with some embodiments is illustrated. In some of the figures, for ease of depicting the drawing, some reference numerals of parts or features may be omitted to avoid obscuring other parts or features.

[0138] Process 400 includes steps 202 to 220 as described in the foregoing process 200 and Figure 2 described. Process 400 includes additional steps starting from step 422.

[0139] In step 422, the exemplary process 400 includes selectively forming a silicide contact on the already exposed source / drain regions. The optional silicide contact may include titanium (e.g., titanium silicide (TiSi)) to reduce the Schottky barrier height of the contact. However, other metals such as nickel, cobalt, erbium, platinum, and palladium, etc. may also be used. The silicidation can be performed by blanket deposition of an appropriate metal layer, followed by an annealing step that causes the metal to react with the exposed silicon beneath the source / drain regions. Refer to Figure 3I FIG., in an embodiment after completing step 422, the semiconductor structure includes a silicide contact 324 optionally formed on the already exposed source / drain region 310 (as Figure 3G shown).

[0140] In step 424, exemplary process 400 includes filling the openings in contact with the source / drain regions with a conductive material to form MD contacts. The MD contacts may include one or more layers. For example, in some embodiments, the MD contacts include a liner and a metal fill material (not shown separately) deposited by, for example, CVD, ALD, electroless deposition (ELD), PVD, electroplating, or another deposition technique. The liner (such as a diffusion barrier layer or an adhesion layer, etc.) may include titanium, titanium nitride, tantalum, or tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, or nickel, etc. A planarization process (such as CMP) may be performed to remove the excess liner and conductive material. The remaining liner and conductive material form the source / drain contacts in the openings. Please refer again to Figure 3I , in an embodiment after step 424 is completed, the semiconductor structure further includes a conductive material that fills the opening 322 (as Figure 3F shown) and contacts the source / drain region 310 to form MD 326.

[0141] In step 425, exemplary process 400 includes planarizing the semiconductor structure. Planarization may include performing a chemical mechanical polishing (CMP) step to remove the dielectric gate capping layer 316 and the metal capping layer 314. Planarization may result in MG 312, MD 326, and one or more spacer layers 306 (as Figure 3A shown) having substantially the same height. Please refer again to Figure 3I , in an embodiment after step 425 is completed, the semiconductor structure further includes MG 312, MD 326, and one or more spacer layers 306 (as Figure 3A shown) having substantially the same height.

[0142] In step 426, exemplary process 400 includes filling the openings above the source / drain and gate regions with ILD1 material to fill the ILD1 layer, and forming one or more intermetal dielectric (IMD) layers above the ILD1 layer. Each IMD layer may include an etch stop layer (ESL) located above the lower layer and an ILD layer located above the ESL. The ESL may be deposited using one or more low-temperature deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Please refer again to Figure 3I , in an embodiment after step 426 is completed, the semiconductor structure further includes an ILD1 layer 336 and an IMD layer 338, and the IMD layer 338 includes an ESL 340 and an ILD2 layer 342. In this example, the height of MG 312 is substantially equal to the height of MD 326.

[0143] The ILD2 layer 342 can be formed of a dielectric material (such as an oxide (e.g., silicon oxide (SiO2))), and can be deposited by any acceptable process (such as CVD, PEALD, thermal ALD, PECVD, etc.). The ILD2 layer 342 can also be formed of other suitable insulating materials (such as PSG, BSG, BPSG, USG, etc.) deposited by any appropriate method (such as CVD, PECVD, flowable CVD, etc.). After the ILD2 layer 342 is formed, the ILD2 layer 342 can be cured, for example, by an ultraviolet curing process.

[0144] In step 428, the exemplary process 400 includes forming one or more contact VIA (vertical interconnection access) openings configured to connect the metal lines in the IMD layer to the MD contacts or the MG contacts. The contact VIA openings for the gate VIA (VG) contacts and the source / drain VIA (VD) contacts are formed by using one or more etching processes. According to some embodiments, the openings configured for the VG contacts and the openings configured for the VD contacts are formed through the second ILD layer, the ESL, and the first ILD layer. The openings can be formed by any combination of acceptable lithography and suitable etching techniques, such as dry etching processes (such as plasma etching, reactive ion etching (RIE), physical etching (such as ion beam etching (IBE))), wet etching, or a combination thereof, etc. However, any suitable etching process can be used to form the contact VIA openings.

[0145] In step 430, the exemplary process 400 includes forming the VG contacts and the VD contacts. The VG contacts are formed over the MG and electrically coupled to the MG, and the VD contacts are formed over the MD contacts and electrically coupled to the MD contacts. The VG contacts and / or the VD contacts can be formed by depositing a metal material in the openings. The metal material can be deposited by CVD, ALD, electroless deposition (ELD), PVD, electroplating, or other deposition techniques. The VG contacts and / or the VD contacts can be or include tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, their alloys, or a combination thereof, etc. Refer to Figure 3J , in an embodiment after steps 428 and 430 are completed, the semiconductor structure includes the VG contacts 344 and the VD contacts 346.

[0146] In step 432, exemplary process 200 includes performing further process operations. The semiconductor device can be further processed to form various components and regions known in the art. For example, various contacts / vias / lines and multi-layer interconnect components (e.g., metal layers and interlayer dielectrics) can be formed on the substrate through subsequent processing, and configured to connect various components to form a functional circuit that can include one or more multi-gate devices. In this example, the multi-layer interconnect can include vertical interconnects (e.g., VIAs or contacts, etc.) and horizontal interconnects (e.g., metal lines, etc.). The various interconnect components can use various conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form copper-related multi-layer interconnect structures. Additionally, additional process steps can be implemented before, during, and after process 400, and some of the above process steps can be replaced or removed according to various embodiments of process 400.

[0147] Although the foregoing examples are illustrated with FinFET devices, the foregoing apparatuses, devices, and methods can also be used in combination with other semiconductor transistor technologies related to, for example, gate all around (GAA) and planar transistor technologies.

[0148] Figure 5 An exemplary dielectric gate cover 502 formed above the MG 504 using the SND process is illustrated. Figure 5 A flowchart of an exemplary SND process 600 for forming an exemplary dielectric gate cover 502 is illustrated. Figure 6 The SND process 600 will be referred to Figure 5 and Figures 7A to 7D described, where Figures 7A to 7D are graphical schematic diagrams of the respective process stages of the exemplary SND process 600.

[0149] As Figure 5 shown, an exemplary dielectric gate cover 502 has been formed above the MG 504 and the gate spacer 506, but not above the ILD0 layer 508 in the S / D region. The exemplary dielectric gate cover 502 is formed by the SND process 600, which includes a surface treatment stage 602, a suppression stage 604, an annealing treatment stage 606, and a deposition stage 608. In this example, the surface treatment stage 602 is in an inductively coupled plasma (ICP) chamber. The suppression stage 604, the annealing treatment stage 606, and the deposition stage 608 are all performed in a furnace, and in various embodiments, in the same furnace.

[0150] In the surface treatment stage 602, as Figure 7AAs shown, the surface of the ILD0 layer 508 above the S / D region is processed in an inductively coupled plasma (ICP) chamber 701 to reduce the oxygen (O) content. The surface treatment includes placing a substrate (e.g., substrate 302) in a hydrogen (H)-rich environment at a temperature of about 300°C. The surface treatment causes oxidation of the surface of a metal overlay (e.g., Figure 3C the metal overlay 314) (e.g., Figure 3C the surface 315) and oxygen reduction of the top surface of the ILD0 layer 308 (e.g., Figure 3C the surface 309).

[0151] As Figure 7B shown, the suppression stage 604 involves applying tungsten hexafluoride (WF6) gas and nitrogen (N2) to the substrate 302 in a furnace 702 and continuing for 16 minutes at a temperature of about 300°C. In various embodiments, the suppression stage 604 causes fluorine (F) from WF6 to bond with Si atoms on the surface of the ILD0 layer.

[0152] As Figure 7C shown, the annealing treatment stage 606 includes annealing the substrate 302 in a furnace 702. In various embodiments, annealing the substrate 302 includes applying N2 gas to the substrate 302 in a furnace 702 at 400°C and continuing for 60 minutes. In various embodiments, the annealing treatment stage 606 causes moisture removal.

[0153] The deposition stage 608 involves growing a dielectric overlay above the gate region but not above the S / D region. In various embodiments, as Figure 7D shown, the deposition stage 608 involves depositing SiN using a thermal ALD process in a furnace 702. In various embodiments, the thermal ALD process involves treating the substrate 302 with SiH2Cl2 and NH3 at 400°C. In various embodiments, the thermal ALD process causes SiN to be deposited above the metal overlay or MG in the gate region, and does not grow SiN above the ILD0 layer in the S / D region.

[0154] Figure 8 Illustrates exemplary steps during the SND process. In step 802, before the surface treatment stage, oxygen binds to silicon in the silicon oxide from the ILD0 oxide layer. The surface treatment can cause oxygen reduction on the surface of the ILD0 layer. In step 804, during the suppression stage, WF6 is introduced into the furnace, F atoms from WF6 bond to Si (after oxygen reduction), and WOF4 is output as a byproduct of the exhaust gas from the furnace. In step 806, during the deposition stage, NH3 introduced to grow a dielectric overlay above the gate region does not react with the oxide layer, and thus prevents the dielectric overlay material (e.g., SiN) from depositing or growing on the ILD oxide.

[0155] Figure 9A , Figure 9B , Figure 9C and Figure 9D Figures showing the characteristics of an exemplary dielectric gate overlay formed over an MG using an SND process. Figure 9A Figure showing an exemplary semiconductor structure 900, where an MG 902 (e.g., formed of TiN) is disposed on a substrate 901 and between ILD layers 903, an optional metal overlay 906 is disposed over the MG 902, a dielectric gate overlay 904 is formed over the MG 902 and the optional metal overlay 906, and a plurality of gate spacers 905 are formed between the ILD layer 903 on the substrate and the MG 902. In this example, the dielectric gate overlay 904 has a height 907 of about 5 nanometers (nm) and is formed of SiN using an SND process.

[0156] Figure 9B Figure showing the Si content 912 in the dielectric gate overlay 904. Figure 9C Figure showing the tungsten (W) content 922 in the metal overlay 906 at the interface between the MG 902 and the dielectric gate overlay 904. Figure 9D Figure showing a first concentration 932 of nitrogen (N) in the MG 902 (formed of TiN) and a second concentration 934 of N in the dielectric gate overlay 904 (formed of SiN). In various embodiments, as Figure 9E shown in the exemplary table of, the dielectric gate overlay 904 includes a Si concentration of less than 40%, a nitrogen (N) concentration of less than 45%, and an oxygen (O) concentration of greater than 25%.

[0157] Figure 9ETable 940 represents exemplary concentrations of various elements in a dielectric gate overlay (e.g., dielectric gate overlay layer 904) formed over an MG (e.g., MG 902). Row 942 labels the various elements that can be present in the dielectric gate overlay. Row 944 labels the percentage concentrations of the various elements in an exemplary dielectric gate overlay when the dielectric gate overlay is formed of SiN using the SND process. Row 946 labels the percentage concentrations of the various elements in an exemplary dielectric gate overlay when the SND process is used and a surface pretreatment step is performed prior to the SND process and the dielectric gate overlay is formed of SiN. Row 948 labels the percentage concentrations of the various elements in an exemplary dielectric gate overlay when a deposition process other than the SND process is used and the dielectric gate cap is formed of SiN. Table 940 represents an example where the ratio of N:O:Si is about 1:1:1 (e.g., the concentration of each of N, O, and Si is about 33%) when the SND process is used to form the dielectric gate. However, when a process other than the SND process is used to form the dielectric gate overlay, the ratio of N:O:Si is about 1:0:1. In this example, Table 940 shows that in a SiN dielectric gate overlay formed by a process other than the SND process, the composition of the N element is about 50% and the composition of the Si element is about 50%. In this example, Table 940 shows that in a SiN dielectric gate overlay formed by the SND process, the composition of the N element is about 33%, the composition of the O element is about 33%, and the composition of the Si element is about 33%. As illustrated by Table 940, in the present embodiment, the O2 concentration of the SND plus pretreatment process is lower than that of the SND process without pretreatment. In various embodiments, the dielectric gate overlay (e.g., dielectric gate overlay layer 904) has a thickness of about 5.05 nanometers or less.

[0158] In various embodiments, as shown in Table 940, the dielectric gate overlay layer (e.g., dielectric gate overlay layer 904) includes a Si concentration of less than 40%, a nitrogen (N) concentration of less than 45%, and an oxygen (O) concentration of greater than 25% when the SND process is used to form the dielectric gate overlay, or when the SND process with a surface pretreatment step performed prior to the SND process is used to form the dielectric gate overlay.

[0159] In various embodiments, as shown in Table 940, the dielectric gate overlay layer (e.g., dielectric gate overlay layer 904) includes a Si concentration of less than 35%, a nitrogen (N) concentration of less than 40%, and an oxygen (O) concentration of greater than 25% when the SND process is used to form the dielectric gate overlay, or when the SND process with a surface pretreatment step performed prior to the SND process is used to form the dielectric gate overlay.

[0160] In various embodiments, as shown in Table 940, the dielectric gate cap layer (e.g., dielectric gate cap layer 904) includes a Si concentration less than 35%, a nitrogen (N) concentration less than 35%, and an oxygen (O) concentration greater than 30% when the dielectric gate cap is formed using a SND process.

[0161] In various embodiments, as shown in Table 940, the dielectric gate cap layer (e.g., dielectric gate cap layer 904) includes a Si concentration less than 35%, a nitrogen (N) concentration less than 40%, and an oxygen (O) concentration greater than 25% when a SND process is used to form the dielectric gate cap in which a surface pretreatment step is performed prior to the SND process.

[0162] In various embodiments, as shown in Table 940, when a dielectric gate cover is formed using a SND process, or when a dielectric gate cover is formed using a SND process in which a surface pretreatment step is performed prior to the SND process, the dielectric gate cover (e.g., dielectric gate cover layer 904) includes a Si concentration between 25% and 35% and an N concentration between 25% and 40%.

[0163] In various embodiments, as shown in Table 940, when the dielectric gate cap is formed using a SND process, or when the dielectric gate cap is formed using a SND process in which a surface pretreatment step is performed prior to the SND process, the dielectric gate cap (e.g., dielectric gate cap layer 904) includes an O concentration between 25% and 40%.

[0164] Figure 10A , Figure 10B and Figure 10C A diagram illustrating that a SND process configured to form a dielectric gate cap may be applied to transistors having different gate region to S / D region height ratios. Figure 10A It is shown that the SND process configured to form the dielectric gate cap layer 1002 can be applied to a transistor having the MG 1004 having approximately the same height as the ILD layer 1006 over the S / D regions and the ILD layer 1006 over the gate spacers 1008 . Figure 10B It is shown that a SND process configured to form a dielectric gate cap layer 1012 may be applied to a transistor having a MG 1014 and a gate spacer 1018 that is lower in height than an ILD layer 1016 over the S / D regions. Figure 10C It is shown that a SND process configured to form a dielectric gate cap layer 1022 may be applied to a transistor having a MG 1024 having a height higher than an ILD layer 1026 and a gate spacer 1028 above the S / D regions.

[0165] In each example, the dielectric gate capping layer (1002, 1012, 1022) is formed over the gate region (1004, 1014, 1024), but not over the ILD layer (1006, 1016, 1026) located over the S / D region. Since the dielectric gate capping layer material is grown over the gate region (1004, 1014, 1024), rather than over the ILD layer (1006, 1016, 1026) over the S / D region, there is no need to etch the dielectric gate capping layer material over the ILD layer (1006, 1016, 1026) over the S / D region. Accordingly, the height of the dielectric gate capping layer is not lost due to etching of the excess dielectric gate capping layer material over the ILD layer (1006, 1016, 1026) over the S / D region. Therefore, the height of the dielectric gate capping layer (1002, 1012, 1022) using the SND process can be smaller than that required for processes other than the SND process.

[0166] In various embodiments, as Figure 10A shown, the ILD layer 1006 and the gate spacer 1008 have a first height (H1) 1003, the MG 1004 has a second height (H2) 1005, and the first height 1003 is approximately equal to the second height 1005. Also, the dielectric gate capping layer 1002 is formed over the MG 1004 and the plurality of gate spacers 1008, but not over the ILD layer 1006.

[0167] In various embodiments, as Figure 10B shown, the ILD layer 1016 and the gate spacer 1018 have a first height (H1) 1013, the MG 1014 has a second height (H2) 1015, and the first height 1013 is greater than the second height 1015. Also, the dielectric gate capping layer 1012 is formed over the MG 1014, but not over the ILD layer 1016 or the gate spacer 1018.

[0168] In various embodiments, as Figure 10C shown, the ILD layer 1026 and the gate spacer 1028 have a first height (H1) 1023, the MG 1024 has a second height (H2) 1025, and the first height 1023 is less than the second height 1025. The dielectric gate capping layer 1022 is formed over the MG 1024 and the gate spacer 1028, but not over the ILD layer 1026.

[0169] In some embodiments, the technology described in this disclosure relates to a method of manufacturing a semiconductor device, including: forming a gate structure between interlayer dielectric (ILD) layers on a substrate; forming a metal capping layer over the gate structure; and selectively depositing a dielectric capping layer over the metal capping layer by: performing a suppression step in a furnace to prevent growth of the dielectric capping layer material on the ILD layer; performing an annealing process on the substrate in the furnace; and selectively growing the dielectric capping layer over the metal capping layer in the furnace. In some embodiments, selectively depositing the dielectric capping layer further includes treating the substrate surface in an inductively coupled plasma chamber and treating the substrate in a hydrogen-rich environment at a temperature of about 300 °C. In some embodiments, performing the suppression step includes applying tungsten hexafluoride gas and nitrogen gas to the substrate in the furnace at a temperature of about 300 °C and for about 16 minutes. In some embodiments, performing the suppression step further includes causing fluorine from the tungsten hexafluoride gas to bond with silicon on the surface of the interlayer dielectric layer. In some embodiments, performing the annealing process includes applying nitrogen gas to the substrate in a furnace at 400 °C and for 60 minutes. In some embodiments, selectively growing the dielectric capping layer includes depositing the dielectric capping layer material by performing a thermal atomic layer deposition process in the furnace. In some embodiments, performing the thermal atomic layer deposition process includes applying SiH2Cl2 and NH3 gases to the substrate in a furnace at 400 °C such that silicon nitride is deposited over the metal capping layer and silicon nitride does not grow over the interlayer dielectric layer. In some embodiments, performing the suppression step, performing the annealing process, and selectively growing the dielectric capping layer occur in a common furnace.

[0170] In some embodiments, the technology described in this disclosure relates to a method of manufacturing a semiconductor device, including: forming a gate structure between interlayer dielectric (ILD) layers on a substrate; selectively depositing a dielectric capping layer containing silicon nitride above the gate structure by: treating the substrate surface to reduce the oxygen (O) content in the top surface of the ILD layer; performing an inhibition step in a furnace to prevent SiN from growing on the ILD layer; annealing the substrate in the furnace; and selectively growing SiN on the gate structure in the furnace. In some embodiments, treating the substrate surface further includes oxidizing the surface above the gate structure. In some embodiments, performing the inhibition step includes applying tungsten hexafluoride gas and nitrogen gas to the substrate in the furnace at a temperature of about 300 °C for about 16 minutes. In some embodiments, selectively growing silicon nitride includes depositing the dielectric capping layer by applying SiH2Cl2 and NH3 gases to the substrate in the furnace at 400 °C in a thermal atomic layer deposition process in the furnace, such that silicon nitride is deposited above the gate structure and silicon nitride does not grow above the interlayer dielectric layer. In some embodiments, in some embodiments, the dielectric capping layer has a ratio of silicon to nitrogen to oxygen of about 1:1:1. In some embodiments, the dielectric capping layer has an oxygen content between 28% and 35%.

[0171] In some embodiments, the technology described in this disclosure relates to a semiconductor device, including: a gate structure disposed between interlayer dielectric (ILD) layers on a substrate; a plurality of gate spacers formed between the interlayer dielectric layer and the gate structure on the substrate; and a silicon nitride (SiN) dielectric capping member formed above the gate structure, wherein the SiN dielectric capping member includes a Si concentration of less than 40%, a nitrogen (N) concentration of less than 45%, and an oxygen (O) concentration of greater than 25%. In some embodiments, the interlayer dielectric layer and the gate spacers have a first height, the gate structure has a second height, and the first height is substantially equal to the second height; and the silicon nitride dielectric capping member is formed above the gate structure and the gate spacers and not above the interlayer dielectric layer. In some embodiments, the interlayer dielectric layer and the gate spacers have a first height, the gate structure has a second height, and the first height is greater than the second height; and the silicon nitride dielectric capping member is formed above the gate structure and not above the interlayer dielectric layer or the gate spacers. In some embodiments, the interlayer dielectric layer and the gate spacers have a first height, the gate structure has a second height, and the first height is less than the second height; and the silicon nitride dielectric capping member is formed above the gate structure and the gate spacers and not above the interlayer dielectric layer. In some embodiments, the silicon concentration is between 25% and 35%, and the nitrogen concentration is between 25% and 40%. In some embodiments, the silicon nitride dielectric capping member has a thickness of about 5.05 nanometers or less.

[0172] In some embodiments, the techniques described herein relate to a method of manufacturing a semiconductor device, comprising: forming a gate structure between interlayer dielectric (ILD) layers on a substrate; selectively depositing a dielectric capping layer comprising silicon nitride (SiN) over the gate structure by treating a surface of the substrate to reduce an oxygen (O) content in a top surface of the ILD layer; performing an inhibition step in a furnace to prevent growth of SiN on the ILD layer; annealing the substrate in the furnace; and selectively growing SiN on the gate structure in the furnace.

[0173] In some embodiments, the techniques described herein relate to a method of manufacturing a semiconductor device, comprising: forming a gate structure between interlayer dielectric (ILD) layers on a substrate; forming a metal capping layer over the gate structure; treating a surface of the substrate in an inductively coupled plasma (ICP) chamber, the treatment comprising oxidizing a surface of the metal capping layer and reducing an oxygen (O) content in a top surface of the ILD layer; performing an inhibition step in a furnace to prevent growth of SiN on the ILD layer; annealing the substrate in the furnace; and selectively growing a SiN dielectric capping member on the gate structure in the furnace.

[0174] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that a vast number of variations exist. Further, it should be understood that one or more exemplary embodiments are merely examples and are not intended to limit in any way the scope, applicability, or configuration of the present disclosure. Rather, the foregoing detailed description will provide those of ordinary skill in the art with instruction for implementing the exemplary embodiments of the present disclosure. It should be understood that various changes can be made in the functions and configurations of the devices described in the exemplary embodiments without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method of manufacturing a semiconductor device, characterized in that, Comprising: Forming a gate structure between interlayer dielectric layers on a substrate; Forming a metal capping layer over the gate structure; And Selectively depositing a dielectric capping layer over the metal capping layer by: Performing a suppression step in a furnace to prevent growth of a dielectric capping layer material on the interlayer dielectric layer; Performing an annealing process on the substrate in the furnace; and Selectively growing the dielectric capping layer over the metal capping layer in the furnace.

2. The method according to claim 1, wherein Selectively depositing the dielectric capping layer further includes treating a substrate surface in an inductively coupled plasma chamber and treating the substrate in a hydrogen-rich environment at a temperature of 300 °C.

3. The method according to claim 1, characterized in that Performing the suppression step includes applying a tungsten hexafluoride gas and a nitrogen gas to the substrate in the furnace at a temperature of 300 °C for 16 minutes.

4. The method according to claim 1, characterized in that, Performing the annealing process includes applying nitrogen gas to the substrate in the furnace at 400 °C for 60 minutes.

5. The method according to claim 1, characterized in that Selectively growing the dielectric capping layer includes depositing the dielectric capping layer material by performing a thermal atomic layer deposition process in the furnace.

6. A method of manufacturing a semiconductor device, characterized in that, Comprising: Forming a gate structure between interlayer dielectric layers on a substrate; And Selectively depositing a dielectric capping layer containing silicon nitride over the gate structure by: Treating a substrate surface to reduce an oxygen content in a top surface of the interlayer dielectric layer; Performing a suppression step in a furnace to prevent growth of silicon nitride on the interlayer dielectric layer; Performing an annealing process on the substrate in the furnace; and Selectively growing the silicon nitride over the gate structure in the furnace.

7. The method according to claim 6, wherein Treating the substrate surface further includes oxidizing a surface over the gate structure.

8. The method according to claim 6, wherein Selectively growing the silicon nitride includes depositing the dielectric capping layer by applying SiH2Cl2 and NH3 gases to the substrate in the furnace at 400 °C in a thermal atomic layer deposition process in the furnace, such that the silicon nitride is deposited over the gate structure and silicon nitride does not grow over the interlayer dielectric layer.

9. A semiconductor device, characterized in that, Comprising: A gate structure disposed between interlayer dielectric layers on a substrate; A plurality of gate spacers formed between the interlayer dielectric layer and the gate structure; and A silicon nitride dielectric capping member formed over the gate structure, wherein the silicon nitride dielectric capping member includes a silicon concentration of less than 40%, a nitrogen concentration of less than 45%, and an oxygen concentration of greater than 25%.

10. The semiconductor device according to claim 9, wherein The silicon nitride dielectric capping member has a thickness of 5.05 nanometers or less.

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