Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. The forming method of the semiconductor device comprises the following steps of forming a substrate, wherein a first doping element is arranged in the substrate; injecting a second doping element into the substrate to form a first buried layer region, and taking the substrate at the periphery of the first buried layer region as a non-buried layer region; at least injecting auxiliary elements into the non-buried layer region to form a sacrificial layer exposed on the front surface of the substrate; processing the substrate by adopting a first thermal oxidation process to form a first thermal oxidation layer covering the front surface of the substrate, and activating the second doping element in the first buried layer region; the first thermal oxide layer is removed, the first buried layer area and the non-buried layer area are exposed, and the exposed surface of the first buried layer area is flush with the exposed surface of the non-buried layer area. According to the invention, the height difference between the first buried layer region and the non-buried layer region is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for forming the same. Background Art

[0002] As a semiconductor structure, an N-type buried layer is commonly used in high-voltage devices and plays an electrical isolation role to improve the reliability and stability of semiconductor devices such as high-voltage devices. In the semiconductor manufacturing process, the method for forming an N-type buried layer is usually to implant doping ions with a low diffusion coefficient into a substrate and then activate the doping ions by high-temperature thermal driving to ensure that the N-type buried layer has a high doping density and a low diffusion range. However, during the process of activating the doping ions in the substrate by high temperature, a thermal oxide layer needs to be formed to reduce the escape of doping elements, thereby ensuring the doping density of the formed N-type buried layer. The current mainstream process is to form the thermal oxide layer by wet oxidation. However, during the process of forming the thermal oxide layer by the wet oxidation method, the oxidation rate of silicon in the N-type buried layer where the doping ions have been implanted is greater than the oxidation rate of silicon in the non-N-type first buried layer region (i.e., the peripheral region of the N-type buried layer), resulting in a step height between the N-type first buried layer region and the non-N-type first buried layer region after the thermal oxide layer is formed by the wet oxidation method, that is, the N-type first buried layer region is lower than the non-N-type first buried layer region. In subsequent semiconductor device manufacturing processes, the step height difference always exists, which may cause a residual SIN mask layer on the active region above the N-type first buried layer region. After forming the STI (shallow trench isolation structure), the residual SIN cannot be removed, thereby causing the failure of the semiconductor device.

[0003] Therefore, how to reduce the step height between the first buried layer regions such as the N-type first buried layer region and the non-buried layer regions such as the non-N-type first buried layer region, thereby reducing the probability of semiconductor device failure and realizing the improvement of the performance of semiconductor devices, is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0004] The present invention provides a semiconductor device and a method for forming the same, which are used to reduce the step height between the first buried layer regions such as the N-type first buried layer region and the non-buried layer regions such as the non-N-type first buried layer region, thereby reducing the probability of semiconductor device failure and realizing the improvement of the performance of semiconductor devices.

[0005] According to some embodiments, the present invention provides a method for forming a semiconductor device, including the following steps:

[0006] Forming a substrate, the substrate including a front surface and a back surface that are oppositely distributed in a first direction, and the substrate having a first doping element therein;

[0007] Inject a second doping element into the substrate to form a first buried layer region exposed on the front surface of the substrate. The substrate outside the first buried layer region serves as a non-buried layer region, and the conductivity type of the first doping element is opposite to that of the second doping element;

[0008] Inject at least an auxiliary element into the non-buried layer region to form a sacrificial layer exposed on the front surface of the substrate;

[0009] Treat the substrate using a first thermal oxidation process to form a first thermal oxide layer covering the front surface of the substrate and activate the second doping element in the first buried layer region;

[0010] Remove the first thermal oxide layer to expose the first buried layer region and the non-buried layer region, and the exposed surface of the first buried layer region is flush with the exposed surface of the non-buried layer region.

[0011] In some embodiments, the specific steps of forming the substrate include:

[0012] Provide an initial substrate, where the initial substrate includes a first surface and a second surface distributed oppositely along the first direction;

[0013] Use a second thermal oxidation process to oxidize a part of the initial substrate from the first surface to form a protective layer. The remaining initial substrate below the protective layer serves as the substrate, and the surface of the substrate facing the protective layer serves as the front surface of the substrate, and the second surface serves as the back surface of the substrate.

[0014] In some embodiments, the specific steps of injecting a second doping element into the substrate to form a first buried layer region exposed on the front surface of the substrate include:

[0015] Form a photoresist layer above the protective layer, and the photoresist layer has an opening penetrating the photoresist layer along the first direction;

[0016] Inject the second doping element into the substrate along the opening to form the first buried layer region, and the top surface of the first buried layer region is flush with the front surface of the substrate;

[0017] Remove the photoresist layer and the protective layer to expose the first buried layer region.

[0018] In some embodiments, the first doping element is a P-type element, and the second doping element is an antimony element.

[0019] In some embodiments, the auxiliary element is any one or a combination of two or more of silicon element, germanium element, carbon element, and argon element.

[0020] In some embodiments, the specific steps of forming a sacrificial layer by injecting at least an auxiliary element into the non-buried layer region and exposing the front surface of the substrate include:

[0021] Inject the auxiliary element into a part of the first buried layer region and a part of the non-buried layer region to form the sacrificial layer continuously distributed on the first buried layer region and the non-buried layer region.

[0022] In some embodiments, the specific steps of injecting the auxiliary element into a part of the first buried layer region and a part of the non-buried layer region to form the sacrificial layer continuously distributed on the first buried layer region and the non-buried layer region further include:

[0023] Adjust the injection energy and / or injection dose when injecting the auxiliary element to form an amorphous sacrificial layer with uniform distribution.

[0024] In some embodiments, the auxiliary element is silicon, the injection energy when injecting the auxiliary element is 200 keV, and the injection dose of the auxiliary element is greater than or equal to 1.25×10 14 ions / cm 2 .

[0025] In some embodiments, after removing the first thermal oxide layer to expose the first buried layer region and the non-buried layer region, the following steps are further included:

[0026] Form an epitaxial layer on the front surface of the substrate;

[0027] Form a mask layer on the surface of the epitaxial layer facing away from the substrate;

[0028] Form a plurality of shallow trench isolation structures covering the mask layer and extending into the interior of the epitaxial layer, and the plurality of shallow trench isolation structures divide the epitaxial layer into a plurality of active regions;

[0029] Remove the shallow trench isolation structures above the epitaxial layer and all of the mask layer to expose the surface of the active regions.

[0030] According to some other embodiments, the present invention further provides a semiconductor device formed by using the method for forming a semiconductor device as described above; the semiconductor device includes:

[0031] A substrate, the substrate includes a front surface and a back surface distributed oppositely along a first direction, and a first doping element is provided in the substrate;

[0032] A first buried region is located in the substrate, the first buried region includes a second doped element, the conductivity type of the first doped element is opposite to the conductivity type of the second doped element, and the top surface of the first buried region is flush with the front surface of the substrate.

[0033] In some embodiments, it also includes:

[0034] an epitaxial layer covering the front surface of the substrate, wherein the epitaxial layer has a second buried layer region corresponding to the first buried layer region, and the second buried layer region includes the second doping element;

[0035] A shallow trench isolation structure extends from a surface of the epitaxial layer away from the substrate toward the inside of the epitaxial layer, wherein a plurality of the shallow trench isolation structures separate the epitaxial layer into a plurality of active regions;

[0036] The gate structure is located on the surface of the epitaxial layer away from the substrate, and a plurality of the gate structures are contact-connected with the plurality of active regions in a one-to-one correspondence.

[0037] The semiconductor device and its formation method provided by the present invention, before the first buried layer region is activated by the first thermal oxidation process, at least an auxiliary element is implanted into the non-buried layer region outside the first buried layer region to form a sacrificial layer exposed to the front of the substrate, and in the process of activating the first buried layer region by the first thermal oxidation process, the surfaces of the first buried layer region and the non-buried layer region are both lattice damaged, so that the oxidation rate of the first buried layer region in the first thermal oxidation process is the same as the oxidation rate of the non-buried layer region, avoiding the generation of a height difference between the first buried layer region and the non-buried layer region after removing the first thermal oxidation layer formed by the first thermal oxidation process, so that the exposed surface of the first buried layer region is flush with the exposed surface of the non-buried layer region, providing a flat surface for the implementation of subsequent semiconductor processes, and avoiding the subsequent device failure caused by the residual mask layer. Moreover, the first thermal oxidation layer formed by the first thermal oxidation process can block the escape of the second doping element in the first buried layer region during the subsequent annealing process, ensuring the doping concentration in the first buried layer region, thereby improving the reliability and stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a flow chart of a method for forming a semiconductor device in a specific embodiment of the present invention;

[0039] Figure 2 is a schematic structural diagram of an initial substrate in a specific embodiment of the present invention;

[0040] Figure 3It is a schematic structural diagram after forming a photoresist layer above a substrate in a specific embodiment of the present invention;

[0041] Figure 4 It is a schematic structural diagram after patterning the photoresist layer in a specific embodiment of the present invention;

[0042] Figure 5 It is a schematic structural diagram when injecting a second doping element into the substrate in a specific embodiment of the present invention;

[0043] Figure 6 It is a schematic structural diagram after forming a first buried layer region in a specific embodiment of the present invention;

[0044] Figure 7 It is a schematic structural diagram when injecting an auxiliary element into the substrate in a specific embodiment of the present invention;

[0045] Figure 8 It is a schematic structural diagram after performing a first thermal oxidation process in a specific embodiment of the present invention;

[0046] Figure 9 It is a schematic structural diagram after removing the first thermal oxide layer in a specific embodiment of the present invention;

[0047] Figure 10 It is a schematic structural diagram after forming an epitaxial layer on the substrate in a specific embodiment of the present invention;

[0048] Figure 11 It is a schematic structural diagram after forming a shallow trench isolation structure in a specific embodiment of the present invention;

[0049] Figure 12 It is a schematic structural diagram after removing a mask layer in a specific embodiment of the present invention;

[0050] Figure 13 It is a schematic structural diagram after forming a gate structure in a specific embodiment of the present invention.

[0051] Description of Reference Numerals

[0052] 20 Initial substrate

[0053] 201 First surface

[0054] 202 Second surface

[0055] 30 Substrate

[0056] 301 Front side

[0057] 302 Back side

[0058] 31 Protective layer

[0059] 32 Photoresist layer

[0060] 40 Opening

[0061] 60 First Buried Layer Region

[0062] 70 Sacrificial Layer

[0063] 80 First Thermal Oxide Layer

[0064] 100 Epitaxial Layer

[0065] 101 Second Buried Layer Region

[0066] 110 Mask Layer

[0067] 111 Shallow Trench Isolation Structure

[0068] 112 Active Region

[0069] 130 Gate Structure Detailed Implementation Manner

[0070] The following describes in detail the detailed implementation manner of the semiconductor device and the method for forming the same provided by the present invention with reference to the accompanying drawings.

[0071] This detailed implementation manner provides a method for forming a semiconductor device. Figure 1 It is a flowchart of the method for forming a semiconductor device in the detailed implementation manner of the present invention. As Figure 1 shown, the method for forming the semiconductor device includes the following steps:

[0072] Step S11: Form a substrate, the substrate includes a front surface and a back surface that are oppositely distributed in a first direction, and the substrate has a first doping element therein.

[0073] Step S12: Inject a second doping element into the substrate to form a first buried layer region exposed on the front surface of the substrate, and the substrate outside the first buried layer region serves as a non-buried layer region. The conductivity type of the first doping element is opposite to that of the second doping element.

[0074] Step S13: Inject at least an auxiliary element into the non-buried layer region to form a sacrificial layer exposed on the front surface of the substrate.

[0075] Step S14: Process the substrate by a first thermal oxidation process to form a first thermal oxide layer covering the front surface of the substrate and activate the second doping element in the first buried layer region.

[0076] Step S15: Remove the first thermal oxide layer to expose the first buried layer region and the non-buried layer region, and the exposed surface of the first buried layer region is flush with the exposed surface of the non-buried layer region.

[0077] Figure 2 is a schematic structural view of the initial substrate in a specific embodiment of the present invention, Figure 3 is a schematic structural view after forming a photoresist layer on top of the substrate in a specific embodiment of the present invention, Figure 4 is a schematic structural view after patterning the photoresist layer in a specific embodiment of the present invention, Figure 5 is a schematic structural view when injecting a second doping element into the substrate in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the substrate 30 include:

[0078] providing an initial substrate 20, the initial substrate 20 including a first surface 201 and a second surface 202 that are oppositely distributed along the first direction D1, as Figure 2 shown;

[0079] using a second thermal oxidation process to oxidize a part of the initial substrate 20 from the first surface 201 to form a protective layer 31, the remaining initial substrate 20 below the protective layer 31 serving as the substrate 30, and using the surface of the substrate 30 facing the protective layer 31 as the front surface 301 of the substrate 30, and the second surface 202 as the back surface 302 of the substrate 30, as Figure 3 shown.

[0080] In some embodiments, the specific steps of injecting a second doping element into the substrate 30 to form a first buried layer region 60 exposed on the front surface 301 of the substrate 30 include:

[0081] forming a photoresist layer 32 on top of the protective layer 31, the photoresist layer 32 having an opening 40 that penetrates the photoresist layer 32 along the first direction D1, as Figure 4 shown;

[0082] injecting the second doping element into the substrate 30 along the opening 40 to form the first buried layer region 60, and the top surface of the first buried layer region 60 being flush with the front surface 301 of the substrate 30;

[0083] removing the photoresist layer 32 and the protective layer 31 to expose the first buried layer region 60, as Figure 6 shown.

[0084] For example, providing the initial substrate 20 doped with the first doping element. In one example, the initial substrate 20 is a silicon substrate or a silicon-on-insulator substrate. The initial substrate 20 includes the first surface 201 and the second surface 202 that are oppositely distributed along the first direction D1, as Figure 2As shown. First, use a wet cleaning process to clean the initial substrate 20 to remove impurities such as organic pollutants and particulate matter on the surface of the initial substrate 20. Then, a second thermal oxidation process can be used to oxidize a part of the initial substrate 20 from the first surface 201 of the initial substrate 20 to form the protective layer 31 whose material includes silicon dioxide. The remaining unoxidized initial substrate 20 below the protective layer 31 serves as the substrate 30, as Figure 3 shown. The surface of the substrate 30 facing the protective layer 31 serves as the front surface 301 of the substrate 30, and the second surface 202 of the initial substrate 20 serves as the back surface 302 of the substrate 30. The protective layer 31 covers the front surface 301 of the substrate 30. On the one hand, it can protect the front surface 301 of the substrate 30 to prevent the front surface 301 of the substrate 30 from being contaminated; on the other hand, it can serve as a protective layer when the second doping element is subsequently implanted, thereby better protecting the substrate 30.

[0085] After forming the protective layer 31, the photoresist layer 32 is formed through steps such as spin coating, exposure, and development, as Figure 3 shown. Pattern the photoresist layer 32 to form the opening 40 in the photoresist layer 32 that penetrates the photoresist layer 32 along the first direction D1 and exposes the protective layer 31, as Figure 4 shown. In one example, the photoresist layer 32 may include a plurality of the openings 40 arranged at intervals along at least the second direction D2 to facilitate the subsequent synchronous formation of a plurality of first buried layer regions 60 arranged at intervals, where the second direction D2 is perpendicular to the first direction D1. Then, use a vertical implantation method to implant the second doping element into the interior of the substrate 30 along the first direction D1 from the opening 40, as Figure 5 shown, where Figure 5 the solid arrow direction in represents the implantation direction of the second doping element. After implanting the second doping element, the first buried layer region 60 is formed in the substrate 30, as Figure 6 shown, and the top surface of the first buried layer region 60 (i.e., the surface of the first buried layer region 60 facing away from the back surface 302 of the substrate 30) is flush with the front surface 301 of the substrate 30. Then, through a high-temperature ashing process, most of the photoresist layer 32 is removed, and through a wet etching process, the remaining photoresist layer 32 and the protective layer 31 are removed to expose the front surface 301 of the substrate 30 and the top surface of the first buried layer region 60, see Figure 6 . In one example, the etchant used in the wet etching process includes hydrogen peroxide and sulfuric acid. In another example, the etchant used in the wet etching process includes hydrogen peroxide and ammonia.

[0086] In some embodiments, the first doping element is a P-type element and the second doping element is antimony.

[0087] For example, the substrate 30 is a substrate doped with a P-type element, and the second doping element is an N-type element. Since antimony has a low diffusion coefficient, it can ensure the doping concentration of the first buried layer region 60 after subsequent annealing treatment, and further ensure the electrical isolation performance of the first buried layer region 60.

[0088] In some embodiments, the auxiliary element is any one or a combination of two or more of silicon, germanium, carbon, and argon.

[0089] Specifically, setting the auxiliary element as a Group IVA element or an inert element (i.e., a Group 0 element) can prevent the auxiliary element implanted into the substrate 30 from participating in the gain and loss of electrons and holes of N-type or P-type, that is, by making the auxiliary element electrically neutral to ensure that the performance of the semiconductor device is not affected.

[0090] Figure 7 It is a schematic structural diagram when an auxiliary element is implanted into a substrate in a specific embodiment of the present invention. Figure 8 It is a schematic structural diagram after a first thermal oxidation process is performed in a specific embodiment of the present invention. In some embodiments, the specific steps of at least implanting an auxiliary element into the non-buried layer region to form a sacrificial layer 70 exposed to the front surface 301 of the substrate 30 include:

[0091] Implant the auxiliary element into a part of the first buried layer region 60 and a part of the non-buried layer region to form the sacrificial layer 70 continuously distributed on the first buried layer region 60 and the non-buried layer region.

[0092] Specifically, consider a 40 keV energy Sb ion (i.e., an antimony ion), whose projected range reaches 0.3 μm (300 nm). The average nuclear energy loss in the entire energy range is about The energy required to displace a silicon atom from its lattice position is 15 eV. Since the lattice plane spacing of silicon is about This means that, on average, on each plane, the Sb ion will lose about 3325 eV of energy (i.e., ). Most of the 3325 eV of lost energy is transferred to the first silicon atom collided with, and this atom will continuously generate 221 displaced atoms (i.e., 3325 eV / 15 eV). The total number of displaced atoms is 265200 (i.e., ). Assuming that each atom moves about 2.5 nm, the damaged volume VD ≈ π(2.5 nm) 2 ×(300 nm) = 10-17 cm 3 , the damage density is 265200 / VD ≈ 3×10²² per cm 3 , accounting for approximately 60% of the total atoms within the damaged volume VD (there are approximately 5×10 22 silicon atoms in one cubic centimeter of silicon). It can be seen that the implantation of the heavy ion Sb has almost transformed the material of the first buried layer region 60 into an amorphous state, and within the entire projected range, crystal damage has formed disordered clusters.

[0093] In this specific embodiment, by simultaneously implanting the auxiliary element into the first buried layer region 60 and the non-buried layer region, the formed sacrificial layer 70 simultaneously covers the remaining first buried layer region 60 (the remaining first buried layer region refers to the first buried layer region where the auxiliary element has not been implanted) and the remaining non-buried layer region (the remaining non-buried layer region refers to the non-buried layer region where the auxiliary element has not been implanted), thereby enabling the same lattice damage formed due to the implantation of the auxiliary element to exist above the remaining first buried layer region 60 and the remaining non-buried layer region. Subsequently, during the process of treating the substrate 30 using the first thermal oxidation process, it is further ensured that the oxidation rates above the remaining non-buried layer region and the remaining first buried layer region 60 are the same, thereby further avoiding the generation of a height difference between the first buried layer region 60 and the non-buried layer region after the completion of the first thermal oxidation process.

[0094] In some embodiments, the specific steps of implanting the auxiliary element into a part of the first buried layer region 60 and a part of the non-buried layer region to form the sacrificial layer 70 continuously distributed on the first buried layer region 60 and the non-buried layer region further include:

[0095] Adjust the implantation energy and / or implantation dose when implanting the auxiliary element to form a uniformly distributed amorphous sacrificial layer 70.

[0096] In some embodiments, the auxiliary element is silicon, the implantation energy when implanting the auxiliary element is 200 keV, and the implantation dose of the auxiliary element is greater than or equal to 1.25×10 14 ions per cm 2 .

[0097] For example, in materials science theory, in order to estimate the implantation amount required to transform a crystalline material into an amorphous material, the following criterion can be used: that is, it is considered that this implantation amount should be related to the energy density required to melt this material (10 21 keV / cm 3) are of the same order of magnitude. For 40 keV Si ions, the projected range Rp is 0.3 μm, and the dose S required to form amorphous silicon is S = (Rp(10 21 keV / cm 3 ) / E0) = 7.5×10 14 ions / cm 2 , where E0 is the initial energy of the implanted Si ions. The average projected range Rp is the statistical average of the projected ranges of a large number of incident ions. For 200 keV silicon, the projected range Rp is 0.25 μm, and the required dose is 1.25×10 14 ions / cm 2 . However, in practice, due to the non-uniform distribution of damage along the ion path, a higher dose is required to form an amorphous for Si implantation at room temperature, that is, the implanted dose of 200 keV Si ions needs to be greater than 1.25×10 14 ions / cm 2 .

[0098] After implanting the auxiliary element to form the sacrificial layer 70, the substrate 30 is processed by the first thermal oxidation process to form a first thermal oxide layer 80 covering the front surface of the substrate 30, and the second doping element in the first buried layer region 60 is activated, as Figure 8 shown. In one example, the first thermal oxidation process may be a wet oxygen oxidation process. During the first thermal oxidation process, since the sacrificial layer 70 with lattice damage is formed above both the first buried layer region 60 and the non-buried layer region, the amorphous sacrificial layer 70 needs to be consumed first during the first thermal oxidation process, so as to avoid generating a height difference between the first buried layer region 60 and the non-buried layer region after forming the first thermal oxide layer 80.

[0099] Figure 9 is a schematic structural diagram after removing the first thermal oxide layer in the specific embodiment of the present invention, Figure 10 is a schematic structural diagram after forming an epitaxial layer on the substrate in the specific embodiment of the present invention, Figure 11 is a schematic structural diagram after forming a shallow trench isolation structure in the specific embodiment of the present invention, Figure 12 is a schematic structural diagram after removing the mask layer in the specific embodiment of the present invention, Figure 13 is a schematic structural diagram after forming a gate structure in the specific embodiment of the present invention. In some embodiments, after removing the first thermal oxide layer 80 to expose the first buried layer region 60 and the non-buried layer region, the following steps are further included:

[0100] Form an epitaxial layer 100 on the front surface 301 of the substrate 30, as Figure 10 shown;

[0101] Form a mask layer 110 on the surface of the epitaxial layer 100 facing away from the substrate 30;

[0102] Form a plurality of shallow trench isolation structures 111 covering the mask layer 110 and extending into the interior of the epitaxial layer 100. The plurality of shallow trench isolation structures 111 divide the epitaxial layer 100 into a plurality of active regions 112, as Figure 11 shown;

[0103] Remove the shallow trench isolation structures 111 above the epitaxial layer 100 and all of the mask layer 110 to expose the surface of the active regions 112, as Figure 12 shown.

[0104] For example, after removing the first thermal oxide layer 80 by a wet etching process, the top surface of the first buried layer region 60 is flush with the front surface 301 of the substrate 30, as Figure 9 shown. Thereafter, form the epitaxial layer 100 on the front surface 301 of the substrate 30, as Figure 10 shown. In one example, an ion implantation process may be used to form a second buried layer region 101 corresponding to the first buried layer region 60 in the epitaxial layer 100, and the second buried layer region 101 also includes the second doping element. In another example, after forming the epitaxial layer 100, a high-temperature drive-in process is performed on the first buried layer region 60, so that the second doping element in the first buried layer region 60 further diffuses into the epitaxial layer 100 to form the second buried layer region 101.

[0105] Next, deposit a silicon nitride mask material on the epitaxial layer 100 to form the mask layer 110. Pattern the mask layer 110 to form a plurality of etching windows penetrating the mask layer 110 along the first direction D1, and the plurality of etching windows are arranged at intervals along the second direction D2. Etch the epitaxial layer 100 downward along the plurality of etching windows to form a plurality of isolation trenches. Deposit an insulating dielectric layer material such as silicon dioxide on the epitaxial layer 100 to form the shallow trench isolation structures 111 filling the isolation trenches, as Figure 11 shown. Next, use a chemical mechanical polishing process to remove the insulating dielectric layer material covering the surface of the mask layer 110. Since the front surface 301 of the substrate 30 is flush with the first buried layer region 60, after removing the insulating dielectric layer material covering the surface of the mask layer 110, the mask layer 110 can be completely exposed. Subsequently, all of the mask layer 110 can be removed by a wet etching process, as Figure 12As shown, the problem of device failure caused by the residue of the mask layer is avoided. Then, a gate structure 130 is formed on the surface of the exposed active region 112, as Figure 13 shown.

[0106] This specific embodiment also provides a semiconductor device, which is formed by using the method for forming a semiconductor device as described above. Refer to Figures 1 - 13 . The schematic structural diagram of the semiconductor device formed in this specific embodiment can be referred to Figure 13 . As Figures 1 - 13 shown, the semiconductor device includes:

[0107] A substrate 30, the substrate 30 includes a front surface 301 and a back surface 302 that are oppositely distributed along a first direction D1, and a first doping element is provided in the substrate 30;

[0108] A first buried layer region 60, which is located in the substrate 30, the first buried layer region 60 includes a second doping element, the conductivity type of the first doping element is opposite to that of the second doping element, and the top surface of the first buried layer region 60 is flush with the front surface 301 of the substrate 30.

[0109] In some embodiments, the semiconductor device further includes:

[0110] An epitaxial layer 100, which covers the front surface 301 of the substrate 30, and a second buried layer region 101 corresponding to the first buried layer region 60 is provided in the epitaxial layer 100, and the second buried layer region 101 includes the second doping element;

[0111] A shallow trench isolation structure 111, which extends from the surface of the epitaxial layer 100 away from the substrate 30 into the epitaxial layer 100, and a plurality of the shallow trench isolation structures 111 divide the epitaxial layer 100 into a plurality of active regions 112;

[0112] A gate structure 130, which is located on the surface of the epitaxial layer 100 away from the substrate 30, and a plurality of the gate structures 130 are in one-to-one contact connection with a plurality of the active regions 112.

[0113] The semiconductor device and the method for forming the same provided by the specific embodiment inject at least an auxiliary element into a non-buried layer region outside the first buried layer region to form a sacrificial layer exposed on the front surface of the substrate before activating the first buried layer region by using a first thermal oxidation process. During the process of activating the first buried layer region by using the first thermal oxidation process, lattice damage exists on the surfaces of both the first buried layer region and the non-buried layer region, so that the oxidation rate of the first buried layer region is the same as that of the non-buried layer region in the first thermal oxidation process, avoiding the generation of a height difference between the first buried layer region and the non-buried layer region after removing the first thermal oxidation layer formed by the first thermal oxidation process, making the exposed surface of the first buried layer region flush with the exposed surface of the non-buried layer region, providing a flat surface for the implementation of subsequent semiconductor processes, and avoiding the device failure problem caused by the residual mask layer in the subsequent process. Moreover, the first thermal oxidation layer formed by the first thermal oxidation process can block the escape of the second doping element in the first buried layer region during the subsequent annealing process, ensuring the doping concentration in the first buried layer region, thereby improving the reliability and stability of the semiconductor device.

[0114] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes the following steps: Form a substrate, the substrate includes a front surface and a back surface that are oppositely distributed along a first direction, and a first doping element is provided in the substrate; Inject a second doping element into the substrate to form a first buried layer region exposed on the front surface of the substrate, the substrate outside the first buried layer region is used as a non-buried layer region, and the conductivity type of the first doping element is opposite to that of the second doping element; Inject at least an auxiliary element into the non-buried layer region to form a sacrificial layer exposed on the front surface of the substrate; Treat the substrate with a first thermal oxidation process to form a first thermal oxidation layer covering the front surface of the substrate, and activate the second doping element in the first buried layer region; Remove the first thermal oxidation layer to expose the first buried layer region and the non-buried layer region, and the exposed surface of the first buried layer region is flush with the exposed surface of the non-buried layer region.

2. The method for forming a semiconductor device according to claim 1, wherein The specific steps for forming the substrate include: Provide an initial substrate, the initial substrate includes a first surface and a second surface that are oppositely distributed along the first direction; Use a second thermal oxidation process to oxidize a part of the initial substrate from the first surface to form a protective layer, the remaining initial substrate below the protective layer is used as the substrate, and the surface of the substrate facing the protective layer is used as the front surface of the substrate, and the second surface is used as the back surface of the substrate.

3. The method for forming a semiconductor device according to claim 2, wherein, The specific steps for injecting a second doping element into the substrate to form a first buried layer region exposed on the front surface of the substrate include: Form a photoresist layer on the protective layer, and an opening penetrating the photoresist layer along the first direction is formed in the photoresist layer; Inject the second doping element into the substrate along the opening to form the first buried layer region, and the top surface of the first buried layer region is flush with the front surface of the substrate; Remove the photoresist layer and the protective layer to expose the first buried layer region.

4. The method for forming a semiconductor device according to claim 1, wherein The first doping element is a P-type element, and the second doping element is antimony.

5. The method for forming a semiconductor device according to claim 1, wherein The auxiliary element is any one or a combination of two or more of silicon, germanium, carbon, and argon.

6. The method for forming a semiconductor device according to claim 1, wherein, The specific steps for injecting at least an auxiliary element into the non-buried layer region to form a sacrificial layer exposed on the front surface of the substrate include: Inject the auxiliary element into a part of the first buried layer region and a part of the non-buried layer region to form the sacrificial layer continuously distributed on the first buried layer region and the non-buried layer region.

7. The method for forming a semiconductor device according to claim 6, wherein, The specific steps for injecting the auxiliary element into a part of the first buried layer region and a part of the non-buried layer region to form the sacrificial layer continuously distributed on the first buried layer region and the non-buried layer region further include: Adjust the injection energy and / or injection dose when injecting the auxiliary element to form a uniformly distributed amorphous sacrificial layer.

8. The method for forming a semiconductor device according to claim 7, wherein, The auxiliary element is silicon, the implantation energy when implanting the auxiliary element is 200 keV, and the implantation dose of the auxiliary element is greater than or equal to 1.25×10 14 ions / cm 2 .

9. The method for forming a semiconductor device according to claim 1, wherein, After removing the first thermal oxidation layer to expose the first buried layer region and the non-buried layer region, the following steps are further included: Form an epitaxial layer on the front surface of the substrate; Form a mask layer on the surface of the epitaxial layer facing away from the substrate; Forming a plurality of shallow trench isolation structures that cover the mask layer and extend into the interior of the epitaxial layer, and the plurality of shallow trench isolation structures divide the epitaxial layer into a plurality of active regions; Removing the shallow trench isolation structures above the epitaxial layer and all of the mask layer to expose the surface of the active regions.

10. A semiconductor device, characterized in that, Formed by using the method for forming a semiconductor device as claimed in claim 1; the semiconductor device includes: A substrate, the substrate includes a front surface and a back surface that are oppositely distributed in a first direction, and the substrate has a first doping element therein; A first buried layer region, located within the substrate, the first buried layer region includes a second doping element, the conductivity type of the first doping element is opposite to the conductivity type of the second doping element, and the top surface of the first buried layer region is flush with the front surface of the substrate.

11. The semiconductor device according to claim 10, wherein, Further includes: An epitaxial layer, covering the front surface of the substrate, the epitaxial layer has a second buried layer region corresponding to the first buried layer region, and the second buried layer region includes the second doping element; Shallow trench isolation structures, extending from the surface of the epitaxial layer facing away from the substrate into the interior of the epitaxial layer, and the plurality of shallow trench isolation structures divide the epitaxial layer into a plurality of active regions; Gate structures, located on the surface of the epitaxial layer facing away from the substrate, and the plurality of gate structures are in one-to-one contact connection with the plurality of active regions.

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