Semiconductor device and manufacturing method thereof
Through isotropic wet etching and side wall self-alignment dry etching technology, the P-type ion implantation angle is controlled, and the symmetry and consistency of transistors in LDMOS devices are achieved, improving the reliability of the device.
Patent Information
- Application Number
- CN202510396993.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-04
AI Technical Summary
In the BCD process, the gate coverage area and drift area of the first transistor and the second transistor of the switching type LDMOS device are asymmetric, resulting in device reliability problems and poor consistency.
The hard mask layer is etched by isotropic wet method to form an intermediate hard mask layer, and the gate material layer is etched by self-aligning side walls to control the P-type ion implantation angle, so that the body region and drift region covered by the first gate and the second gate are equal in width, ensuring the transistor size symmetry.
Improve the reliability and consistency of switching LDMOS devices, and solve the reliability problem caused by gate coverage asymmetry.
Smart Images
Figure CN120264794A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof. Background Art
[0002] The process of simultaneously fabricating bipolar transistors, CMOS devices, and DMOS devices on the same chip is the BCD process. And the switching LDMOS device is a commonly used device in the BCD process. The LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor, due to its advantages of high voltage resistance, large current driving ability, extremely low power consumption, and compatibility with CMOS integration, is currently widely used.
[0003] As Figure 1 shown, in a switching LDMOS device, an ideal state is to form a left-right symmetric first transistor and a second transistor on the substrate 001, and the first transistor and the second transistor share the body region 001b. First, the body region 001b is formed by well implantation. A polysilicon layer and a photoresist layer R are formed on the substrate. Using the photoresist layer R as a mask, the polysilicon layer is etched to define the channel, forming the gate one 010 in the first transistor and the gate two 020 in the second transistor. The alignment deviation of the process will cause the width La of the gate one 010 covering the body region 001b and the width Lb of the gate two 020 covering the body region 001b to be asymmetric; when the channel is made short, the asymmetry between La and Lb will cause reliability problems; in addition, the polysilicon layer etching is manufactured by photolithography, and it is also impossible to make the width Lc of the gate one 010 covering the drift region one 001a equal to the width Ld of the gate two 020 covering the drift region two 001c symmetrically. The left and right dimensions of the first transistor and the second transistor are asymmetric, with poor consistency, causing reliability problems in the switching LDMOS device. Summary of the Invention
[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof. By using isotropic wet etching of the hard mask layer, the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width to form an intermediate hard mask layer; the gate material layer covers the intermediate hard mask layer; the gate material layer is etched by sidewall self-alignment dry etching to form a first gate and a second gate with equal widths on both sides of the intermediate hard mask layer; by controlling the P-type ion implantation angle for forming the P-type body region, the width of the first gate covering the P-type body region is made equal to the width of the second gate covering the P-type body region; finally, the left and right dimensions of the transistors on both sides are symmetric, with good consistency, improving the reliability of the switching LDMOS device.
[0005] The present invention provides a manufacturing method of a semiconductor device, including:
[0006] Step S1: Provide a substrate, form a first oxide layer and a hard mask layer on the surface of the substrate, and etch the hard mask layer, the first oxide layer and a part of the thickness of the substrate in sequence to form a plurality of first trenches;
[0007] Step S2: Isotropically wet-etch the hard mask layer, and etch the side walls on both sides of the hard mask layer between two adjacent first trenches by the same width; Fill an isolation layer in the first trenches to form shallow trench isolation;
[0008] Step S3: Etch and remove the hard mask layer on the side of each of the two adjacent shallow trench isolations away from the middle region; Wet-etch and remove the part of the shallow trench isolation that protrudes above the substrate;
[0009] Step S4: Form a gate oxide layer, the gate oxide layer covering the remaining shallow trench isolation and the substrate; Form a gate material layer, the gate material layer covering the remaining middle hard mask layer and the gate oxide layer; Use self-aligned dry etching to etch the gate material layer to form a first gate and a second gate with equal widths on both sides of the middle hard mask layer; Remove the middle hard mask layer;
[0010] Step S5: Perform P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region; A first drift region and a second drift region are respectively formed in the substrate on both sides of the P-type body region; By controlling the ion implantation angle, make the width of the P-type body region covered by the first gate equal to the width of the P-type body region covered by the second gate.
[0011] Further, step S1 further includes: Form an N-type deep well in the substrate by N-type ion implantation and thermal promotion, and the N-type deep well is used to form the subsequent first drift region and second drift region;
[0012] Form the first oxide layer and the hard mask layer on the surface of the substrate after forming the N-type deep well.
[0013] Further, in step S2, the hard mask layer includes a silicon nitride layer; Use a hot phosphoric acid solution to isotropically wet-etch the hard mask layer.
[0014] Further, step S3 specifically includes:
[0015] S31: Form a second oxide layer, the second oxide layer covering the middle hard mask layer between two adjacent shallow trench isolations and exposing the hard mask layer on the side of each of the two adjacent shallow trench isolations away from the middle region;
[0016] S32. Using the second oxide layer as a mask, wet-etch to remove the hard mask layer on one side of each of the adjacent two shallow trench isolations away from the middle region.
[0017] S33. Wet-etch to remove the second oxide layer, the part of the shallow trench isolation that protrudes above the substrate, and the part of the first oxide layer that is not covered by the middle hard mask layer.
[0018] Further, in step S33, a wet-etching solution with a high selectivity ratio for silicon oxide and the hard mask layer is selected, and a preset final etching state is achieved by controlling the etching time and etching rate.
[0019] Further, in step S5, inclined ion implantation is used to make the width of the P-type body region greater than the opening width between the first gate and the second gate; the angle of the ion implantation for forming the part of the P-type body region covered by the first gate tilts to the left, and the angle of the ion implantation for forming the part of the P-type body region covered by the second gate tilts to the right.
[0020] Further, after step S5, it further includes:
[0021] Form sidewalls on both sides of the first gate and the second gate respectively.
[0022] Further, after forming the sidewalls, it further includes:
[0023] Selectively perform source-drain ion implantation to form an N-type heavily doped region and a P-type heavily doped region. The N-type heavily doped region includes a source region and a drain region; the source region is located in the upper region of the P-type body region; the drain region is located in the drift region on the side of the shallow trench isolation away from the P-type body region.
[0024] The present invention also provides a semiconductor device, including:
[0025] A substrate, the substrate includes a P-type body region and a first drift region and a second drift region located on both sides of the P-type body region;
[0026] A gate oxide layer is formed on the surface of the substrate, and spaced first and second gates are formed on the surface of the gate oxide layer;
[0027] The width of the P-type body region covered by the first gate is equal to the width of the P-type body region covered by the second gate, and the width of the first drift region covered by the first gate is equal to the width of the second drift region covered by the second gate.
[0028] Further, sidewalls are formed on both sides of each of the first gate and the second gate; an N-type heavily doped region is formed in the substrate, and the N-type heavily doped region includes a source region and a drain region; the source region is located in the upper region of the P-type body region; the drain region is located in the drift region on the side of the shallow trench isolation away from the P-type body region.
[0029] Compared with the prior art, the present invention has the following beneficial effects:
[0030] The present invention provides a semiconductor device and a manufacturing method thereof, including:
[0031] Step S1: Provide a substrate, form a first oxide layer and a hard mask layer on the surface of the substrate, sequentially etch the hard mask layer, the first oxide layer and a part of the thickness of the substrate to form a plurality of first trenches; Step S2: Isotropically wet-etch the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width; Fill an isolation layer in the first trenches to form a shallow trench isolation; Step S3: Etch and remove the hard mask layer on the side of each of the two adjacent shallow trench isolations away from the middle region; Wet-etch and remove the part of the shallow trench isolation that protrudes above the substrate; Step S4: Form a gate oxide layer, and the gate oxide layer covers the remaining shallow trench isolation and the substrate; Form a gate material layer, and the gate material layer covers the remaining middle hard mask layer and the gate oxide layer; Use self-aligned dry etching of the gate material layer to form a first gate and a second gate with equal widths on both sides of the middle hard mask layer; Remove the middle hard mask layer; Step S5: Perform P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region; A first drift region and a second drift region are respectively formed in the substrate on both sides of the P-type body region; By controlling the ion implantation angle, the width of the P-type body region covered by the first gate is equal to the width of the P-type body region covered by the second gate.
[0032] The present invention uses isotropic wet etching of the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width to form a middle hard mask layer. The gate material layer covers the middle hard mask layer and the gate oxide layer; Use sidewall self-aligned dry etching of the gate material layer to form a first gate and a second gate with equal widths on both sides of the middle hard mask layer; By controlling the P-type ion implantation angle for forming the P-type body region, the width of the P-type body region covered by the first gate is equal to the width of the P-type body region covered by the second gate; So that the width of the first drift region covered by the first gate is equal to the width of the second drift region covered by the second gate; Finally, the left and right dimensions of the transistors on both sides are symmetric, with good consistency, improving the reliability of the switching LDMOS device. Description of the Drawings
[0033] Figure 1 It is a schematic diagram of a semiconductor device.
[0034] Figure 2Schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0035] Figures 3 to 13 Schematic diagrams of the steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0036] Among them, the reference numerals are as follows:
[0037] 001 - Substrate; 001a - First drift region; 001b - Body region; 001c - Second drift region; 010 - First gate; 020 - Second gate; R - Photoresist layer;
[0038] 10 - Substrate; 10a - First drift region; 10b - P - type body region; 10c - Second drift region; 20 - First oxide layer; 30 - Hard mask layer; 40 - Shallow trench isolation; 50 - Second oxide layer; 60 - Photoresist layer; 11 - Gate oxide layer; 12 - Gate material layer; 120 - First gate; 220 - Second gate; 13 - Sidewall; D - Drain region; S - Source region. Detailed implementation manners
[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non - precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.
[0040] For the convenience of description, some embodiments of the present application may use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the respective drawings of the embodiments. It should be understood that in addition to the orientations described in the drawings, spatial relative terms are also intended to include different orientations during the use or operation of the device. For example, if the device in the drawing is flipped, the element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "on" other elements or components. The terms "first", "second", etc. in the following text are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that these terms can be replaced under appropriate circumstances.
[0041] An embodiment of the present invention provides a method for manufacturing a semiconductor device, as Figure 2 shown, including:
[0042] Step S1: Provide a substrate, form a first oxide layer and a hard mask layer on the surface of the substrate, and etch the hard mask layer, the first oxide layer, and a part of the thickness of the substrate in sequence to form a plurality of first trenches;
[0043] Step S2: Isotropically wet-etch the hard mask layer such that the sidewalls on both sides of the hard mask layer between two adjacent first trenches are etched by the same width; fill the isolation layer in the first trenches to form shallow trench isolation.
[0044] Step S3: Etch and remove the hard mask layer on the side of each of the two adjacent shallow trench isolations away from the middle region; wet-etch and remove the part of the shallow trench isolation that protrudes above the substrate.
[0045] Step S4: Form a gate oxide layer that covers the remaining shallow trench isolation and the substrate; form a gate material layer that covers the remaining middle hard mask layer and the gate oxide layer; use self-aligned dry etching on the gate material layer to form a first gate and a second gate with equal widths on both sides of the middle hard mask layer; remove the middle hard mask layer.
[0046] Step S5: Perform P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region; form a first drift region and a second drift region in the substrate on both sides of the P-type body region; by controlling the ion implantation angle, make the width of the P-type body region covered by the first gate equal to the width of the P-type body region covered by the second gate.
[0047] The following details each step of the manufacturing method of the semiconductor device according to the embodiments of the present invention with reference to the accompanying drawings.
[0048] As Figure 3 shown, provide a substrate 10, where the substrate includes a single-layer silicon substrate or a SOI substrate, and the SOI substrate includes a bottom silicon layer, an N-type buried layer, and a top silicon layer (such as an epitaxial layer) from bottom to top. Form an N-type deep well in the substrate 10 through N-type ion implantation and thermal drive, and the N-type deep well is used as the subsequent drift region. The N-type deep well is located in the substrate 10 and extends downward from the upper surface of the substrate 10 to a certain depth.
[0049] The substrate 10 can be any suitable substrate material known in the art. For example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or can also be a double-side polished silicon wafer. Exemplarily, in this embodiment, the substrate is, for example, a silicon wafer.
[0050] A first oxide layer 20 and a hard mask layer 30 are formed on the surface of the substrate 10. Using active region lithography, the shallow trench isolation (STI) regions are opened, and the hard mask layer 30, the first oxide layer 20, and a portion of the substrate 10 with a certain thickness are etched in sequence to form a plurality of first trenches. Exemplarily, in a cross-section perpendicular to the substrate 10, the first trenches are rectangular or trapezoidal in reverse.
[0051] As Figure 4 shown, the hard mask layer 30 is etched by isotropic wet etching, and the Figure 3 formed semiconductor structure is placed in a hot phosphoric acid solution. After wet etching for a preset time, due to isotropic etching, the sidewalls of the hard mask layer 30 exposed in each first trench are laterally etched by the same width under the same time and the same solution conditions; correspondingly, the two sidewalls of the intermediate hard mask layer 30 between two adjacent first trenches are etched by the same width, the etching width on the left side is m, and the etching width on the right side is n, and m = n. After wet etching the hard mask layer 30, the part of the first trench located in the hard mask layer 30 is widened, and the first trench after wet etching the hard mask layer 30 is in a T shape. As Figure 5 shown, an isolation layer is filled in the first trench after wet etching the hard mask layer 30 to form the shallow trench isolation (STI) 40.
[0052] As Figure 6 shown, a second oxide layer 50 is formed, and the second oxide layer covers the hard mask layer 30 and the shallow trench isolation 40. A photoresist layer 60 is formed on the surface of the second oxide layer. The photoresist layer 60 covers the intermediate hard mask layer 30 region between two adjacent shallow trench isolations 40 and does not cover the hard mask layer 30 regions on the sides of the two adjacent shallow trench isolations 40 away from the intermediate region. As Figure 7 shown, using the photoresist layer 60 as a mask, the two ends of the second oxide layer 50 exposed by removing the photoresist layer 60 are etched away. As Figure 8 shown, using the patterned second oxide layer 50 after etching as a mask, the hard mask layer 30 on the sides of the two adjacent shallow trench isolations 40 away from the intermediate region is etched away. Specifically, the exposed hard mask layer 30 at both ends can be removed by wet etching with a hot phosphoric acid solution. As Figure 9 shown, the second oxide layer 50, the part of the shallow trench isolation 40 protruding above the substrate 10, and the part of the first oxide layer 20 not covered by the intermediate hard mask layer 30 are removed by wet etching; a wet etching solution with a high selectivity to silicon oxide and the hard mask layer 30 is selected, and the preset final etching state is achieved by controlling the etching time and the etching speed.
[0053] As Figure 10 shown, a gate oxide layer 11 is formed, and the gate oxide layer 11 covers the remaining shallow trench isolation 40 and the part of the substrate exposed by the intermediate hard mask layer 302. A gate material layer 12 is formed, and the gate material layer 12 covers the intermediate hard mask layer 302 and the gate oxide layer 11. As Figure 11As shown, etch the gate material layer 12. Use sidewall self-aligned dry etching to etch the gate material layer 12 to form a first gate 120 and a second gate 220 with equal widths on both sides of the middle hard mask layer 30. As Figure 12 shown, remove the middle hard mask layer 30.
[0054] As Figure 13 shown, a chemical mechanical polishing process can be used to planarize the upper surfaces of the formed first gate 120 and second gate 220. Perform P-type ion implantation into the substrate from the opening between the first gate 120 and the second gate 220 to form a P-type body region. By tilting the ion implantation, the width of the P-type body region is made larger than the width of the opening between the first gate 120 and the second gate 220. By controlling the ion implantation tilt angle and implantation concentration, the width La of the P-type body region 10b covered by the first gate 120 is made equal to the width Lb of the P-type body region 10b covered by the second gate 220. The N-type deep wells on both sides of the P-type body region in the substrate 10 are the first drift region 10a and the second drift region 10c respectively. The width (La + Lc) of the first gate 120 is equal to the width (Lb + Ld) of the second gate 220, and the width La of the P-type body region 10b covered by the first gate 120 is equal to the width Lb of the P-type body region 10b covered by the second gate 220, so that the width Lc of the first drift region 10a covered by the first gate 120 is equal to the width Ld of the second drift region 10c covered by the second gate 220.
[0055] Next, sidewalls 13 are formed on both sides of the first gate 120 and the second gate 220 respectively. Selectively perform source-drain ion implantation to form an N-type heavily doped region N+ and a P-type heavily doped region P+. The N-type heavily doped region N+ includes a source region S and a drain region D. The source region S is located in the upper region of the P-type body region 10b. The drain region D is located in the drift region on the side of the shallow trench isolation 40 away from the P-type body region 10b. In the present invention, the first drift region 10a and the second drift region 10c adopt N-type deep wells to achieve a higher breakdown voltage. A shallow trench isolation 40 is formed in the first drift region 10a, and a shallow trench isolation 40 is also formed in the second drift region 10c. The shallow trench isolation 40 optimizes the drift region electric field, shortens the drift region current path, which is beneficial to the breakdown voltage and leakage current characteristics of the LDMOS device. The shallow trench isolation 40 process flow is simple and is easy to integrate with the CMOS process.
[0056] The present invention also provides a semiconductor device, including:
[0057] A substrate 10, the substrate includes a P-type body region 10b and a first drift region 10a and a second drift region 10c located on both sides of the P-type body region 10b;
[0058] A gate oxide layer is formed on the surface of the substrate, and a first gate 120 and a second gate 220 are formed on the surface of the gate oxide layer;
[0059] The width La of the first gate 120 covering the P-type body region 10b is equal to the width Lb of the second gate 220 covering the P-type body region 10b, and the width Lc of the first gate 120 covering the first drift region 10a is equal to the width Ld of the second gate 220 covering the second drift region 10c.
[0060] In summary, the present invention provides a method for manufacturing a semiconductor device, including: Step S1, providing a substrate, forming a first oxide layer and a hard mask layer on the surface of the substrate, sequentially etching the hard mask layer, the first oxide layer, and a part of the thickness of the substrate to form a plurality of first trenches; Step S2, isotropically wet-etching the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width; filling an isolation layer in the first trenches to form shallow trench isolation; Step S3, etching and removing the hard mask layer on one side of each of the two adjacent shallow trench isolations away from the middle region; wet-etching and removing the part of the shallow trench isolation that protrudes above the substrate; Step S4, forming a gate oxide layer, the gate oxide layer covering the remaining shallow trench isolation and the substrate; forming a gate material layer, the gate material layer covering the remaining middle hard mask layer and the gate oxide layer; using self-aligned dry etching of the gate material layer to form a first gate and a second gate with equal widths on both sides of the middle hard mask layer; removing the middle hard mask layer; Step S5, performing P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region; a first drift region and a second drift region are respectively formed in the substrate on both sides of the P-type body region; by controlling the ion implantation angle, the width of the first gate covering the P-type body region is equal to the width of the second gate covering the P-type body region.
[0061] The present invention uses isotropic wet etching of the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width to form a middle hard mask layer. The gate material layer covers the middle hard mask layer and the gate oxide layer; using sidewall self-aligned dry etching of the gate material layer to form a first gate and a second gate with equal widths on both sides of the middle hard mask layer; by controlling the P-type ion implantation angle for forming the P-type body region, the width of the first gate covering the P-type body region is equal to the width of the second gate covering the P-type body region; thereby making the width of the first gate covering the first drift region equal to the width of the second gate covering the second drift region; finally, the left and right dimensions of the transistors on both sides are symmetric, with good consistency, improving the reliability of the switching type LDMOS device.
[0062] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the methods disclosed in the embodiments, since they correspond to the devices disclosed in the embodiments, the description is relatively simple. For related parts, reference can be made to the description in the method part.
[0063] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Including: Step S1: Provide a substrate, form a first oxide layer and a hard mask layer on the surface of the substrate, sequentially etch the hard mask layer, the first oxide layer and a part of the thickness of the substrate to form a plurality of first trenches; Step S2: Isotropically wet-etch the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width; Fill an isolation layer in the first trenches to form shallow trench isolation; Step S3: Etch and remove the hard mask layer on the side of each of the two adjacent shallow trench isolations away from the middle region; Wet-etch and remove the part of the shallow trench isolation that protrudes above the substrate; Step S4: Form a gate oxide layer, the gate oxide layer covering the remaining shallow trench isolation and the substrate; Form a gate material layer, the gate material layer covering the remaining middle hard mask layer and the gate oxide layer; Use sidewall self-aligned dry etching to etch the gate material layer to form a first gate and a second gate with equal width on both sides of the middle hard mask layer; Remove the middle hard mask layer; Step S5: Perform P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region; A first drift region and a second drift region are respectively formed in the substrate on both sides of the P-type body region; By controlling the ion implantation angle, the width of the P-type body region covered by the first gate is equal to the width of the P-type body region covered by the second gate.
2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Step S1 further includes: Form an N-type deep well in the substrate through N-type ion implantation and thermal drive, and the N-type deep well is used to form the subsequent first drift region and second drift region; Form the first oxide layer and the hard mask layer on the surface of the substrate after forming the N-type deep well.
3. The manufacturing method of the semiconductor device according to claim 1, characterized in that, In step S2, the hard mask layer includes a silicon nitride layer; The hard mask layer is isotropically wet-etched with a hot phosphoric acid solution.
4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Step S3 specifically includes: S31: Form a second oxide layer, the second oxide layer covering the middle hard mask layer between two adjacent shallow trench isolations and exposing the hard mask layer on the side of each of the two adjacent shallow trench isolations away from the middle region; S32: Using the second oxide layer as a mask, wet-etch and remove the hard mask layer on the side of each of the two adjacent shallow trench isolations away from the middle region; S33: Wet-etch and remove the second oxide layer, the part of the shallow trench isolation that protrudes above the substrate, and the part of the first oxide layer not covered by the middle hard mask layer.
5. The manufacturing method of the semiconductor device according to claim 4, characterized in that, In step S33, a wet-etching solution with a high selectivity ratio for silicon oxide and the hard mask layer is selected, and the preset final etching state is achieved by controlling the etching time and etching speed.
6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, In step S5, inclined ion implantation is adopted to make the width of the P-type body region greater than the opening width between the first gate and the second gate; the inclination angle of the ion implantation for forming the part of the P-type body region covered by the first gate is inclined to the left and is equal to the inclination angle of the ion implantation for forming the part of the P-type body region covered by the second gate to the right.
7. The manufacturing method of the semiconductor device according to claim 1, wherein After step S5, it further includes: Forming sidewalls on both sides of the first gate and the second gate respectively.
8. The manufacturing method of the semiconductor device according to claim 7, wherein After forming the sidewalls, it further includes: Selectively performing source-drain ion implantation to form an N-type heavily doped region and a P-type heavily doped region, the N-type heavily doped region includes a source region and a drain region; the source region is located in the upper region of the P-type body region; the drain region is located in the drift region on the side away from the P-type body region of the shallow trench isolation.
9. A semiconductor device, characterized in that, It includes: A substrate, the substrate includes a P-type body region and a first drift region and a second drift region located on both sides of the P-type body region; A gate oxide layer is formed on the surface of the substrate, and spaced first and second gates are formed on the surface of the gate oxide layer; The width of the P-type body region covered by the first gate is equal to the width of the P-type body region covered by the second gate, and the width of the first drift region covered by the first gate is equal to the width of the second drift region covered by the second gate.
10. The semiconductor device according to claim 9, wherein Sidewalls are formed on both sides of the first gate and the second gate respectively; an N-type heavily doped region is formed in the substrate, the N-type heavily doped region includes a source region and a drain region; the source region is located in the upper region of the P-type body region; the drain region is located in the drift region on the side away from the P-type body region of the shallow trench isolation.