Method for preparing power device and power device
By adjusting the gate oxide layer thickness in the SiC VDMOSFET device, making it thinner in the cell region than the terminal region, the problem of early breakdown of the gate oxide layer is solved, and the high-temperature gate bias test of the device is passed.
Patent Information
- Application Number
- CN202510489964.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-18
- Publication Date
- 2025-07-04
AI Technical Summary
In SiC VDMOSFET devices, the gate oxide layer in the terminal area is too large due to excessive mechanical stress at the FOX slope climb, resulting in advance breakdown of the gate oxide layer at the slope climb, and cannot pass the high-temperature gate bias test.
A gate oxidation structure is formed on the front surface of the semiconductor laminated structure, so that its thickness in the cell region is smaller than that of the terminal region. The thickness of the gate oxidation layer is adjusted by photolithography and etching processes to retain a certain thickness of the gate oxidation structure in the cell region, and a thicker gate oxidation structure is formed in the terminal region to avoid excessive mechanical stress.
It effectively avoids the early breakdown of the gate oxide layer at the hill climb, ensuring that the power device can pass the high-temperature gate bias test and maintains device performance.
Smart Images
Figure CN120264800A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor power devices, and particularly relates to a method for manufacturing a power device and a power device. Background Art
[0002] In a SiC VDMOSFET device, due to the presence of a terminal, it is necessary to grow a FOX (Field Oxide) in the terminal region of the SiC VDMOSFET device to protect the terminal. The gate oxide layer covers the cell region and the terminal region, and in the terminal region, due to the presence of the FOX, there will be a region where the FOX slopes. And because there is a FOX slope in the terminal region, the mechanical stress of the gate oxide layer at the slope is too large, which will cause the gate oxide layer at the slope to break down prematurely, resulting in the SiC VDMOSFET not being able to pass the high-temperature gate bias test (HTGB, High Temperature Gate Bias). Summary of the Invention
[0003] The object of the present invention is to provide a method for manufacturing a power device and a power device. Without affecting the power device, the present invention can avoid the premature breakdown of the gate oxide layer at the slope of the field oxide layer, enabling the power device to pass the high-temperature gate bias test.
[0004] The present invention provides a method for manufacturing a power device, characterized by comprising: Forming a gate oxide structure on the front surface of a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region; wherein, the gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is less than the thickness in the terminal region.
[0005] Further, forming a gate oxide structure on the front surface of a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region; wherein, the gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is less than the thickness in the terminal region.
[0006] Further, the forming a gate oxide structure on the front surface of the semiconductor stack structure includes: Providing a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region; Step S1-1, forming a first gate oxide layer on the front surface of the semiconductor stack structure; Step S1-2: Remove the part of the first gate oxide layer in the cell region by photolithography and etching, and retain a part of the cell region. Step S1-3: Form a second gate oxide layer, which covers the surface of the cell region and the first gate oxide layer, thereby forming the gate oxide structure.
[0007] Further, in step S1-2, removing the part of the first gate oxide layer in the cell region and retaining a part of the cell region includes the following steps: Step S1-2-1: Define the cell region in the first gate oxide layer by photolithography. Step S1-2-2: Remove the first gate oxide layer in the cell region by etching. Step S1-2-3: Remove the photoresist.
[0008] Further, in step S1-2-2, the first gate oxide layer in the cell region is removed by wet etching.
[0009] Further, in step 1-2-3, the photoresist is removed by a dry combined with wet process.
[0010] Further, forming the gate oxide structure on the front surface of the semiconductor stack structure includes the following steps: Provide a semiconductor stack structure, which includes a cell region and a terminal region, and a field oxide layer is provided on the front surface of the terminal region. Form a gate oxide layer on the front surface of the semiconductor stack structure, and the gate oxide layer covers the cell region and the terminal region. By photolithography and etching processes, etch the gate oxide layer located in the cell region by a predetermined thickness to obtain the gate oxide structure.
[0011] Further, etching the gate oxide layer located in the cell region by a predetermined thickness includes the following steps: Step S2-2-1: Define the cell region in the gate oxide layer by photolithography. Step S2-2-2: Etch the gate oxide layer in the cell region by a predetermined thickness by an etching process. Step S2-2-3: Remove the photoresist by a dry combined with wet process.
[0012] Further, the thickness of the gate oxide structure in the terminal region is 1.9 - 2.1 times the thickness in the cell region.
[0013] Further, the method for manufacturing a power device further includes successively forming a polysilicon layer, a dielectric layer, a metal layer, a passivation layer, and a polyimide layer to obtain the power device.
[0014] The present invention also provides a power device, which successively includes from bottom to top: A semiconductor stack structure, the semiconductor stack structure includes a cell region and a terminal region, and a field oxide layer is provided on the front surface of the terminal region; A gate oxide structure, stacked on the front surface of the semiconductor stack structure, the gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is less than the thickness in the terminal region; and A gate; A dielectric layer; and A metal interconnect structure layer.
[0015] Advantages of the present invention: In the method for manufacturing a power device of the present invention, since the thickness of the gate oxide structure in the cell region is less than the thickness in the terminal region, it can not only have a certain thickness of the gate oxide structure in the cell region to ensure the device performance of the cell region, but also have a thicker gate oxide structure in the terminal region to avoid excessive mechanical stress of the gate oxide structure at the ramp of the field oxide layer, resulting in premature breakdown of the gate oxide layer at the ramp, thereby causing the problem that the SiC VDMOSFET cannot pass the high-temperature gate bias test. Description of the drawings
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.
[0017] Figure 1 Shows a flowchart of forming a gate oxide structure on the front surface of a semiconductor stack structure in an embodiment of the present invention; Figure 2 Shows a specific flowchart of step S1-2 in an embodiment of the present invention; Figure 3 Shows a flowchart of forming a gate oxide structure on the front surface of a semiconductor stack structure in another embodiment of the present invention; Figure 4 Shows a specific flowchart of step S2-2 in another embodiment of the present invention; Figure 5 Shows a flowchart of manufacturing a SiC VDMOSFET in an embodiment of the present invention; Figure 6 Shows a structural diagram of a semiconductor stack structure in an embodiment of the present invention; Figure 7Shows the structural diagram after completing step 1 in the preparation of SiC VDMOSFET in an embodiment of the present invention; Figure 8 Shows the structural diagram after completing step 2 in the preparation of SiC VDMOSFET in an embodiment of the present invention; Figure 9 Shows the structural diagram after completing step 3 in the preparation of SiC VDMOSFET in an embodiment of the present invention; Figure 10 Shows the structural diagram after completing step 4 in the preparation of SiC VDMOSFET in an embodiment of the present invention; Figure 11 Shows the structural diagram after completing step 5 in the preparation of SiC VDMOSFET in an embodiment of the present invention; Figure 12 Shows the structural diagram after completing step 6 in the preparation of SiC VDMOSFET in an embodiment of the present invention. Detailed implementation manners
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.
[0019] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the specification and claims of the present patent application do not denote any order, quantity, or importance, but are only used to distinguish different components.
[0020] In this specification, the semiconductor stack structure is a semi-finished product with a cell region and a terminal region that has been completed by existing semiconductor manufacturing processes. After only completing the preparation of the gate oxide layer, the gate structure, dielectric layer, etc. can be further formed to fabricate a power device. As an embodiment, as Figure 6 shown, the semiconductor stack structure 100 includes: a Ti / Ni / Ag metal layer 11, a Ti metal layer 12, a heavily doped N+-type silicon carbide substrate 13, and a lightly doped N-type silicon carbide epitaxial layer 14 stacked in sequence. The semiconductor stack structure 100 includes a cell region 20 and a terminal region 30. Specifically, as Figure 6It is divided by a black dotted line. The left side is the cell region 20, and the right side is the terminal region 30. In the cell region 20, a plurality of P-type doped well regions 22 distributed at intervals are formed on the silicon carbide epitaxial layer 14 through a selective ion implantation process. A JFET region 21 is formed between adjacent P-type doped well regions 22. A heavily doped P+ source region 23 is implanted in the middle of the P-type doped well region 22 through a high-dose ion implantation process. Heavily doped N+ regions 24 symmetrically distributed are formed on both sides of the P+ source region 23 through the same process. The N+ regions 24 form a direct ohmic contact with the P+ source region 23. In the terminal region 30, a continuously or discretely arranged heavily doped P+ source region 32 is implanted in the silicon carbide epitaxial layer 14 through a high-dose ion implantation process. Two field oxide layers 31 arranged at intervals cover the front surface of the terminal region 30. The field oxide layer 31 is formed through a thermal oxidation or chemical vapor deposition process and is used to optimize the terminal electric field distribution. In this application, the semiconductor stack structure 100 is not limited to this. It only needs to have a field oxide layer (FOX) on the front surface of the terminal region. The subsequent gate oxide structure and gate structure need to be grown on the front surface with the field oxide layer (FOX). For the convenience of description, the semiconductor stack structure in this specification takes the structure of this embodiment as an example. The semiconductor stack structure in this embodiment is used to prepare a silicon carbide vertical double-diffused metal oxide semiconductor field effect transistor (SiC VDMOSFET).
[0021] The semiconductor stack structure can also be used to prepare silicon-based power devices, gallium nitride-based power devices, etc. It can be understood that as long as the semiconductor stack structure of the power device satisfies the inclusion of a cell region and a terminal region, and a field oxide layer needs to be grown in the terminal region, then the semiconductor stack structure belongs to the semiconductor stack structure required by the present invention.
[0022] This embodiment provides a method for manufacturing a power device, including: Forming a gate oxide structure on the front surface of the semiconductor stack structure. The semiconductor stack structure includes a cell region and a terminal region, and a field oxide layer is provided on the front surface of the terminal region. Among them, the gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is less than the thickness in the terminal region.
[0023] In the present invention, since the thickness of the gate oxide structure in the cell region is less than the thickness in the terminal region, therefore, it can not only have a certain thickness of the gate oxide structure in the cell region to ensure the device performance of the cell region, but also have a relatively thick gate oxide structure in the terminal region to avoid excessive mechanical stress at the ramp of the gate oxide structure, resulting in premature breakdown of the gate oxide layer at the ramp, thereby causing the problem that the power device cannot pass the high-temperature gate bias test.
[0024] It should be noted that: The boundary of the thickness change of the gate oxide structure in the cell region and the terminal region is not exactly the same as the boundary between the cell region and the terminal region of the semiconductor stack structure. It is sufficient that the thicker part of the gate oxide structure can completely cover the field oxide layer and exceed a predetermined distance, and this predetermined distance can meet the requirements that the gate oxide layer at the ramp cannot be broken down prematurely and can pass the high-temperature gate bias test.
[0025] This embodiment provides a method for manufacturing a power device, including: Forming a gate oxide structure on the front surface of a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region; wherein, the gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is less than the thickness in the terminal region.
[0026] Specifically, the material of the gate oxide structure is silicon dioxide (SiO2), hafnium-based oxide (HfO2, HfSiO), aluminum-based oxide (Al2O3), etc. Optimally, the material of the gate oxide structure is silicon dioxide (SiO2). In some examples, the method for manufacturing a power device further includes: sequentially forming a polysilicon layer, a dielectric layer, a metal layer, a passivation layer, and a polyimide layer to obtain the power device.
[0027] In some examples, as Figure 1 shown, forming a gate oxide structure on the front surface of the semiconductor stack structure includes the following steps: Step S1-1, providing a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region, and forming a first gate oxide layer on the front surface of the semiconductor stack structure.
[0028] Specifically, the first gate oxide layer is formed at a high temperature on the front surface of the semiconductor stack structure by thermal oxidation. Of course, the first gate oxide layer can also be formed on the front surface of the semiconductor stack structure by chemical vapor deposition (CVD) or atomic layer deposition (ALD). It can be understood that as long as the first gate oxide layer can be formed on the front surface of the semiconductor stack structure, the specific method used is not limited in this specification.
[0029] Specifically, the thickness of the first gate oxide layer is 400 angstroms.
[0030] Step S1-2, removing the part of the first gate oxide layer in the cell region by photolithography and etching and retaining the part in the cell region.
[0031] In some examples, as Figure 2 shown, removing the part of the first gate oxide layer in the cell region by photolithography and etching and retaining the part in the cell region includes the following steps: Step S1-2-1, define the cell region on the first gate oxide layer through a photolithography process. Specifically, first, apply photoresist on the first gate oxide layer. Then, perform exposure. Align the photomask with the first gate oxide layer to ensure the pattern position accuracy. Use a lithography machine (such as ultraviolet light UV, deep ultraviolet light DUV, extreme ultraviolet light EUV) to pass through the mask, causing a photochemical reaction in the photoresist. Finally, immerse the semiconductor layer stack structure deposited with the first gate oxide layer after exposure into the developer to form a three-dimensional pattern corresponding to the mask, that is, the cell region is not covered with photoresist, and the terminal region is covered with photoresist.
[0032] Step S1-2-2, remove the first gate oxide layer in the cell region through etching.
[0033] In some examples, using the photoresist as a mask, remove the first gate oxide layer in the cell region through wet etching.
[0034] Step S1-2-3, remove the photoresist.
[0035] In some examples, remove the photoresist through a dry combined with wet process.
[0036] Step S1-3, form a second gate oxide layer. The second gate oxide layer covers the surfaces of the cell region and the first gate oxide layer to form the gate oxide structure.
[0037] Specifically, form the second gate oxide layer at a high temperature through a thermal oxidation method. Of course, the second gate oxide layer can also be formed through chemical vapor deposition (CVD) or atomic layer deposition (ALD). It can be understood that as long as the first gate oxide layer can be formed on the front surface of the structure formed in step S1-2-3, the specific method used is not limited in this specification.
[0038] Specifically, the thickness of the second gate oxide layer is 400 angstroms.
[0039] In some examples, as Figure 3 shown, forming the gate oxide structure on the front surface of the semiconductor layer stack structure includes the following steps: Step S2-1, provide a semiconductor layer stack structure. The semiconductor layer stack structure includes a cell region and a terminal region, and a field oxide layer is provided on the front surface of the terminal region. Form a gate oxide layer on the front surface of the semiconductor layer stack structure. The gate oxide layer covers the cell region and the terminal region. Specifically, the thickness of the gate oxide layer is 800 angstroms.
[0040] Step S2-2, through photolithography and etching processes, etch the gate oxide layer located in the cell region to a predetermined thickness to obtain the gate oxide structure. Specifically, the etched In some examples, as Figure 4As shown, etching a predetermined thickness of the gate oxide layer in the cell region includes the following steps: Step S2-2-1, defining the cell region in the gate oxide layer through a photolithography process.
[0041] Specifically, first, apply photoresist on the gate oxide layer. Then, perform exposure. Align the photomask with the gate oxide layer to ensure the pattern position accuracy. Use a lithography machine (such as ultraviolet light UV, deep ultraviolet light DUV, extreme ultraviolet light EUV) to pass through the mask, causing a photochemical reaction in the photoresist. Finally, immerse the semiconductor layer stack structure with the deposited gate oxide layer after exposure into the developer to form a three-dimensional pattern corresponding to the mask, that is, the cell region is not covered with photoresist, and the terminal region is covered with photoresist.
[0042] Step S2-2-2, etching the gate oxide layer in the cell region by a predetermined thickness through an etching process.
[0043] Specifically, etch the gate oxide layer in the cell region by a predetermined thickness through a dry etching process. Specifically, the thickness of the etched gate oxide layer in the cell region is 800 angstroms, and the remaining thickness of the gate oxide layer in the cell region is 400 angstroms.
[0044] Step S2-2-3, removing the photoresist through a dry combined with wet process.
[0045] In some examples, the thickness of the gate oxide structure in the terminal region is 1.9 - 2.1 times the thickness in the cell region. Optimally, the thickness of the gate oxide structure in the terminal region is 2 times the thickness in the cell region. Specifically, the thickness of the gate oxide structure in the terminal region is 800 angstroms, and the thickness of the gate oxide structure in the cell region is 400 angstroms.
[0046] Specifically, taking the preparation of SiC VDMOSFET as an example, as Figure 5 shown, the specific process of preparing the power device is as follows: Provide a semiconductor stack structure, as Figure 6 shown, the semiconductor stack structure 100 includes: including a Ti / Ni / Ag metal layer 11, a Ti metal layer 12, a heavily doped N+-type silicon carbide substrate 13, and a lightly doped N-type silicon carbide epitaxial layer 14 stacked in sequence. The semiconductor stack structure 100 includes a cell region 20 and a terminal region 30. In the terminal region 30, the silicon carbide epitaxial layer 14 forms a P+ source region 32 through extremely high-concentration ion implantation, and two field oxide layers 31 are provided in the terminal region 30.
[0047] Step 1, thermally oxidize at a high temperature on the front surface of the semiconductor layer stack structure to form a first gate oxide layer 40. After Step 1, the formed structure is as Figure 7 shown.
[0048] Step 2: Define the cell region in the first gate oxide layer through a lithography process. After step 2, the formed structure is as shown in Figure 8 . In the figure, there is no photoresist above the cell region in the first gate oxide layer 40, and a layer of photoresist 50 covers the first gate oxide layer 40 above the terminal region. The cell region defined by the lithography process does not completely coincide with the cell region divided in the semiconductor stack structure 100, that is, the cell region defined by the lithography process exceeds the cell region divided in the semiconductor stack structure 100. The terminal region covered by the photoresist is smaller than the terminal region divided in the semiconductor stack structure 100. The region covered by the photoresist completely includes the field oxide layer and exceeds a certain distance to the left of the long oxide layer. This distance can prevent the gate oxide layer at the ramp from being prematurely broken down and can pass the high-temperature gate bias test.
[0049] Step 3: Remove the first gate oxide layer 40 in the cell region through wet etching. After step 3, the formed structure is as shown in Figure 9 . On the front side of the semiconductor stack structure 100, there is no first gate oxide layer 40 in the cell region, and the first gate oxide layer 40 and the photoresist 50 are sequentially stacked in the terminal region.
[0050] Step 4: Remove the photoresist through a dry and wet combined process. After step 4, the formed structure is as shown in Figure 10 . Only a first gate oxide layer 40 covers the front side of the semiconductor stack structure 100 in the terminal region.
[0051] Step 5: High-temperature form the second gate oxide layer through thermal oxidation. The second gate oxide layer covers the surfaces of the cell region and the first gate oxide layer to form the gate oxide structure 200. After step 5, the formed structure is as shown in Figure 11 . The gate oxide structure 200 is formed on the front side of the semiconductor stack structure 100.
[0052] Step 6: Sequentially complete the preparation of the polysilicon 300, dielectric layer 500, metal interconnect structure layer 400, passivation layer 600, and polyimide layer 700 to obtain the power device. The specific processes for forming each structure layer in this step are not elaborated in detail, and existing processes can be selected for preparation. The power device obtained after step 6 is as shown in Figure 12 .
[0053] The present invention also provides a semiconductor device, which sequentially includes from bottom to top: a semiconductor stack structure, a gate oxide structure, a gate, a dielectric layer, and a metal interconnect structure layer.
[0054] The semiconductor stack structure includes a cell region and a terminal region, and a field oxide layer is provided on the front side of the terminal region. The gate oxide structure is stacked on the front side of the semiconductor stack structure. The gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is smaller than the thickness in the terminal region.
[0055] In one embodiment, the semiconductor device is a power device 1000. As Figure 12 shown, the power device 1000 includes: a semiconductor stack structure 100, a gate oxide structure 200, a gate 300, a metal interconnect structure layer 400, a dielectric layer 500, etc.
[0056] The semiconductor stack structure 100 includes a cell region 20 and a terminal region 30, and a field oxide layer 31 is provided on the front surface of the terminal region 30.
[0057] The gate oxide structure 200 is stacked on the front surface of the semiconductor stack structure 100. The gate oxide structure 200 covers the cell region 20 and the terminal region 30, and the thickness in the cell region 20 is less than the thickness in the terminal region 30.
[0058] The source is provided in the active region of the semiconductor stack structure, the gate is provided on the gate oxide structure, and the drain is provided on the semiconductor stack structure.
[0059] Specifically, taking SiC VDMOSFET as an example, as Figure 6 shown, it is fabricated on the semiconductor stack structure 100. The front surface of the semiconductor stack structure 100 has a field oxide layer 31 located in the terminal region. The method for fabricating a power device as described in the above embodiments is used to form a gate oxide structure 200 on its front surface. The thickness of the gate oxide structure 200 in the terminal region is greater than its thickness in the cell region. As Figure 12 shown, the gate 300 is provided on the gate oxide structure 200. Specifically, the gate 300 is polysilicon. A dielectric layer 500, a metal interconnect structure layer 400, a passivation layer 600, and a polyimide layer 700 are sequentially formed above the gate 300. The metal interconnect structure layer 400 can be a multi-layer metal structure. For example, a nickel layer and an Al / Cu layer, the nickel layer is the bottom metal, and the Al / Cu layer is the upper metal.
[0060] The text and drawings in this disclosure are provided only as examples to assist in understanding the disclosure. They should not be construed as limiting the scope of the disclosure in any way. Although certain embodiments and examples have been provided, it will be clear to those skilled in the art based on the content disclosed herein that the shown embodiments and examples can be changed without departing from the scope of the disclosure.
[0061] Although the disclosure has been described with exemplary embodiments, various changes and modifications can be suggested to those skilled in the art. The disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.
[0062] None of the descriptions in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.
Claims
1. A method for manufacturing a power device, characterized in that, Comprising: Forming a gate oxide structure on the front surface of a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region; wherein, the gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is less than the thickness in the terminal region.
2. The method for manufacturing a power device according to claim 1, wherein, The forming of the gate oxide structure on the front surface of the semiconductor stack structure includes: Providing a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region; Step S1-1, forming a first gate oxide layer on the front surface of the semiconductor stack structure; Step S1-2, removing a part of the first gate oxide layer in the cell region by photolithography and etching and retaining a part of the cell region; Step S1-3, forming a second gate oxide layer, the second gate oxide layer covering the cell region and the surface of the first gate oxide layer, thereby forming the gate oxide structure.
3. The method for manufacturing a power device according to claim 2, wherein, In step S1-2, removing a part of the first gate oxide layer in the cell region and retaining a part of the cell region includes the following steps: Step S1-2-1, defining the cell region in the first gate oxide layer by a photolithography process; Step S1-2-2, removing the first gate oxide layer in the cell region by etching; Step S1-2-3, removing the photoresist.
4. The method for manufacturing a power device according to claim 3, wherein, In step S1-2-2, removing the first gate oxide layer in the cell region by wet etching.
5. The method for manufacturing a power device according to claim 3, wherein, In step 1-2-3, removing the photoresist by a dry combined with wet process.
6. The method for manufacturing a power device according to claim 1, wherein, The forming of the gate oxide structure on the front surface of the semiconductor stack structure includes the following steps: Providing a semiconductor stack structure, the semiconductor stack structure including a cell region and a terminal region, and a field oxide layer being provided on the front surface of the terminal region; Forming a gate oxide layer on the front surface of the semiconductor stack structure, the gate oxide layer covering the cell region and the terminal region; By photolithography and etching processes, etching away a predetermined thickness of the gate oxide layer located in the cell region to obtain the gate oxide structure.
7. The method for manufacturing a power device according to claim 6, wherein, The etching away of a predetermined thickness of the gate oxide layer located in the cell region includes the following steps: Step S2-2-1, defining the cell region in the gate oxide layer by a photolithography process; Step S2-2-2, etching away a predetermined thickness of the gate oxide layer in the cell region by an etching process; Step S2-2-3, removing the photoresist by a dry combined with wet process.
8. The method for manufacturing a power device according to claim 1, wherein, The thickness of the gate oxide structure in the terminal region is 1.9 - 2.1 times that in the cell region.
9. The method for preparing a power device according to claim 1, wherein, It further includes: A power device is fabricated by successively forming a polysilicon layer, a dielectric layer, a metal layer, a passivation layer, and a polyimide layer.
10. A power device, characterized in that, It includes, from bottom to top: A semiconductor stack structure, the semiconductor stack structure includes a cell region and a terminal region, and a field oxide layer is provided on the front surface of the terminal region; A gate oxide structure, stacked on the front surface of the semiconductor stack structure, the gate oxide structure covers the cell region and the terminal region, and the thickness in the cell region is less than that in the terminal region; A gate; A dielectric layer; and A metal interconnect structure layer.