High-voltage device

Abstract

A high voltage device includes a high voltage junction boundary component, and a transistor extending annularly along the high voltage junction boundary component. From a top view, the transistor has one or more first U-shaped segments. Each first U-shaped section comprises a first linear part, a second linear part corresponding to the first linear part, and a first arc-shaped part connecting the first linear part and the second linear part. According to the high-voltage device, the wiring width of the transistor can be increased so as to increase the forward current of the transistor, the area of the whole ring on a chip can be saved, and waste of the area of the chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage devices, and specifically to a high-voltage device, especially regarding the optimization of the routing design of transistors. Background Art

[0002] In most switching applications, the switching efficiency depends on the switching loss and the switching speed. One way to supply power to the gate driver of a high-voltage circuit is to use a bootstrap circuit, which exhibits the advantages of simplicity and low cost. The bootstrap circuit includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR), and can provide the voltage level of the high-voltage circuit.

[0003] Although existing high-voltage devices generally meet their original uses, they are not satisfactory in all aspects. For example, the forward current needs further improvement. Therefore, there are still some problems to be overcome regarding high-voltage devices and manufacturing technologies. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-voltage device that can increase the routing width of the transistor to increase the forward current of the transistor, and can save the overall annular area on the chip and reduce the waste of the chip area.

[0005] The purpose of the present invention is achieved as follows: A high-voltage device includes a high-voltage junction boundary component and a transistor extending annularly along the high-voltage junction boundary component. From a top view, the transistor has one or more first U-shaped segments. Each first U-shaped segment includes a first linear portion, a second linear portion disposed corresponding to the first linear portion, and a first arc portion connecting the first linear portion and the second linear portion.

[0006] The technical solution of the present invention has the following advantages over the prior art:

[0007] The transistor can extend annularly along the high-voltage junction boundary component to have a relatively large extension size; by designing the routing width of the transistor to meet the desired forward current, the transistor has a U-shaped segment design, which can increase the routing width of the transistor, save the overall annular area on the chip at the same time, increase the forward current of the transistor, and thus more effectively avoid leakage current. Brief Description of the Drawings

[0008] Aspects of embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0009] Figure 1 is a top view of a high-voltage device according to a comparative example.

[0010] Figure 2 and Figure 3 are top views of a high-voltage device according to some embodiments of the present invention, respectively.

[0011] Figure 4 and Figure 5 are top views of high-voltage devices with various designs according to other embodiments of the present invention, respectively.

[0012] Figure 6 is a forward current-dimension curve graph of a high-voltage device according to some embodiments of the present invention.

[0013] Explanation of reference numerals in the drawings:

[0014] 10: High-voltage device

[0015] 20: High-voltage device

[0016] 30: High-voltage device

[0017] 40: High-voltage device

[0018] 50: Forward current-dimension curve graph

[0019] 100: High-voltage junction boundary component

[0020] 100A: High-voltage region

[0021] 100B: Low-voltage region

[0022] 200: Isolation diode

[0023] 300: Transistor

[0024] 300A: Concave corner

[0025] 300B: Convex corner

[0026] 300U: U-shaped section

[0027] 300U’: U-shaped section

[0028] 300U-1: Linear part

[0029] 300U-2: Linear part

[0030] 300U-3: Arc part

[0031] 320: Source region

[0032] 340: Drain region

[0033] 360: Gate structure

[0034] 400: Level shifter Detailed implementation manners

[0035] The following description provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, when it is described that the first component is formed on the second component, it may include an embodiment in which the first component and the second component are in direct contact, or may also include an embodiment in which additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. In addition, the present invention may repeat component symbols and / or letters in various examples. Such repetition is for the purpose of simplification and clarity, and does not itself dominate the relationship between the various embodiments and / or configurations discussed.

[0036] In addition, in some embodiments of the present invention, terms related to bonding and connection, such as "connected", "interconnected", etc., unless specifically defined, may refer to two structures in direct contact, or may also refer to two structures not in direct contact, with other structures disposed between these two structures.

[0037] Furthermore, spatially relative terms such as "under", "below", "lower than", "above", "upper", and the like may be used herein to describe the relationship between one component or part and other components or parts as shown in the figure. These spatial terms are intended to include different orientations of the device in use or operation, as well as the orientations shown in the figures. When the device is turned to other orientations (rotated 90° or other orientations), the spatially relative descriptions used herein can be interpreted accordingly in the rotated orientations.

[0038] The terms "about", "approximately", "substantially" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or ±3%, or ±2%, or ±1%, or 0.5% of the given value. The given value is an approximate value, that is, in the case where there is no specific description of "about", "approximately", "substantially", the given value can still imply the meaning of "about", "approximately", "substantially".

[0039] The following describes some embodiments of the present invention. Before, during, and / or after the multiple stages described in these embodiments, additional steps may be provided. The high-voltage device structure may include additional components. Some of these components may be replaced or omitted in different embodiments. Although some of the steps discussed in the embodiments are performed in a specific order, these steps may still be performed in another logical order.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It is understood that these terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention.

[0041] To improve switching efficiency, a bootstrap circuit can be incorporated into the high-voltage device, which includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR). The key parameters of the bootstrap diode in the bootstrap circuit are the reverse recovery time, the forward conduction voltage drop, and the reverse blocking voltage, respectively. In traditional designs, the bootstrap diodes are generally in a discrete configuration. The discrete bootstrap diodes are placed outside the high-voltage device and are individually connected to the high side and the low side of the high-voltage device. To meet the requirements of the cut-off breakdown voltage, the bootstrap diodes must be achieved by relaxing the design rules, which results in a relatively large component size. Since the discrete bootstrap diodes are not integrated into the high-voltage device, they may occupy too much space and increase the cost of the additional bills of materials (BOM). Therefore, the above problems can be solved by using buried bootstrap diodes integrated into the high-voltage device. However, compared with the discrete bootstrap diodes, the buried bootstrap diodes may generate a forward leakage current from the anode terminal to the substrate (vertical bipolar junction) during operation, while there is no significant reverse leakage current at the cathode terminal because there is no bipolar junction. Therefore, an isolation component (such as a buried layer) can be further added to the buried bootstrap diodes to reduce the generation of the forward leakage current.

[0042] When a high-voltage device integrates a buried bootstrap diode and a high-voltage junction termination (HVJT) component in a configuration, the transistor in the bootstrap diode can utilize the annular profile of the high-voltage junction termination component and then extend along the annulus to save extra space. It should be understood that when the extension dimension of the transistor (such as the trace width) is larger, the forward current of the transistor can also increase to drive the bootstrap diode. To accommodate the extension dimension of the transistor, the annulus of the high-voltage junction termination component must also occupy a larger chip area. However, generally, the components required in the high-voltage region do not occupy too much space, resulting in a high proportion of the space in the overly large annulus not being used, leading to waste of chip area. The inventors found that the high-voltage junction termination component and the profile of the corresponding transistor can be designed to have a U-shaped segment (such as a shape like a hairpin bend) to save space in the high-voltage region while maintaining the extension dimension required by the transistor.

[0043] Figure 1 FIG. is a top view of a high-voltage device 10 according to a comparative example. In some embodiments, a high-voltage device generally may include any number of active components and passive components. Active components include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, laterally diffused metal-oxide semiconductor (LDMOS) transistors, bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistors, bipolar junction transistors (BJT), planar transistors, fin field-effect transistors (FinFET), gate-all-around field-effect transistors (GAA FET), other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bond pads, or other similar structures.

[0044] Referring to Figure 1, the high-voltage device 10 may include a high-voltage junction boundary component 100, an isolation diode 200, a transistor 300, and a plurality of level shifters 400. In some embodiments, the high-voltage junction boundary component 100 may be designed in a ring shape. A high-voltage region 100A may be defined within the ring of the high-voltage junction boundary component 100, and a low-voltage region 100B may be defined outside the ring of the high-voltage junction boundary component 100. Furthermore, the isolation diode 200 and the transistor 300 may form a bootstrap diode in a buried configuration. The transistor 300 and the plurality of level shifters 400 may both be integrated into the ring of the high-voltage junction boundary component 100, thus effectively saving the overall area of the high-voltage device 10. In addition, the integrated configuration electrically couples the high-voltage junction boundary component 100, the isolation diode 200, the transistor 300, and the plurality of level shifters 400 to each other, thus omitting wire bonding and via formation, resulting in improved reliability.

[0045] Continuing to refer to Figure 1 , although the high-voltage junction boundary component 100 is shown as a rectangular ring, the embodiments of the present invention are not limited thereto. For example, the high-voltage junction boundary component 100 may be a circular ring, an oval ring, a square ring, a triangular ring, or any suitable closed geometric ring. The ring configuration makes the integration of the high-voltage junction boundary component 100 with the isolation diode 200, the transistor 300, and the plurality of level shifters 400 more efficient and does not occupy additional chip area. The high-voltage junction boundary component 100 physically and electrically separates the high-voltage region 100A and the low-voltage region 100B. The high-voltage region 100A may accommodate components operating at a high-voltage level, and the low-voltage region 100B may accommodate components operating at a low-voltage level. Generally, "high voltage" generally refers to a voltage above 300V, such as between 300V and 1200V, between 300V and 750V, or between 750V and 1200V. "Low voltage" generally refers to a voltage below 20V, such as between 1V and 20V, between 1V and 10V, or between 10V and 20V. In a specific embodiment of the present invention, the high-voltage region 100A and the low-voltage region 100B operate at voltages of 600V and 15V, respectively.

[0046] Refer to Figure 1, an isolation diode 200 can be disposed in the low voltage region 100B. In some embodiments, the isolation diode 200 can be electrically connected to the transistor 300. As previously mentioned, in order to avoid the forward leakage current generated from the anode terminal to the substrate (vertical bipolar junction), a buried layer can be added, for example, to suppress the leakage current of the substrate to less than 1%. As a result, the component architecture coupled with the isolation diode 200 and the transistor 300 can withstand a reverse blocking voltage of 650V and a forward current of 17mA. In addition, the recovery time required for the isolation diode 200 to switch from the conducting state to the off state can be between 10nsec and 50nsec.

[0047] Continuing to refer to Figure 1 , the transistor 300 can extend annularly along the high voltage junction boundary component 100. It should be understood that both the transistor 300 and the plurality of level shifters 400 are integrally formed annularly with the high voltage junction boundary component 100. Therefore, the plurality of level shifters 400 occupy a section of the annulus of the high voltage junction boundary component 100, while the transistor 300 traverses the remaining section of the annulus of the high voltage junction boundary component 100. The transistor 300 can be designed in depletion mode (normally open and conducting at a gate voltage of 0V), or can be designed in enhancement mode (normally off at a gate voltage of 0V). In a specific embodiment of the present invention, the transistor 300 can be a laterally diffused metal oxide semiconductor transistor. For example, when the gate voltage is 20V, the transistor 300 is in the forward mode, allowing current to flow. In contrast, when the gate voltage is 0V, the transistor 300 is in the reverse mode, preventing current from flowing. It should be understood that when using a laterally diffused metal oxide semiconductor transistor, the forward current of the bootstrap diode will be limited by the internal resistance of the laterally diffused metal oxide semiconductor transistor.

[0048] In some embodiments, the transistor 300 may include a source region 320, a drain region 340, and a gate structure 360. The source region 320 may be disposed adjacent to the low voltage region 100B, the drain region 340 may be disposed adjacent to the high voltage region 100A, and the gate structure 360 may be disposed between the source region 320 and the drain region 340. In addition, the isolation diode 200 may be located between the source region 320 of the transistor 300 and the body region (not shown) of the substrate ground terminal. During operation of the transistor 300, current may flow from the isolation diode 200 through the region under the source region 320 and the gate structure 360 to the drain region 340, and its flow rate may be controlled by the gate structure 360. In the case of not being integrated with the high voltage junction boundary component 100, the transistor 300 may have a circular design, such as a central circle of the drain region 340, and a ring of the gate structure 360, a ring of the source region 320, and a ring of the body region (if any) sequentially surrounding the drain region 340. Such a design may avoid the sharp edge effect, which may cause component failure. In addition, the circular design may also make the electric field distribution more uniform.

[0049] Referring Figure 1 , a plurality of level shifters 400 may be integrated in the ring of the high voltage junction boundary component 100. From another perspective, a plurality of level shifters 400 may be located on the ring of the high voltage junction boundary component 100. As previously mentioned, the plurality of level shifters 400 occupy a section of the ring of the high voltage junction boundary component 100, and the transistor 300 traverses the remaining section of the ring of the high voltage junction boundary component 100. It is worth noting that the plurality of level shifters 400 are spaced apart from each other, and the plurality of level shifters 400 are spaced apart from the transistor 300. Although Figure 1 two level shifters 400 are shown, the embodiments of the present invention are not limited thereto. For example, any number of level shifters 400 may be configured depending on the application and design requirements. According to some embodiments of the present invention, the level shifter 400 may convert signals between the high voltage region 100A and the low voltage region 100B. For example, the level shifter 400 may receive a signal from a control logic (not shown) to perform voltage switching from the high voltage region 100A to the low voltage region 100B, or from the low voltage region 100B to the high voltage region 100A.

[0050] According to some embodiments of the present invention, the transistor 300 and the level shifter 400 may have the same conductivity type. For example, both may be N-type. According to alternative embodiments of the present invention, the transistor 300 and the level shifter 400 may both have another conductivity type. For example, both may be P-type. In some embodiments, the P-type and N-type may be doped with appropriate dopants (or impurities) individually. P-type dopants may include boron (B), indium (In), aluminum (Al), or gallium (Ga), while N-type dopants may include phosphorus (P) or arsenic (As).

[0051] In a conventional process, the extension dimension (such as the trace width) of the transistor 300 (including the source region 320, the drain region 340, and the gate structure 360) may be increased to increase the forward current of the transistor 300 and preferably avoid leakage current. According to the performance requirements of the high-voltage device 10, the trace width required for the transistor 300 may be determined. When determining the trace width of the transistor 300, the loop of the high-voltage junction boundary component 100 also needs to be adjusted conformally to accommodate the transistor 300. More precisely, the extension dimension (such as the trace width) of the high-voltage junction boundary component 100 may be the sum of the trace width of the transistor 300 and the dimensions of the plurality of level shifters 400, as Figure 1 shown. The loop obtained by the high-voltage junction boundary component 100 may occupy a relatively large chip area, while the components in the high-voltage region 100A may occupy a relatively small chip area (such as the local space near the plurality of level shifters 400). As a result, a large proportion of the space within the loop of the high-voltage junction boundary component 100 will not be used, causing waste of the chip area.

[0052] For simplicity, only the main components of the high-voltage device 10 are shown, such as the high-voltage junction boundary component 100, the isolation diode 200, the transistor 300 (including the source region 320, the drain region 340, and the gate structure 360), and the plurality of level shifters 400. For example, the structure of the high-voltage device 10 may further include a substrate, a buried layer, an epitaxial layer, and an interlayer dielectric (ILD) layer. The substrate, the epitaxial layer, and the interlayer dielectric layer may span the entire circuit area, while the buried layer may be disposed in one or more of the main components. In other words, each of the high-voltage junction boundary component 100, the isolation diode 200, the transistor 300, and the level shifter 400 may include a substrate, an epitaxial layer, and an interlayer dielectric layer (and / or a buried layer).

[0053] In some embodiments, the substrate may be, for example, a wafer or a die, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate may be a semiconductor substrate, such as a silicon (Si) substrate. Additionally, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including a silicon germanium (SiGe) alloy, a gallium arsenide phosphide (GaAsP) alloy, an aluminum indium arsenide (AlInAs) alloy, an aluminum gallium arsenide (AlGaAs) alloy, a gallium indium arsenide (GaInAs) alloy, a gallium indium phosphide (GaInP) alloy, and / or a gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

[0054] In other embodiments, the substrate may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a bottom plate, a buried oxide (BOX) layer disposed on the bottom plate, and a semiconductor layer disposed on the buried oxide layer. For example, the substrate may be P-type, and its doping concentration may be between 1×10 14 cm -3 and 3×10 14 cm -3 .

[0055] In other embodiments, the substrate may include isolation structures (not shown) to define active regions and electrically isolate active region components within or on the substrate, but the embodiments of the present invention are not limited thereto. The isolation structures may include deep trench isolation (DTI) structures, shallow trench isolation (STI) structures, or local oxidation of silicon (LOCOS) structures. In some embodiments, forming the isolation structures may include, for example, forming an insulating layer on the substrate, selectively etching the insulating layer and the substrate to form trenches extending from the top surface of the substrate to a position within the substrate, where the trenches are located between adjacent active regions. Next, forming the isolation structures may include growing a liner rich in nitrogen (such as silicon oxynitride (SiON) or other similar materials) along the trenches, and then filling the trenches with an insulating material (such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. Thereafter, an annealing process is performed on the insulating material in the trenches, and a planarization process (such as chemical mechanical polish (CMP)) is performed on the substrate to remove the excess insulating material, making the insulating material in the trenches flush with the top surface of the substrate.

[0056] In some embodiments, an epitaxial layer is formed on the substrate. For example, the epitaxial layer may be N-type, and its doping concentration may be between 1.13×10 15 cm -3 and 2.30×10 15 cm-3. In other words, the substrate and the epitaxial layer may have different conductivity types, and the doping concentration of the substrate is less than that of the epitaxial layer. The material of the epitaxial layer may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer may be between 3 μm and 7 μm. The epitaxial layer may be formed by an epitaxial process, and the epitaxial process may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

[0057] In some embodiments, a buried layer may be disposed within the substrate. The buried layer may be in direct contact with the epitaxial layer. According to some embodiments of the present invention, the buried layer helps to reduce the leakage current from the upper surface of the epitaxial layer to the substrate, increase the channel space to withstand higher currents, and form the substrate of the high voltage region 100A. For example, the buried layer may be N-type, and its doping concentration may be between 6.4×10 16 cm -3 and 9.6×10 16 cm -3 . The vertical dimension of the buried layer may be between 1 μm and 2 μm. The method of forming the buried layer may include implanting an N-type dopant (such as phosphorus or arsenic) into the substrate by ion implantation before forming the epitaxial layer, performing a heat treatment to drive the implanted ions into the substrate, and then forming the epitaxial layer on the substrate. In some embodiments, since the epitaxial layer is formed under high temperature conditions, the implanted ions will diffuse into the epitaxial layer. The buried layer is located near the interface between the substrate and the epitaxial layer, and has a part within the substrate and another part within the epitaxial layer. In other words, the buried layer may extend upward from the interface between the substrate and the epitaxial layer.

[0058] In some embodiments, high voltage well regions, deep well regions, well regions, and doped regions of various conductivity types (such as P-type or N-type) may be formed in the epitaxial layer. The high voltage well regions, deep well regions, well regions, and doped regions may be formed by, for example, ion implantation and / or diffusion processes. In alternative embodiments, instead of using ion implantation and / or diffusion processes, the high voltage well regions, deep well regions, well regions, and doped regions may be doped in situ during the growth of the epitaxial layer. In other embodiments, in situ and implantation doping may be used together.

[0059] As Figure 1 shown, a source region 320 and a drain region 340 may be disposed in the epitaxial layer (not shown). The source region 320 and the drain region 340 may extend vertically from the upper surface of the epitaxial layer into the epitaxial layer. According to some embodiments of the present invention, the source region 320 and the drain region 340 may serve as the source terminal and the drain terminal of the transistor 300, respectively. The source region 320 and the drain region 340 may be N-type, and their doping concentration may be between 4.0×10 20 cm -3 and 6.0×10 20 cm -3 . Since the source region 320 and the drain region 340 are N-type, the transistor 300 may thus be N-type. The thickness of the source region 320 and the drain region 340 may be between 0.09 μm and 0.11 μm. The method of forming the source region 320 and the drain region 340 may be similar to the methods of forming the above-mentioned high voltage well regions, deep well regions, well regions, and doped regions, and the details will not be repeated here.

[0060] As Figure 1 shown, a gate structure 360 can be disposed on the epitaxial layer. As previously mentioned, the gate structure 360 can be horizontally located between the source region 320 and the drain region 340. According to some embodiments of the present invention, the gate structure 360 can serve as the gate terminal of the transistor 300 and can modulate the electric field in the underlying channel region. It should be understood that in high-voltage operations, the drain region 340 may accumulate an excessive electric field. To adjust the distribution of the electric field, the gate structure 360 is not disposed at the center point between the source region 320 and the drain region 340 in the horizontal direction. The gate structure 360 can be closer to the source region 320 and can be farther from the drain region 340. The thickness of the gate structure 360 can be between 3.5 μm and 4.0 μm.

[0061] The material of the gate structure 360 may include amorphous silicon, polysilicon, poly - SiGe, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, and metals. The metals may include cobalt (Co), ruthenium (Ru), aluminum (Al), palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, their combinations, or their multi - layer films. The gate structure 360 may be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), plating, other suitable processes, or their combinations.

[0062] In some embodiments, an inter - layer dielectric layer may be formed on the epitaxial layer. The inter - layer dielectric layer may cover the epitaxial layer and the gate structure 360. In addition to providing mechanical protection and insulation to the underlying components, the inter - layer dielectric layer may also isolate different levels of conductive materials. The material of the inter - layer dielectric layer may include silicon oxide (SiO), silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiO x N y C 1-x-y, where x and y are in the range of 0 to 1), tetraethyl orthosilicate (TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low-k dielectric materials, or other suitable dielectric materials.

[0063] The thickness of the interlayer dielectric layer can be between 1000 μm and 1200 μm. The interlayer dielectric layer can be formed by spin-on coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Then, a planarization process (such as chemical mechanical polishing) can be performed on the interlayer dielectric layer to make the interlayer dielectric layer have a flat top surface.

[0064] Figure 2 and Figure 3 is a top view of the high-voltage device 20 according to some embodiments of the present invention. Compared with Figure 1 of the high-voltage device 10, Figure 2 the transistor 300 of the high-voltage device 20 includes one or more U-shaped segments 300U. Figure 3 is one arrangement of the high-voltage device 20. For simplicity, the features of the high-voltage junction boundary component 100, isolation diode 200, transistor 300 (including source region 320, drain region 340, and gate structure 360), and multiple level shifters 400 are the same as Figure 1The features shown are similar, and their details will not be repeated here.

[0065] Referring to Figure 2 , each U-shaped segment 300U may include a linear portion 300U-1, a linear portion 300U-2, and an arcuate portion 300U-3. In some embodiments, the arcuate portion 300U-3 is close to the low-pressure region 100B. It is worth noting that the annular shape of the high-voltage junction boundary component 100 extends conformally along the contour of one or more U-shaped segments 300U. The linear portions 300U-1 and 300U-2 of each U-shaped segment 300U may be correspondingly arranged, and the arcuate portion 300U-3 may connect the linear portion 300U-1 and the linear portion 300U-2. For example, the arcuate portion 300U-3 may extend from the end point of the linear portion 300U-1 to the end point of the linear portion 300U-2, thereby forming a U-shaped contour. The U-shaped segment 300U is characterized by having an elongated contour, thus saving the space occupied by the overall ring. The transistor 300 (including the source region 320, the drain region 340, and the gate structure 360) may extend along the linear portion 300U-1 towards the arcuate portion 300U-3, pass through the arcuate portion 300U-3, and then extend along the linear portion 300U-2 away from the arcuate portion 300U-3, completing one cycle of the U-shaped segment 300U. It is worth noting that when each U-shaped segment 300U has a certain overall length, it can contribute to the extension dimension (such as the trace width) of the transistor 300 to reach at least twice the length or more.

[0066] It should be understood that since one or more U-shaped segments 300U contribute a significant extension dimension (such as the trace width) of the transistor 300, the size of the original rectangular portion of the ring can be compressed, thereby saving the space occupied by the overall ring. Each U-shaped segment 300U may extend outward from the relative side of the rectangular portion with respect to the location of the plurality of level shifters 400. For example, the plurality of level shifters 400 are located on the upper side of the rectangular portion, and one or more U-shaped segments 300U may extend downward from the lower side of the rectangular portion. Although Figure 2Three U-shaped segments 300U are shown (at the left end, the midpoint, and the right end of the lower side of the rectangular portion, respectively), but the embodiments of the present invention are not limited thereto. For example, any number of U-shaped segments 300U can be configured, depending on the application and design requirements. The space between the linear portion 300U-1 and the linear portion 300U-2 is very limited, thus further reducing the space occupied by the overall ring. According to a specific embodiment of the present invention, the linear portion 300U-1 can be directly adjacent to the linear portion 300U-2, such that there is no space between the linear portion 300U-1 and the linear portion 300U-2 (making the U-shaped segment 300U present a shape similar to a hairpin bend). When the linear portion 300U-1 is directly adjacent to the linear portion 300U-2, the drain region 340 of the linear portion 300U-1 and the drain region 340 of the linear portion 300U-2 face each other and are merged into a single component. In other words, the linear portion 300U-1 and the linear portion 300U-2 can share a single drain region 340.

[0067] Continuing to refer to Figure 2 , from the perspective of the high-voltage region 100A, the transistor 300 can extend to have a concave corner 300A and a convex corner 300B. Specifically, the concave corner 300A of the transistor 300 is recessed outward away from the center of the high-voltage region 100A, while the convex corner 300B of the transistor 300 protrudes inward toward the center of the high-voltage region 100A. It should be understood that when the transistor 300 extends along the rectangular ring, the transistor 300 only has concave corners. However, when the U-shaped segment 300U is incorporated into the ring, there are convex corners 300B at the connection of the U-shaped segment 300U and other segments of the ring. Therefore, the concave corner 300A is away from the U-shaped segment 300U, and the convex corner 300B is close to the U-shaped segment 300U. According to some embodiments of the present invention, the number and curvature of the concave corner 300A and the convex corner 300B can be designed to adjust the electric field distribution, thereby improving the breakdown voltage.

[0068] Referring to Figure 3 , two structural arrangements of the high-voltage device 20 are shown arranged together. Although incorporating the U-shaped segment 300U into the ring of the transistor 300 can save the area of the overall ring on the chip, the space between adjacent U-shaped segments 300U is relatively narrow and difficult to be effectively utilized, so there is still a waste of chip area. According to some embodiments of the present invention, the U-shaped segments 300U of the two structures can face each other, such that the U-shaped segment 300U of one structure can extend into the space between the U-shaped segments 300U of the other structure. In other words, the U-shaped segments 300U of one structure and the U-shaped segments 300U of the other structure are arranged in a cross pattern, thereby achieving more effective utilization of the chip area.

[0069] Figure 4 and Figure 5According to other embodiments of the present invention, a top view of high-voltage devices 30 and 40 with various designs is shown. Compared with the high-voltage device 20 of Figure 2 , the transistors 300 of the high-voltage devices 30 and 40 may include a plurality of U-shaped segments 300U arranged continuously. For simplicity, the features of the high-voltage junction boundary component 100, isolation diode 200, transistor 300 (including source region 320, drain region 340, and gate structure 360), and the plurality of level shifters 400 are similar to those of Figure 2 shown, and the details thereof will not be repeated here.

[0070] Referring to Figure 4 , the high-voltage device 30 is shown. The plurality of U-shaped segments 300U of the high-voltage device 30 may be arranged continuously along the annular rectangular portion relative to the opposite side where the plurality of level shifters 400 are located. The plurality of U-shaped segments 300U arranged continuously may present a shape similar to a meandering snake. According to some embodiments of the present invention, arranging the plurality of U-shaped segments 300U continuously may further increase the extension dimension (e.g., trace width) of the transistor 300 while saving the overall area of the ring on the chip. As previously mentioned, each U-shaped segment 300U may include a linear portion 300U-1, a linear portion 300U-2, and an arc portion 300U-3 (not labeled for simplicity). Due to the continuous arrangement configuration, the linear portion 300U-1 of each U-shaped segment 300U may be directly adjacent to the linear portion 300U-2 of the U-shaped segment 300U on the left, and the linear portion 300U-2 of the U-shaped segment 300U may be directly adjacent to the linear portion 300U-1 of the U-shaped segment 300U on the right. In order to make the extension of the transistor 300 uninterrupted, the linear portion 300U-1 of each U-shaped segment 300U needs to be adjacent to the linear portion 300U-2 of the U-shaped segment 300U on the left, and the linear portion 300U-2 of the U-shaped segment 300U needs to be adjacent to the linear portion 300U-1 of the U-shaped segment 300U on the right.

[0071] Continuing to refer to Figure 4, when connecting adjacent U-shaped segments 300U, multiple U-shaped segments 300U' arranged in an inverted manner can be indirectly formed. In some embodiments, each U-shaped segment 300U' may include two linear portions and an arc portion connecting the two linear portions. For example, when the linear portion 300U-2 of the left U-shaped segment 300U is connected to the linear portion 300U-1 of the right U-shaped segment 300U, the linear portion 300U-2 of the left U-shaped segment 300U and the linear portion 300U-1 of the right U-shaped segment 300U can be respectively regarded as the two linear portions of the U-shaped segment 300U', and the two linear portions of the U-shaped segment 300U' are connected by the arc portion of the U-shaped segment 300U'. In some embodiments, the arc portion of the U-shaped segment 300U' is close to the high-voltage region 100A. When the two linear portions of the U-shaped segment 300U' are directly adjacent, the two source regions 320 of the two linear portions of the U-shaped segment 300U' face each other and are combined into a single component. In other words, the two linear portions of the U-shaped segment 300U' can share a single source region 320. Since the multiple U-shaped segments 300U are arranged continuously, the multiple U-shaped segments 300U' are also arranged continuously. The arc portion of each U-shaped segment 300U' forms a convex angle 300B, while the concave angle 300A is away from the U-shaped segment 300U'.

[0072] Refer to Figure 5 , a high-voltage device 40 is shown. The multiple U-shaped segments 300U of the high-voltage device 40 can be continuously arranged along the two adjacent sides where the multiple level shifters 400 are located. The multiple U-shaped segments 300U arranged continuously can present a shape similar to a meandering snake. According to some embodiments of the present invention, continuously arranging the multiple U-shaped segments 300U can further increase the extension dimension (such as the trace width) of the transistor 300 while saving the overall area of the loop on the chip. On the left side of the loop, the linear portion 300U-1 of each U-shaped segment 300U can be directly adjacent to the linear portion 300U-2 of the upper U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U can be directly adjacent to the linear portion 300U-1 of the lower U-shaped segment 300U. On the right side of the loop, the linear portion 300U-1 of each U-shaped segment 300U can be directly adjacent to the linear portion 300U-2 of the lower U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U can be directly adjacent to the linear portion 300U-1 of the upper U-shaped segment 300U. In order to make the extension of the transistor 300 uninterrupted, the linear portion 300U-1 of each U-shaped segment 300U needs to be adjacent to the linear portion 300U-2 of the adjacent U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U needs to be adjacent to the linear portion 300U-1 of the adjacent U-shaped segment 300U.

[0073] Continue to refer to Figure 5, when connecting multiple U-shaped segments 300U, multiple U-shaped segments 300U' in an inverted arrangement can be indirectly constituted. Since the multiple U-shaped segments 300U are arranged continuously, the multiple U-shaped segments 300U' are also arranged continuously. As mentioned previously, each U-shaped segment 300U' may include two linear portions, and an arc-shaped portion connecting the two linear portions. For example, when the linear portion 300U-2 of the lower U-shaped segment 300U is connected to the linear portion 300U-1 of the upper U-shaped segment 300U (on the right side of the ring), the linear portion 300U-2 of the lower U-shaped segment 300U and the linear portion 300U-1 of the upper U-shaped segment 300U can be respectively regarded as two linear portions of the U-shaped segment 300U', and the two linear portions of the U-shaped segment 300U' are connected by the arc-shaped portion of the U-shaped segment 300U'. As mentioned above, the arc portion 300U-3 of the U-shaped segment 300U is close to the low voltage region 100B, and the arc portion of the U-shaped segment 300U' is close to the high voltage region 100A. Furthermore, the linear portion 300U-1 and the linear portion 300U-2 of the U-shaped segment 300U are directly adjacent to and share a single drain region 340, and the two linear portions of the U-shaped segment 300U' are directly adjacent to and share a single source region 320. The arc portion of each U-shaped segment 300U' forms a convex corner 300B. Since the plurality of U-shaped segments 300U' crosses the two adjacent sides where the plurality of level shifters 400 are located, the transistor 300 of the high voltage device 40 does not have a concave corner 300A.

[0074] Figure 6 5 is a forward current-size graph 50 of a high-voltage device according to some embodiments of the present invention. According to some embodiments of the present invention, the forward current-size graph 50 illustrates the effect of the extended dimension (e.g., trace width) of the transistor 300 on the forward current of the transistor 300. It should be understood that the first three points (indicated by dotted lines) of the forward current-size graph 50 are actually measured data points, which are then extrapolated toward the positive horizontal axis using a linear model. As shown in the forward current-size graph 50, if the transistor 300 is to achieve a forward current of 100mA, the transistor 300 needs to have an extended dimension (e.g., trace width) of approximately 5500μm. Depending on the application and design requirements, the trace width of the transistor 300 can be designed to accommodate the desired forward current. In addition, by Figures 2 to 5 Any design with the U-shaped segment 300U (and / or the U-shaped segment 300U′) can increase the routing width of the transistor 300 while saving the area of ​​the entire ring on the chip.

[0075] The high-voltage device of the present invention integrates a bootstrap diode and a high-voltage junction boundary component arranged in a buried configuration. The transistor in the bootstrap diode can extend along the loop of the high-voltage junction boundary component to have a relatively large extension dimension (e.g., trace width). It should be understood that when the extension dimension (e.g., trace width) of the transistor is larger, the forward current of the transistor is also higher, thereby driving the bootstrap diode. In order to accommodate the required extension dimension of the transistor, the loop of the high-voltage junction boundary component must also be designed to occupy a larger chip area, resulting in waste of the chip area. The inventors found that the contour of the loop can be designed to have one or more U-shaped segments (presenting a shape similar to a hairpin bend), or a plurality of continuously arranged U-shaped segments (presenting a shape similar to a winding snake). The U-shaped segment is characterized by having an elongated contour, thus saving the space occupied by the overall loop. Furthermore, since the U-shaped segment has two correspondingly arranged linear portions, the trace width contributed by the transistor can reach at least twice the overall length of the U-shaped segment. In this way, the trace width of the transistor arranged along the loop can be increased while saving the area of the overall loop on the chip. As a result, the forward current of the transistor increases, thereby more effectively avoiding leakage current.

[0076] The above outlines the features of several embodiments so that those of ordinary skill in the art can better understand the viewpoints of the embodiments of the present invention. Those of ordinary skill in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as those introduced herein. Those of ordinary skill in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A high-voltage device, wherein, The high-voltage device includes: A high-voltage junction boundary component; and A transistor extending along an annular shape of the high-voltage junction boundary component, wherein the transistor has one or more first U-shaped segments, and each first U-shaped segment includes: A first linear portion; A second linear portion disposed corresponding to the first linear portion; and A first arcuate portion connecting the first linear portion and the second linear portion.

2. The high-voltage device according to claim 1, wherein, The first linear portion is directly adjacent to the second linear portion.

3. The high-voltage device according to claim 1, wherein, The high-voltage device further includes a plurality of level shifters located on the annular shape of the high-voltage junction boundary component.

4. The high-voltage device according to claim 3, wherein, The plurality of level shifters are spaced apart from each other.

5. The high-voltage device according to claim 3, wherein, The plurality of level shifters are spaced apart from the transistor.

6. The high-voltage device according to claim 3, wherein, The transistor and the plurality of level shifters have the same conductivity type.

7. The high-voltage device according to claim 1, wherein, The annular shape of the high-voltage junction boundary component defines a high-voltage region and a low-voltage region, inside and outside the annular shape respectively.

8. The high-voltage device according to claim 7, wherein, The high-voltage device further includes an isolation diode electrically connected to the transistor.

9. The high-voltage device according to claim 8, wherein, The isolation diode is located in the low-voltage region.

10. The high-voltage device according to claim 8, wherein, The isolation diode and the transistor form a bootstrap diode.

11. The high-voltage device according to claim 7, wherein, The extending transistor has a concave corner and a convex corner.

12. The high-voltage device according to claim 11, wherein, The concave corner is away from the plurality of first U-shaped segments, while the convex corner is close to the plurality of first U-shaped segments.

13. The high-voltage device according to claim 7, wherein, The transistor further includes: A source region disposed close to the low-voltage region; A drain region disposed close to the high-voltage region; and A gate structure disposed between the source region and the drain region.

14. The high-voltage device according to claim 13, wherein, The transistor is a laterally diffused metal oxide semiconductor transistor.

15. The high-voltage device according to claim 13, wherein, The first linear portion and the second linear portion share a single drain region.

16. The high-voltage device according to claim 13, wherein, The plurality of first U-shaped segments are arranged continuously, and the first arcuate portion of each first U-shaped segment is close to the low-voltage region.

17. The high-voltage device according to claim 16, wherein, The transistor has a plurality of second U-shaped segments, and each second U-shaped segment includes: A third linear portion; A fourth linear portion disposed corresponding to the third linear portion; and A second arcuate portion connecting the third linear portion and the fourth linear portion.

18. The high-voltage device according to claim 17, wherein, The third linear portion is directly adjacent to the fourth linear portion.

19. The high-voltage device according to claim 18, wherein, The third linear portion and the fourth linear portion share a single source region.

20. The high-voltage device according to claim 17, wherein The plurality of second U-shaped segments are arranged continuously, and the second arcuate portion of each second U-shaped segment is close to the high-voltage region.

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