Semiconductor structure
By using multiple insulating parts to fill the grooves and form gaps in the semiconductor structure, the damage problem of high-strength internal stress on the semiconductor device is solved, and higher reliability is achieved.
Patent Information
- Application Number
- CN202510420924.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2019-09-29
- Publication Date
- 2025-07-04
AI Technical Summary
In the conventional semiconductor structure, the problem of damage to the semiconductor device due to high internal stress is caused.
In the semiconductor structure, at least two insulating parts are used to fill the grooves, and a void is formed in the insulating filling layer to relieve internal stress, and the void is closed by a cover layer to achieve stress relief.
It effectively alleviates damage to adjacent semiconductor devices by high-strength internal stress of the insulating material in the groove, and improves the reliability of the semiconductor structure.
Smart Images
Figure CN120264829A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure. Background Art
[0002] For semiconductor processes, internal stress has a significant impact on the reliability of semiconductor devices. In particular, with the continuous development of semiconductor technology, the size of semiconductor devices has been continuously reduced, and the impact of internal stress in semiconductor structures on semiconductor devices has become increasingly obvious. Generally speaking, the internal stress generated by materials filled in grooves during high-temperature processes is greater, and it is more likely to affect adjacent semiconductor devices. Summary of the Invention
[0003] The purpose of the present invention is to provide a semiconductor structure to solve the problem that existing semiconductor structures are prone to damage semiconductor devices due to high-intensity internal stress.
[0004] To solve the above technical problems, the present invention provides a semiconductor structure, including:
[0005] A substrate, in which at least one semiconductor device and an interlayer dielectric layer are formed, and the interlayer dielectric layer covers the semiconductor device;
[0006] At least two interconnect structures, the interconnect structure including a contact plug and a contact pad, the contact plug penetrating the interlayer dielectric layer and extending to the semiconductor device, and the contact pad covering the top of the contact plug and extending to cover a part of the top surface of the interlayer dielectric layer; and,
[0007] A groove located between adjacent contact pads, the groove also extending downward and stopping in the interlayer dielectric layer; and,
[0008] An insulating filling layer filled in the groove, and the insulating filling layer includes at least two insulating parts.
[0009] Optionally, the insulating filling layer at least includes two first insulating parts, the two first insulating parts covering two opposite sidewalls of the groove, and the two first insulating parts defining a depression in the middle area of the groove; and the semiconductor structure further includes a covering layer, the covering layer covering the contact pad and the insulating filling layer and filling the depression.
[0010] Optionally, the bottom of the depression extends to the bottom of the groove, the covering layer filling the depression and extending to the bottom of the groove, and a cavity is further formed in the part of the covering layer corresponding to the depression.
[0011] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of a substrate. The interlayer dielectric layer includes a masking layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the masking layer. Wherein, the groove extends downward from between adjacent contact pads to the masking layer in the height direction, laterally extends from the masking layer to the sidewall structure in the width direction, and the depth value of the groove is not greater than the height value of the gate conductive layer, and the width dimension of the groove is greater than the width dimension of the gate conductive layer.
[0012] Optionally, the insulating filling layer further includes a second insulating portion covering the bottom of the groove, and a gap is formed between the second insulating portion and the first insulating portion, and the gap extends in the direction of the depression from the corner where the bottom wall and the sidewall of the groove are connected to each other.
[0013] Optionally, the bottom of the depression extends to the second insulating portion to communicate the gap with the depression, and the covering layer fills the depression and closes the opening of the first gap.
[0014] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of a substrate. The interlayer dielectric layer includes a masking layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the masking layer. Wherein, the groove extends downward from between adjacent contact pads to the masking layer in the height direction, laterally extends from the masking layer to the sidewall structure in the width direction, and the depth value of the groove is not greater than the height value of the gate conductive layer.
[0015] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of a substrate. The interlayer dielectric layer includes a masking layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the masking layer;
[0016] Wherein, the groove extends downward from between adjacent contact pads to the masking layer in the height direction, laterally extends from the masking layer to the sidewall structure in the width direction, and the depth value of the groove is greater than the height value of the gate conductive layer.
[0017] Optionally, a gap is also formed in the portion of the covering layer corresponding to the depression.
[0018] Optionally, a gap is formed between the two first insulating portions in the middle region of the groove, and the gap extends along the height direction below the depression.
[0019] Optionally, the covering layer fills the depression and closes the top opening of the gap.
[0020] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of a substrate, and a first source / drain region and a second source / drain region formed in the substrate, where the first source / drain region and the second source / drain region are respectively located on two sides of the gate conductive layer; wherein, the interconnect structures are respectively disposed on the first source / drain region and the second source / drain region, and a contact pad corresponding to the first source / drain region and a contact pad corresponding to the second source / drain region respectively extend laterally from two sides of the gate conductive layer in a direction towards the gate conductive layer.
[0021] Optionally, the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the shielding layer; wherein, a contact pad corresponding to the first source / drain region and a contact pad corresponding to the second source / drain region respectively extend laterally from two sides of the gate conductive layer to the sidewall structure.
[0022] Optionally, the groove extends laterally from the shielding layer into the sidewall structure in the width direction, and the groove extends downward from between adjacent contact pads into the shielding layer in the height direction.
[0023] In the semiconductor structure provided by the present invention, there is a groove located between adjacent contact pads, and an insulating filling layer is filled in the groove for separating adjacent contact pads. Moreover, the insulating filling layer filled in the groove is composed of at least two insulating parts. Compared with filling the groove with only one insulating material having a larger volume, filling the groove with at least two insulating parts in the present invention can more effectively relieve the internal stress of the insulating material in the groove, thereby improving the problem of damage to adjacent semiconductor devices caused by the high-intensity internal stress of the insulating material in the groove.
[0024] Furthermore, voids can be formed in the insulating material filled in the groove (for example, voids can be formed between adjacent insulating parts), so that the stress release of the insulating material can be realized by using the voids, and further reduce the internal stress of the insulating material filled in the groove. Description of the Drawings
[0025] Figure 1 It is a schematic diagram of the semiconductor structure in Embodiment 1 of the present invention;
[0026] Figure 2 It is a schematic diagram of the semiconductor structure in Embodiment 2 of the present invention;
[0027] Figure 3 It is a schematic diagram of the semiconductor structure in Embodiment 3 of the present invention;
[0028] Figure 4Schematic diagram of the semiconductor structure in Embodiment 4 of the present invention.
[0029] Among them, the reference numerals are as follows:
[0030] 100 - Substrate;
[0031] 110 - First source / drain region;
[0032] 120 - Second source / drain region;
[0033] 200 - Gate conductive layer;
[0034] 210 - First conductive layer;
[0035] 220 - Second conductive layer;
[0036] 230 - Third conductive layer;
[0037] 300 - Interconnection structure;
[0038] 310 - Contact plug;
[0039] 320 - Contact pad;
[0040] 400 - Interlayer dielectric layer;
[0041] 410 - Masking layer;
[0042] 420 - Isolation sidewall;
[0043] 430 - Isolation dielectric layer;
[0044] 500 - Insulating filling layer;
[0045] 500a - Depression;
[0046] 510 - First insulating part;
[0047] 520 - Second insulating part;
[0048] 510a - First void;
[0049] 520a - Second void;
[0050] 600 - Covering layer;
[0051] 600a - Void. Detailed implementation manners
[0052] The semiconductor structure proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.
[0053] Embodiment 1
[0054] Figure 1 is a schematic diagram of the semiconductor structure in Embodiment 1 of the present invention. As Figure 1 shown, the semiconductor structure includes:
[0055] A substrate 100, in which at least one semiconductor device and an interlayer dielectric layer 400 are formed, and the interlayer dielectric layer 400 covers the semiconductor device;
[0056] At least two interconnect structures 300, the interconnect structure 300 includes a contact plug 310 and a contact pad 320, the contact plug 310 penetrates through the interlayer dielectric layer 400 and extends to the semiconductor device, and the contact pad 320 covers the top of the contact plug 310 and extends to cover a part of the top surface of the interlayer dielectric layer 400; and,
[0057] A groove between adjacent contact pads 320 of the bit line, and the groove also extends downward and stops in the interlayer dielectric layer 400; and,
[0058] An insulating filling layer is filled in the groove, and the insulating filling layer includes at least two insulating parts (for example, Figure 1 two first insulating parts 510 shown in).
[0059] Wherein, the groove is formed by etching the interlayer dielectric layer 400 with adjacent contact pads 320 as a mask, so as to ensure that adjacent contact pads 320 are separated from each other, and avoid the problem of electrical connection between adjacent contact pads due to the residue of conductive material during the preparation of the contact pads 320.
[0060] And, in this embodiment, the insulating filling layer filled in the groove is also composed of at least two insulating parts. It should be noted that compared with filling the groove with only one larger-volume insulating part, filling the groove with multiple insulating parts will be more conducive to realizing the stress release of the insulating material in the groove. Wherein, each insulating part in the insulating filling layer can be formed of the same material, for example, the material of each insulating part includes silicon nitride or silicon oxide.
[0061] Continuing to refer to Figure 1 shown, the insulating filling layer includes at least two first insulating parts 510, and the two first insulating parts 510 cover two opposite side walls of the groove. In this embodiment, the first insulating part 510 also covers the side wall of the contact pad 320 exposed in the groove.
[0062] Further, the two first insulating portions 510 can define a recess 500a in the middle region of the groove. Specifically, the two opposite first insulating portions 510 respectively extend from the two opposite sidewalls of the groove towards the middle region of the groove and approach each other, and the recess 500a is defined by the boundaries of the two first insulating portions 510. In this embodiment, the top of the recess 500a is not higher than the top of the groove.
[0063] Continue to refer to Figure 1 As shown, the semiconductor structure further includes a covering layer 600, and the covering layer 600 covers the contact pad 320 and the insulating filling layer and fills the recess 500a.
[0064] In this embodiment, the bottom of the recess 500a also extends to the bottom of the groove, that is, the two first insulating portions 510 are separated from each other by the recess 500a located in the middle region. Based on this, the covering layer 600 fills the recess 500a and can extend to the bottom of the groove.
[0065] It should be noted that the recess 500a is located in the spatial region of the groove, and the covering layer 600 fills the recess 500a. Based on this, it can be considered that the covering layer 600 is at least partially filled in the groove. Therefore, in the groove of this embodiment, not only the insulating filling layer (including the two first insulating portions 510) is filled, but also a part of the covering layer 600 is filled, so that at least three insulating portions are used to fill the groove.
[0066] Among them, the covering layer 600 can be formed of the same material as the insulating filling layer. For example, silicon nitride can be used for both. By forming the covering layer 600 of the same material as the insulating filling layer, the insulating filling layer and the covering layer 600 have the same or similar coefficient of thermal expansion, and thus the problem of increased internal stress caused by the difference in thermal expansion between different materials can be avoided.
[0067] In an alternative solution, voids 600a can be further formed in the portion of the covering layer 600 corresponding to the recess 500a.
[0068] Specifically, the width dimension of the recess 500a is at least partially determined by the interval dimension between the two first insulating portions 510, and the first insulating portions 510 are filled in the groove, so that the interval dimension between the two first insulating portions 510 is small, and correspondingly, the width dimension of the defined recess 500a is small. Also, the recess 500a extends downward in the depth direction to the bottom of the groove, so the depth value of the recess 500a corresponds to the depth value of the groove. Thus, the aspect ratio of the recess 500a can be made large, and when the covering layer 600 fills the recess 500a, voids 600a are likely to be formed in the portion corresponding to the recess 500a.
[0069] In this embodiment, a pit is further formed in the bottom of the groove corresponding to the recess 500a, so as to further increase the depth of the recess 500a. For example, the bottom of the recess 500a can be made lower than the bottom of the first insulating portion 510. In this way, it is equivalent to increasing the aspect ratio of the recess 500a, which will be more conducive to forming the voids 600a in the covering layer 600.
[0070] It should be noted that since voids are formed in the insulating material corresponding to the groove (that is, voids 600a are formed in the portion of the covering layer 600 corresponding to the groove), the voids 600a can be used to further release the stress of the insulating material filled in the groove. For example, when a high-temperature process is performed on the semiconductor structure, the insulating material in the groove can use the voids 600a to release stress, avoiding the problem that the insulating material in the groove damages other components due to high-intensity stress squeezing other components.
[0071] In particular, when the groove is formed directly above the semiconductor device, the high-intensity internal stress of the insulating material filled in the groove may damage the semiconductor device. As Figure 1 shown, in this embodiment, the insulating filling layer and the covering layer 600 filled in the groove are formed directly above the semiconductor device.
[0072] Continuing to refer to Figure 1 shown, in this embodiment, the semiconductor device includes, for example, a transistor. The transistor includes a gate conductive layer 200 formed on the top surface of the substrate 100, and a first source / drain region 110 and a second source / drain region 120 formed in the substrate 100. The first source / drain region 110 and the second source / drain region 120 are respectively located on both sides of the gate conductive layer 200.
[0073] In this embodiment, the gate conductive layer 200 includes a first conductive layer 210, a second conductive layer 220, and a third conductive layer 230 which are stacked. Among them, the material of the first conductive layer 210 includes, for example, polysilicon, the material of the second conductive layer 220 includes, for example, titanium nitride, and the material of the third conductive layer 230 includes, for example, tungsten.
[0074] Among them, the interconnect structure 300 is respectively disposed on the first source / drain region 110 and the second source / drain region 120. Specifically, the contact plug 310 corresponding to the first source / drain region and the contact plug 310 corresponding to the second source / drain region are respectively formed on both sides of the gate conductive layer 200 and vertically extend to the first source / drain region 110 and the second source / drain region 120 of the substrate 100 to be electrically connected to the first source / drain region 110 and the second source / drain region 120. And, the contact pad 320 corresponding to the first source / drain region and the contact pad 320 corresponding to the second source / drain region respectively extend laterally from both sides of the gate conductive layer 200 in the direction towards the gate conductive layer 200.
[0075] Furthermore, the interlayer dielectric layer 400 includes a shielding layer 410 covering the top surface of the gate conductive layer 200, and an isolation sidewall 420 covering the sidewalls of the gate conductive layer 200 and the sidewalls of the shielding layer 410.
[0076] Specifically, the isolation sidewall 420 is, for example, a stacked structure that sequentially covers the gate conductive layer 200. In this embodiment, the isolation sidewall 420 includes a first isolation layer, a second isolation layer, and a third isolation layer that sequentially cover the gate conductive layer 200 from the inside to the outside. Among them, the first isolation layer and the third isolation layer can be formed of the same material, for example, both include silicon oxide, and the material of the second isolation layer includes, for example, silicon nitride, thereby forming the isolation sidewall 420 of the ONO structure. And, the material of the shielding layer 410 can also include silicon nitride.
[0077] In this embodiment, the two contact pads 320 corresponding to the first source / drain region 110 and the second source / drain region 120 respectively extend laterally from both sides of the gate conductive layer 200 in the direction towards the gate conductive layer 200 to above the isolation sidewall 420. Based on this, the groove located between adjacent contact pads 320 extends laterally in the width direction from the shielding layer 410 to the isolation sidewall 420. In this embodiment, the groove extends laterally in the width direction to the second isolation layer of the isolation sidewall 420, correspondingly making the width dimension of the groove larger than the width dimension of the gate conductive layer 220.
[0078] Further, the groove extends downward from between adjacent contact pads 320 in the height direction to the masking layer 410 and the isolation sidewall 420. Further, the depth value H2 of the groove may not be greater than the height value H1 of the semiconductor device above the top surface of the substrate. In this embodiment, the depth value H2 of the groove is not greater than the height value H1 of the gate conductive layer 200.
[0079] As described above, the width dimension of the groove is greater than the width dimension of the gate conductive layer 200. Therefore, it can be considered that in this embodiment, the depth-to-width ratio of the groove is small, so that two mutually separated first insulating portions 510 can be formed in the groove, and the two first insulating portions 510 can be mutually separated by a relatively large recess 500a. In this embodiment, the bottom of the recess 500a further extends downward into the masking layer 410, so that the portion of the masking layer 410 corresponding to the recess 500a sinks more.
[0080] Furthermore, the outer edge boundary of the first insulating portion 510 correspondingly extends beyond the outer edge boundary of the gate conductive layer 200 and covers the sidewalls of the contact pad 320 and the isolation sidewall 410 exposed in the groove.
[0081] Continue to refer to Figure 1 As shown, the interlayer dielectric layer 400 further includes an isolation dielectric layer 430. The isolation dielectric layer 430 is formed on the periphery of the isolation sidewall 420 away from the gate conductive layer 200, and the conductive plug 310 penetrates the isolation dielectric layer 430.
[0082] In addition, it should be noted that in this embodiment, a void 600a is formed in the portion of the covering layer 600 corresponding to the recess 500a. However, in other embodiments, a void may also be formed between the covering layer 600 and the insulating filling layer. For example, a void may also be formed between the covering layer 600 and the first insulating portion 510.
[0083] Embodiment 2
[0084] The difference from Embodiment 1 is that in this embodiment, the insulating filling layer further includes a second insulating portion covering the bottom of the groove.
[0085] Figure 2 It is a schematic diagram of the semiconductor structure in Embodiment 2 of the present invention. As Figure 2 shown, in this embodiment, the insulating filling layer 500 includes two first insulating portions 510 and a second insulating portion 520. The first insulating portion 510 covers the sidewalls of the groove, and the second insulating portion 520 covers the bottom of the groove.
[0086] Further, a gap (i.e., the first gap 510a) is formed between the second insulating portion 520 and the first insulating portion 510. The first gap 510a located between the first insulating portion 510 and the second insulating portion 520 extends from the corner where the bottom wall and the side wall of the groove are connected to the direction of the recess 500a. Among them, the first gap 510a extends obliquely upward from the corner, for example. In this embodiment, the first gap 510a is formed between the two first insulating portions 510 and the second insulating portion 520 to relieve the internal stress of the insulating filling layer 500.
[0087] Continue to refer to Figure 2 As shown, the bottom of the recess 500a further extends downward into the second insulating portion 520, that is, pits are formed in the portion of the second insulating portion 520 corresponding to the two first insulating portions 510. In this way, the first gap 510a and the recess 500a can be communicated with each other. In this embodiment, the first gap 510a communicates with the recess 500a on the side wall of the recess 500a, that is, the opening position of the first gap 510a exposed in the recess 500a is higher than the bottom position of the recess 500a.
[0088] Among them, the opening size of the recess 500a is larger than the opening size of the first gap 510a. And, the covering layer 600 fills the recess 500a and closes the opening of the first gap 510a, so that the first gap 510a between the first insulating portion 510 and the second insulating portion 520 can be retained.
[0089] It should be noted that in this embodiment, the groove extends laterally from the shielding layer 410 to the first isolation layer of the isolation sidewall 420 in the width direction. And, the depth value H2 of the groove is not greater than the height value H1 of the gate conductive layer 200, and the recess 500a does not extend to the bottom of the groove, correspondingly making the depth value of the recess 500a smaller. Therefore, compared with the first embodiment, the depth-width ratio of the recess 500a in this embodiment is smaller. At this time, for example, no gap is formed in the portion of the covering layer 600 corresponding to the recess 500a.
[0090] Embodiment Three
[0091] The difference from Embodiment Two is that in this embodiment, the depth value H2 of the groove is greater than the height value H1 of the gate conductive layer, so that the groove has a larger depth-width ratio and can correspondingly increase the depth-width ratio of the recess, and further make gaps also formed in the portion of the covering layer corresponding to the recess.
[0092] Figure 3Schematic diagram of the semiconductor structure in Embodiment 3 of the present invention. As Figure 3 shown, in this embodiment, the groove extends downward in the height direction and has a lower depth in the shielding layer 410, so that the depth value H2 of the groove is greater than the height value H1 of the gate conductive layer, and thus the groove has a larger aspect ratio.
[0093] Correspondingly, the recess 500a between the two first insulating portions 510 can have a larger aspect ratio. In this way, a void 600a can be formed in the portion of the covering layer 600 filled in the recess 500a. Similar to Embodiment 1, the bottom of the recess 500a can further extend into the second insulating portion 520, which is beneficial to further increase the aspect ratio of the recess 500a.
[0094] That is, in this embodiment, for a groove with a large aspect ratio, the filled insulating material can include two first insulating portions 510, a second insulating portion 520, and a part of the covering layer 600. A void 510a is formed between the adjacent first insulating portion 510 and the second insulating portion 520, and a void 600a is also formed in the portion of the covering layer 600 filled in the groove, so as to further improve the stress resistance of the insulating material filled in the groove.
[0095] Embodiment 4
[0096] The difference from Embodiment 3 is that in this embodiment, the recess does not extend into the second insulating portion, and the two first insulating portions are close to each other in the middle region of the groove and a void is also formed.
[0097] Figure 4 Schematic diagram of the semiconductor structure in Embodiment 4 of the present invention. As Figure 4 shown, a void (i.e., the second void 520a) is also formed between the two first insulating portions 510, and the second void 520a located between the two first insulating portions 510 extends along the height direction below the recess 500a. That is, the top of the second void 520a communicates with the recess 500a.
[0098] In this embodiment, the void (i.e., the first void 510a) between the first insulating portion 510 and the second insulating portion 520 extends obliquely upward from the corner of the groove and communicates with the bottom of the second void 520a.
[0099] Continue to refer to Figure 4As shown, the covering layer 600 fills the recess 500a and closes the top opening of the second void 520a. That is, the second void 520a located between the two first insulating portions 510 and the first void 510a located between the first insulating portion 510 and the second insulating portion 520 can both be retained for stress relief of the insulating material filled in the groove.
[0100] It should be noted that, compared with the third embodiment, the recess 500a in this embodiment does not extend downward to the second insulating portion 520, so that the recess 500a has a smaller depth-to-width ratio, and thus no voids are formed in the portion of the covering layer 600 corresponding to the recess 600a.
[0101] In summary, in the semiconductor structure as described above, the insulating filling layer filled in the groove includes at least two insulating portions. Compared with filling the groove with only one relatively large insulating material, filling the groove with multiple insulating portions is more conducive to stress relief of the insulating material filled in the groove, thereby alleviating the problem that the insulating material filled in the groove damages adjacent semiconductor devices due to high-intensity internal stress.
[0102] Furthermore, voids can also be formed in the insulating material filled in the groove (for example, voids are also formed between adjacent insulating portions). In this way, the stress of each insulating portion can be further relieved by using the voids, and thus the internal stress of the insulating material in the groove can be more effectively alleviated.
[0103] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.
[0104] It should also be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.
[0105] It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0106] It should also be recognized that the terminology described herein is only used to describe specific embodiments and is not intended to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, a reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" definition unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.
Claims
1. A semiconductor structure, characterized in that, Comprising: A substrate; A gate conductive layer located on the top surface of the substrate; A masking layer covering the top surface of the gate conductive layer; A sidewall structure covering the sidewalls of the gate conductive layer and the sidewalls of the masking layer; An interconnect structure including a contact plug and a contact pad, the contact plug being located on a side of the sidewall structure away from the gate conductive layer and extending to the substrate, and the contact pad covering the top of the contact plug; A groove located on a side of the contact pad close to the gate conductive layer, the groove extending downward in the height direction into the masking layer, and the groove extending laterally from the masking layer into the sidewall structure in the width direction; and An insulating filling layer filling the groove, and the insulating filling layer includes at least two insulating portions, and the at least two insulating portions are in contact with both the masking layer and the sidewall structure simultaneously.
2. The semiconductor structure according to claim 1, wherein, The insulating filling layer includes at least two first insulating portions covering opposite sidewalls of the groove, and the two first insulating portions define a depression in a middle region of the groove; And, the semiconductor structure further includes a covering layer covering the contact pad and the insulating filling layer and filling the depression.
3. The semiconductor structure according to claim 2, wherein The bottom of the depression extends to the bottom of the groove, the covering layer fills the depression and extends to the bottom of the groove, and voids are formed in a portion of the covering layer corresponding to the depression.
4. The semiconductor structure according to claim 2, wherein A second void is formed between the two first insulating portions in the middle region of the groove, and the second void extends along the height direction below the depression.
5. The semiconductor structure according to claim 2, wherein The width dimension of the groove is greater than the width dimension of the gate conductive layer, the depth value of the groove is not greater than the height value of the gate conductive layer, and voids are not formed in a portion of the covering layer corresponding to the depression.
6. The semiconductor structure according to claim 1, wherein, The semiconductor structure includes at least two of the interconnect structures, the groove is located between adjacent contact pads, and the gate conductive layer is located between adjacent two contact plugs.
7. The semiconductor structure according to claim 1, wherein At least one semiconductor device is formed in the substrate, the semiconductor device includes the gate conductive layer and a first source / drain region and a second source / drain region formed in the substrate, the interconnect structures are respectively disposed on the first source / drain region and the second source / drain region, and the contact pad corresponding to the first source / drain region and the contact pad corresponding to the second source / drain region respectively extend laterally from both sides of the gate conductive layer in a direction toward the gate conductive layer above the sidewall structure.
8. A semiconductor structure, characterized in that, Comprising: A substrate; A gate conductive layer located on the top surface of the substrate; A masking layer covering the top surface of the gate conductive layer; A sidewall structure covering the sidewalls of the gate conductive layer and the sidewalls of the masking layer; At least two interconnect structures respectively located on both sides of the gate conductive layer, the interconnect structure includes a contact plug and a contact pad, the contact plug is located on a side of the sidewall structure away from the gate conductive layer and extends to the substrate, and the contact pad covers the top of the contact plug; A groove located between the contact pads of the at least two interconnect structures; And An insulating filling layer is filled in the groove, and the insulating filling layer includes at least two first insulating parts and one second insulating part. The first insulating parts cover the side walls of the groove, and the second insulating part covers the bottom of the groove. The two first insulating parts define a depression in the middle area of the groove, and a first gap is formed between the second insulating part and the first insulating parts. The first gap extends from the corner where the bottom wall and the side wall of the groove are connected to the direction of the depression.
9. The semiconductor structure according to claim 8, wherein, The semiconductor structure further includes a covering layer that covers the contact pad and the insulating filling layer and fills the depression.
10. The semiconductor structure as described in claim 9, characterized in that, The depth value of the groove is greater than the height value of the gate conductive layer, and a gap is also formed in the part of the covering layer corresponding to the depression.
11. The semiconductor structure according to claim 8, wherein The bottom of the depression extends to the second insulating part, so that the first gap communicates with the depression, and the covering layer fills the depression and closes the opening of the first gap.
12. The semiconductor structure according to claim 8, wherein, A second gap is formed between the two first insulating parts in the middle area of the groove. The second gap extends along the height direction below the depression, and the covering layer fills the depression and closes the top opening of the second gap.
13. The semiconductor structure according to claim 8, wherein, The groove extends downward from between adjacent contact pads to the covering layer in the height direction, and extends laterally from the covering layer to the sidewall structure in the width direction. The depth value of the groove is not greater than the height value of the gate conductive layer, and the width dimension of the groove is greater than the width dimension of the gate conductive layer.
14. The semiconductor structure according to claim 13, wherein No gap is formed in the part of the covering layer corresponding to the depression.
15. The semiconductor structure according to claim 8, wherein The semiconductor device includes the gate conductive layer, and a first source / drain region and a second source / drain region formed in the substrate. The first source / drain region and the second source / drain region are respectively located on both sides of the gate conductive layer. Interconnection structures are respectively provided on the first source / drain region and the second source / drain region. The contact pad corresponding to the first source / drain region and the contact pad corresponding to the second source / drain region respectively extend laterally from both sides of the gate conductive layer in the direction towards the gate conductive layer to above the sidewall structure.
16. A semiconductor structure, characterized in that, Comprising: A substrate; A gate conductive layer located on the top surface of the substrate. The gate conductive layer has a first side wall and a corresponding second side wall; A covering layer covering the top surface of the gate conductive layer. The covering layer has a third side wall and a corresponding fourth side wall; A sidewall structure covering the side walls of the gate conductive layer and the side walls of the covering layer; At least two interconnection structures respectively located on both sides of the gate conductive layer. The interconnection structure includes a contact plug and a contact pad. The contact plug is located on the side of the sidewall structure away from the gate conductive layer and extends to the substrate. The bottommost part of the contact plug contacts the substrate, and the contact pad covers the top of the contact plug; The insulating filling layer includes a first insulating portion and a second insulating portion, wherein the second insulating portion is located between the first insulating portions and completely covers the top of the shielding layer, the first insulating portion is directly in contact with the side walls of two adjacent contact pads at the same time, and the second insulating portion is between the shielding layer and the first insulating portion.
17. The semiconductor structure according to claim 16, wherein, Further included are: A groove, located on the side of the contact pad close to the gate conductive layer, the groove extends downward in the height direction into the shielding layer, and the groove extends laterally from the shielding layer into the sidewall structure in the width direction; the insulating filling layer is located in the groove.
18. A semiconductor structure, characterized in that, Comprising: A substrate; A gate conductive layer, located on the top surface of the substrate, the gate conductive layer has a first side wall and a corresponding second side wall; A shielding layer, covering the top surface of the gate conductive layer, the shielding layer has a third side wall and a corresponding fourth side wall; A sidewall structure, covering the side walls of the gate conductive layer and the side walls of the shielding layer; At least two interconnect structures, respectively located on both sides of the gate conductive layer, the interconnect structure includes a contact plug and a contact pad, the contact plug is located on the side of the sidewall structure away from the gate conductive layer and extends to the substrate, the bottommost part of the contact plug contacts the substrate, and the contact pad covers the top of the contact plug; And An insulating filling layer, located between the at least two interconnect structures, isolating two adjacent interconnect structures; Wherein the projection of the side wall of the contact pad close to the gate conductive layer in the extending direction of the contact plug is separated from the gate conductive layer and does not intersect.
19. The semiconductor structure according to claim 18, wherein, Further included are: A groove, located on the side of the contact pad close to the gate conductive layer, the groove extends downward in the height direction into the shielding layer, and the groove extends laterally from the shielding layer into the sidewall structure in the width direction; the insulating filling layer is located in the groove.
20. A semiconductor structure, characterized in that, Comprising: A substrate; A gate conductive layer, located on the top surface of the substrate, the gate conductive layer has a first side wall and a corresponding second side wall; A shielding layer, covering the top surface of the gate conductive layer, the shielding layer has a third side wall and a corresponding fourth side wall; A sidewall structure, covering the side walls of the gate conductive layer and the side walls of the shielding layer; At least two interconnect structures, respectively located on both sides of the gate conductive layer, the interconnect structure includes a contact plug and a contact pad, the contact plug is located on the side of the sidewall structure away from the gate conductive layer and extends to the substrate, the bottommost part of the contact plug contacts the substrate, and the contact pad covers the top of the contact plug; And An insulating filling layer, including a first insulating portion, the first insulating portion has a first surface in contact with the side wall of the contact pad, a second surface in contact with the side wall structure, and a third surface in contact with the top of the shielding layer, and the first surface, the second surface and the third surface are connected together.
21. The semiconductor structure according to claim 20, wherein, Further included are: A groove, located on a side of the contact pad close to the gate conductive layer, extends downward in the height direction into the masking layer, and extends laterally from the masking layer into the sidewall structure in the width direction; an insulating filling layer is located in the groove.
22. A semiconductor structure, characterized in that, Comprising: A substrate; A gate conductive layer, located on the top surface of the substrate, the gate conductive layer having a first sidewall and a corresponding second sidewall; A masking layer, covering the top surface of the gate conductive layer, the masking layer having a third sidewall and a corresponding fourth sidewall; A sidewall structure, covering the sidewalls of the gate conductive layer and the sidewalls of the masking layer; At least two interconnect structures, respectively located on two sides of the gate conductive layer, the interconnect structure comprising a contact plug and a contact pad, the contact plug being located on a side of the sidewall structure away from the gate conductive layer and extending to the substrate, and the contact pad covering the top of the contact plug; And An insulating filling layer, located between the at least two interconnect structures, comprising a first insulating portion and a second insulating portion, wherein the second insulating portion is located between the first insulating portions and the first insulating portions are in direct contact with two sidewalls corresponding to the sidewall structure at the same time, and the second insulating portion is in direct contact with the masking layer.
23. The semiconductor structure according to claim 22, wherein Further comprising: A groove, located on a side of the contact pad close to the gate conductive layer, extends downward in the height direction into the masking layer, and extends laterally from the masking layer into the sidewall structure in the width direction; an insulating filling layer is located in the groove.