Semiconductor device and power equipment

Abstract

The semiconductor device and the power equipment comprise a driving circuit with an N-type field effect transistor and a P-type field effect transistor, the N-type field effect transistor comprises a 4H-SiC substrate, a first 3C-SiC layer on the carbon surface of the N-type field effect transistor, a first grid electrode located on the first 3C-SiC layer and far away from the 4H-SiC substrate, a first electrode and a second electrode, and a second grid electrode located on the second 3C-SiC layer and far away from the 4H-SiC substrate. The P-type field effect transistor comprises a 4H-SiC substrate, a second 3C-SiC layer on the silicon surface of the 4H-SiC substrate, a second grid located on the second 3C-SiC layer and far away from the 4H-SiC substrate, a third electrode and a fourth electrode; the interconnection columns penetrate through the 4H-SiC substrate and are insulated from the first 3C-SiC layer, the second 3C-SiC layer and the 4H-SiC substrate, the interconnection columns comprise the first interconnection column, the second interconnection column and the third interconnection column, the first interconnection column is connected with the first grid electrode and the second grid electrode, the second interconnection column is connected with the first electrode and the third electrode, the third interconnection column is connected with the fourth electrode and one end of the constant voltage source, and the other end of the constant voltage source and the second electrode are grounded.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor device and a power device. Background Art

[0002] Power devices need to be driven by a drive circuit (also known as a drive buffer). In related technologies, the drive circuit is integrated on one side of the substrate, resulting in a dense layout of the drive circuit and a relatively high process difficulty. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a power device to solve the technical problems of a dense layout of the drive circuit and a high process difficulty.

[0004] The semiconductor device and the power device provided by the embodiments of the present disclosure are specifically as follows: On the one hand, an embodiment of the present disclosure provides a semiconductor device, including: A drive circuit, where the drive circuit includes an N-type field effect transistor and a P-type field effect transistor arranged at intervals. Among them, the N-type field effect transistor includes a 4H-SiC substrate, a first 3C-SiC layer located on the side of the carbon surface of the 4H-SiC substrate, and a first gate, a first electrode, and a second electrode located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The P-type field effect transistor includes the 4H-SiC substrate, a second 3C-SiC layer located on the side of the silicon surface of the 4H-SiC substrate, and a second gate, a third electrode, and a fourth electrode located on the side of the second 3C-SiC layer away from the 4H-SiC substrate; Interconnection posts, penetrating the 4H-SiC substrate, and the interconnection posts are insulated from the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer. The interconnection posts include a first interconnection post, a second interconnection post, and a third interconnection post. The first interconnection post connects the first gate and the second gate. The second interconnection post connects the first electrode and the third electrode. The third interconnection post connects the fourth electrode and one end of a constant voltage source, and the other end of the constant voltage source and the second electrode are both grounded.

[0005] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, a first isolation structure and a second isolation structure are further included; The first 3C-SiC layer is also located in the area where the P-type field effect transistor is located. The first isolation structure penetrates the first 3C-SiC layer in the area where the P-type field effect transistor is located and extends into the 4H-SiC substrate; The second 3C-SiC layer is also located in the region where the N-type field effect transistor is located, and the second isolation structure penetrates through the second 3C-SiC layer in the region where the N-type field effect transistor is located and extends into the 4H-SiC substrate.

[0006] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the first isolation structure is a groove structure or a P-type doping structure, and the second isolation structure is a groove structure or an N-type doping structure.

[0007] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the interconnection pillar specifically penetrates through the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer.

[0008] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, it further includes: a seed layer, a barrier layer, and a dielectric layer that penetrate through the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer, wherein the seed layer is in contact with the interconnection pillar, the dielectric layer is in contact with the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer, and the barrier layer is located between the seed layer and the dielectric layer.

[0009] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode; one of the third electrode and the fourth electrode is a source electrode, and the other is a drain electrode.

[0010] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the thicknesses of both the first 3C-SiC layer and the second 3C-SiC layer are 25 nm to 30 nm.

[0011] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the drive circuit includes a first-stage drive circuit, the first-stage drive circuit includes the N-type field effect transistor and the P-type field effect transistor, the first gate is a pulse gate signal input terminal, and the first electrode is a drive signal output terminal.

[0012] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the drive circuit includes a first-stage drive circuit and a second-stage drive circuit, and the first-stage drive circuit and the second-stage drive circuit respectively include the N-type field effect transistor and the P-type field effect transistor; The first gate of the first-stage driving circuit is a pulsed gate signal input terminal. The first gate of the second-stage driving circuit is electrically connected to the first electrode of the first-stage driving circuit, and the first electrode of the second-stage driving circuit is a driving signal output terminal.

[0013] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, there is further a power device disposed at an interval from the driving circuit. The power device includes the 4H-SiC substrate, the first 3C-SiC layer, the second 3C-SiC layer, and a gate, a source, and a drain located on a side of the first 3C-SiC layer away from the 4H-SiC substrate. The gate of the power device is electrically connected to the driving signal output terminal, the source of the power device is grounded, and the drain of the power device is electrically connected to a load.

[0014] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, there is further a third isolation structure located between the region where the power device is located and the region where the driving circuit is located. The third isolation structure penetrates the first 3C-SiC layer and extends into the 4H-SiC substrate.

[0015] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, the third isolation structure is a groove structure or a P-type doping structure.

[0016] On the other hand, the embodiments of the present disclosure provide a power device including the semiconductor device provided in the embodiments of the present disclosure.

[0017] The beneficial effects of the present disclosure are as follows: The semiconductor device and power device provided by the embodiments of the present disclosure include: a driving circuit, which includes an N-type field-effect transistor and a P-type field-effect transistor arranged at intervals. Among them, the N-type field-effect transistor includes a 4H-SiC substrate, a first 3C-SiC layer located on the side where the carbon surface of the 4H-SiC substrate is located, and a first gate, a first electrode, and a second electrode located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The P-type field-effect transistor includes a 4H-SiC substrate, a second 3C-SiC layer located on the side where the silicon surface of the 4H-SiC substrate is located, and a second gate, a third electrode, and a fourth electrode located on the side of the second 3C-SiC layer away from the 4H-SiC substrate; an interconnecting column, which penetrates the 4H-SiC substrate. The interconnecting column is insulated from the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer. The interconnecting column includes a first interconnecting column, a second interconnecting column, and a third interconnecting column. The first interconnecting column connects the first gate and the second gate. The second interconnecting column connects the first electrode and the third electrode. The third interconnecting column connects the fourth electrode and one end of a constant voltage source. The other end of the constant voltage source and the second electrode are both grounded. In the present disclosure, the components of the driving circuit are arranged on both sides of the 4H-SiC substrate, and the electrical connection of the components on both sides is realized by using the interconnecting column, which simplifies the layout on one side of the 4H-SiC substrate and reduces the process difficulty. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 2 It is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 3 It is a SPICE current simulation schematic diagram of a single-stage driving circuit provided by an embodiment of the present disclosure; Figure 4 For Figure 3 The square-wave voltage pulse signal input by the V2 signal generator in, and the curve of the output voltage waveform of the driving circuit changing with time; Figure 5 For Figure 3 The double-pulse test simulation schematic diagram of; Figure 6 For Figure 3 The turn-off curve of the power device in at time t~40 μs; Figure 7 It is a SPICE current simulation schematic diagram of a double-stage driving circuit provided by an embodiment of the present disclosure; Figure 8 For Figure 7 The double-pulse test simulation schematic diagram of; Figure 9 For Figure 7The turn-off curve of the power device in [it] at time t~40 μs; Figure 10 is Figure 2 A schematic structural diagram of the semiconductor device shown during the manufacturing process; Figure 11 is Figure 2 Another schematic structural diagram of the semiconductor device shown during the manufacturing process; Figure 12 is Figure 2 Another schematic structural diagram of the semiconductor device shown during the manufacturing process. Specific embodiments

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that the embodiments described in the present disclosure should not be construed as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features; the sharp corners illustrated may be rounded, etc. Also, the same or similar reference numerals throughout indicate the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted in the present disclosure.

[0020] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "comprising" or "including" and the like mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "inner", "outer", "upper", "lower", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0021] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer can be directly on one side of the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on" another element or layer or "directly connected to" another element or layer, there are no intermediate elements or layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] Figure 1 A schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure is given. As Figure 1 shown, the semiconductor device provided by the embodiment of the present disclosure may include: A drive circuit DB, the drive circuit DB includes an N-type field effect transistor NFET and a P-type field effect transistor PFET arranged at intervals. Among them, the N-type field effect transistor NFET includes a 4H-SiC substrate 101, a first 3C-SiC layer 102 located on the side where the carbon surface ( ) of the 4H-SiC substrate 101 is located, and a first gate G1, a first electrode S1, and a second electrode D1 located on the side of the first 3C-SiC layer 102 away from the 4H-SiC substrate 101. Due to the spontaneous polarization of the 4H-SiC substrate 101, a two-dimensional electron gas (2DEG) can be induced at the interface between the first 3C-SiC layer 102 and the 4H-SiC substrate 101; the P-type field effect transistor PFET includes a 4H-SiC substrate 101, a second 3C-SiC layer 103 located on the side where the silicon surface (0001) of the 4H-SiC substrate 101 is located, and a second gate G2, a third electrode S2, and a fourth electrode D2 located on the side of the second 3C-SiC layer 103 away from the 4H-SiC substrate 101. Due to the spontaneous polarization of the 4H-SiC substrate 101, a two-dimensional hole gas (2DHG) can be induced at the interface between the second 3C-SiC layer 103 and the 4H-SiC substrate 101.

[0023] In some embodiments, the first 3C-SiC layer 102 can be N-type lightly doped (doping concentration < 10 15 cm -3 ) or intrinsic 3C-SiC, and the second 3C-SiC layer 103 can be P-type lightly doped (doping concentration < 10 15 cm -3), or intrinsic 3C-SiC; the thicknesses of the first 3C-SiC layer 102 and the second 3C-SiC layer 103 can both be 25 nm to 30 nm, such as 26 nm, 27 nm, 28 nm, 29 nm, etc., which is beneficial for gate control. One of the first electrode S1 and the second electrode D1 is the source electrode, and the other is the drain electrode; one of the third electrode S2 and the fourth electrode D2 is the source electrode, and the other is the drain electrode; for example, the first electrode S1 is the source electrode, the second electrode D1 is the drain electrode, the third electrode S2 is the source electrode, and the fourth electrode D2 is the drain electrode; or, the first electrode S1 is the source electrode, the second electrode D1 is the drain electrode, the third electrode S2 is the drain electrode, and the fourth electrode D2 is the source electrode; or, the first electrode S1 is the drain electrode, the second electrode D1 is the source electrode, the third electrode S2 is the source electrode, and the fourth electrode D2 is the drain electrode; or, the first electrode S1 is the drain electrode, the second electrode D1 is the source electrode, the third electrode S2 is the drain electrode, and the fourth electrode D2 is the source electrode.

[0024] The interconnecting posts 104 penetrate through the 4H-SiC substrate 101. The interconnecting posts 104 are insulated from the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103. The interconnecting posts 104 include a first interconnecting post 1041, a second interconnecting post 1042, and a third interconnecting post 1043. The first interconnecting post 1041 connects the first gate G1 and the second gate G2. The second interconnecting post 1042 connects the first electrode S1 and the third electrode S2. The third interconnecting post 1043 connects the fourth electrode D2 and one end of a constant voltage source V1. The other end of the constant voltage source V1 and the second electrode D1 are both grounded.

[0025] As can be seen from the above, in the present disclosure, the N-type field-effect transistor NFET and the P-type field-effect transistor PFET of the driving circuit DB are separately arranged on both sides of the carbon surface and the silicon surface of the 4H-SiC substrate 101, and the electrical connection between the N-type field-effect transistor NFET and the P-type field-effect transistor PFET is realized by using the interconnecting posts 104, thereby simplifying the layout on one side of the 4H-SiC substrate 101 and reducing the process difficulty.

[0026] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, such as Figure 1As shown, the first 3C-SiC layer 102 can be located in the regions of both the N-type field-effect transistor and the P-type field-effect transistor PFET, and the second 3C-SiC layer 103 can also be located in the regions of both the N-type field-effect transistor and the P-type field-effect transistor PFET. In this way, the first 3C-SiC layer 102 and the second 3C-SiC layer 103 can be prepared by an epitaxial process without the need to remove the first 3C-SiC layer 102 in the region of the P-type field-effect transistor PFET and the second 3C-SiC layer 103 in the region of the N-type field-effect transistor through an etching process, simplifying the manufacturing process of the first 3C-SiC layer 102 and the second 3C-SiC layer 103. In this case, a first isolation structure 105 and a second isolation structure 106 can be provided. The first isolation structure 105 penetrates the first 3C-SiC layer 102 in the region of the P-type field-effect transistor PFET and extends into the 4H-SiC substrate 101, thereby truncating the two-dimensional electron gas (2DEG) interconnection between the region of the P-type field-effect transistor PFET and the region of the N-type field-effect transistor NFET. The second isolation structure 106 penetrates the second 3C-SiC layer 103 in the region of the N-type field-effect transistor NFET and extends into the 4H-SiC substrate 101, thereby truncating the two-dimensional hole gas (2DHG) interconnection between the region of the P-type field-effect transistor PFET and the region of the N-type field-effect transistor NFET, ensuring that the P-type field-effect transistor PFET and the N-type field-effect transistor NFET do not interfere with each other.

[0027] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the first isolation structure 105 and the second isolation structure 106 can be prepared by an ion implantation or an etching process. Specifically, P-type doping atoms can be implanted to form the first isolation structure 105, and N-type doping atoms can be implanted to form the second isolation structure 106. In other words, the first isolation structure 105 is a P-type doping structure, and the second isolation structure 106 is an N-type doping structure. In the case of using an etching process to prepare the first isolation structure 105 and the second isolation structure 106, both the first isolation structure 105 and the second isolation structure 106 are groove structures.

[0028] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, when the first 3C-SiC layer 102 and the second 3C-SiC layer 103 are prepared by an epitaxial process, the first 3C-SiC layer 102 and the second 3C-SiC layer 103 will exist in the region of the interconnection column 104, as Figure 1 shown. To effectively conduct the P-type field-effect transistor PFET and the N-type field-effect transistor NFET, the interconnection column 104 needs to penetrate the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103.

[0029] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, it may further include: a seed layer, a barrier layer, and a dielectric layer that penetrate through the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103, wherein the seed layer is in contact with the interconnect post 104, the dielectric layer is in contact with the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103, and the barrier layer is located between the seed layer and the dielectric layer. Among them, the dielectric layer can achieve mutual insulation among the interconnect post 104, the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103, the barrier layer can prevent the metal of the seed layer from diffusing into the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103, the seed layer can be copper metal, and the seed layer plays a conductive role in the electroplating filling process of the interconnect post 104, and can also provide crystal nuclei (such as copper crystal nuclei) to obtain more uniform crystallization.

[0030] In some embodiments, Figure 2 Another structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure is given. As Figure 2 shown, the semiconductor device of the present disclosure may further include a power device PD spaced apart from the drive circuit DB. The power device PD includes a 4H-SiC substrate 101, a first 3C-SiC layer 102, a second 3C-SiC layer 103, and a gate G3, a source S3, and a drain D3 located on a side of the first 3C-SiC layer 102 away from the 4H-SiC substrate 101. The gate G3 of the power device PD is electrically connected to a drive signal output terminal (such as the first electrode S1 of an N-type field effect transistor NFET), the source S3 of the power device PD can be grounded, and the drain D3 of the power device PD can be electrically connected to a load (such as Figure 3 the L1 inductor shown).

[0031] In a main drive module of a new energy vehicle, for example, the drive circuit DB and the power device PD are in a spatially separated positional relationship. A long connection line is required between the drive circuit DB and the power device PD to achieve electrical connection, resulting in a relatively large parasitic inductance in the gate-source loop formed by the drive circuit DB and the power device PD. The relatively high parasitic inductance in the gate-source loop will cause obvious gate drive oscillation. By monolithically integrating the drive circuit DB and the power device PD in the present disclosure, the parasitic inductance in the gate-source loop can be effectively reduced, and the drive performance can be improved.

[0032] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the first 3C-SiC layer 102 and the second 3C-SiC layer 103 can be prepared by an epitaxial process. To isolate the two-dimensional electron gas (2DEG) interconnection between the region where the power device PD is located and the region where the drive circuit DB is located, as Figure 2 shown, the semiconductor device of the present disclosure can further be provided with a third isolation structure 107 located between the region where the power device PD is located and the region where the drive circuit DB is located. The third isolation structure 107 penetrates the first 3C-SiC layer 102 and extends into the 4H-SiC substrate 101. The third isolation structure 107 can be a groove structure prepared by an etching process or a P-type doping structure formed by implanting P-type doping atoms by an ion implantation process.

[0033] In some embodiments, Figure 3 shows a SPICE current simulation schematic diagram of a single-stage drive circuit provided by the embodiments of the present disclosure. As Figure 3 shown, the drive circuit DB of the present disclosure includes a first-stage drive circuit DB1. The first-stage drive circuit DB1 includes an N-type field-effect transistor NFET and a P-type field-effect transistor PFET. The first gate of the N-type field-effect transistor NFET is a pulsed gate signal input terminal electrically connected to the V2 signal generator, and the first electrode of the N-type field-effect transistor NFET is a drive signal output terminal electrically connected to the gate G3 of the power device PD.

[0034] It should be noted that for the convenience of verifying the driving performance of the drive circuit DB of the present disclosure, the P-type field-effect transistor PFET, the N-type field-effect transistor NFET, and the power device PD in Figure 3 can all be replaced by commercial tubes. Among them, Figure 3 the number of P-type field-effect transistors PFET in Figure 3 is one, and 50 N-type field-effect transistors NFET are connected in parallel, aiming to match the rated currents of the P-type field-effect transistor PFET and the N-type field-effect transistor NFET. The model of the P-type field-effect transistor PFET is 2N5018, the rated current is 30 mA, and the threshold voltage is +4.15 V. The model of the N-type field-effect transistor NFET is 2N4119A, the rated current is 600 μA, and the threshold voltage is -4.5 V.

[0035] Figure 4The time-voltage curve with a triangular symbol is the curve of the change of the square-wave voltage pulse signal input by the V2 signal generator over time, and the time-voltage curve with a square symbol is the curve of the change of the gate voltage of the power device PD input after the square-wave voltage pulse signal passes through the first-stage drive circuit DB1 over time. It can be seen that in the present disclosure, the gate voltage of the power device PD input through the first-stage drive circuit DB1 remains in phase with the square-wave voltage pulse signal.

[0036] Figure 5 is Figure 3 The test result of the double-pulse test circuit on the right side in the figure. The time-voltage curve with a square symbol is the curve of the change of the gate voltage of the power device PD input after the square-wave voltage pulse signal input by the V2 signal generator passes through the first-stage drive circuit DB1 over time; the time-current curve with a dot symbol is the curve of the change of the current magnitude of the L1 inductor in the double-pulse test circuit over time. It can be seen that when the gate voltage is about 0V, the power device PD is turned on, and at this time, the current I of the L1 inductor increases, which is in the charging state. When the gate voltage is about -20V, the power device PD is turned off, and the L1 inductor conducts freewheeling through the upper transistor U. At this time, the current inside the L1 inductor is approximately constant.

[0037] Figure 6 is the turn-off curve of the power device PD at about 40 μs. The time-voltage curve with a triangular symbol represents the change of the gate voltage of the power device PD over time, and the time-current curve with a square symbol represents the change of the gate current of the power device PD over time. At about 40 μs, the gate voltage of the power device PD drops from -0.63V to about -12.3V and enters the Miller plateau. The gate current of the power device PD is about -613 mA. After that, the gate voltage of the power device PD reaches -19.3V, and the power device PD is completely turned off. The maximum peak value of the gate current of the power device PD is about -664 mA, and then it decreases to the Miller plateau, and the gate current is about -613 mA. The duration of the gate current pulse is 0.3 μs.

[0038] In some embodiments, Figure 7 shows the SPICE current simulation schematic diagram of the two-stage drive circuit provided by the embodiment of the present disclosure, as Figure 7As shown, the drive circuit DB may include a first-stage drive circuit DB1 and a second-stage drive circuit DB2. The first-stage drive circuit DB1 and the second-stage drive circuit DB2 each include an N-type field-effect transistor NFET and a P-type field-effect transistor PFET. Among them, the first gate of the N-type field-effect transistor NFET in the first-stage drive circuit DB1 is the pulsed gate signal input terminal electrically connected to the V2 signal generator. The first gate of the N-type field-effect transistor NFET in the second-stage drive circuit DB2 is electrically connected to the first electrode of the N-type field-effect transistor NFET in the first-stage drive circuit DB1. The first electrode of the N-type field-effect transistor NFET in the second-stage drive circuit DB2 is the drive signal output terminal electrically connected to the gate G3 of the power device PD.

[0039] It should be noted that, for the convenience of verifying the driving performance of the drive circuit DB of the present disclosure, the P-type field-effect transistor PFET, the N-type field-effect transistor NFET, and the power device PD of the present disclosure can all be replaced by commercial tubes in Figure 7 Among them, Figure 7 in the first-stage drive circuit DB1, the number of P-type field-effect transistors PFET is one, and 50 N-type field-effect transistors NFET are connected in parallel. In the second-stage drive circuit DB2, 3 P-type field-effect transistors PFET are connected in parallel, and 150 N-type field-effect transistors NFET are connected in parallel. The purpose is to match the rated currents of the P-type field-effect transistor PFET and the N-type field-effect transistor NFET. The model of the P-type field-effect transistor PFET is 2N5018, the rated current is 30 mA, and the threshold voltage is +4.15 V. The model of the N-type field-effect transistor NFET is 2N4119A, the rated current is 600 μA, and the threshold voltage is -4.5 V. The rated current of the first-stage drive circuit DB1 is 30 mA, and the rated current of the second-stage drive circuit DB2 is 90 mA.

[0040] By adjusting the parallel connection number of the second-stage drive circuit DB2, as Figure 7 shown, after adding parallel devices and reaching three times the number, the switching time of the power device PD can be adjusted to increase by about three times (it is necessary to use a two-stage drive circuit to achieve the three-fold switching time effect in the embodiment shown in Figure 7 . Only increasing the parallel connection number of the first-stage drive circuit DB1 will not change the magnitude and pulse time of the gate drive pulse of the power device PD). Since the gate drive charge quantity is constant, the embodiment using a two-stage drive circuit can reduce the drive current of the power device PD to about 1 / 3 of that of the single-stage drive circuit embodiment, thereby reducing the peak value of the switching current of the gate of the power device PD. The design of using a two-stage drive circuit for driving plays a role in actively modulating the gate peak current of the power device PD and protecting the gate of the power device PD.

[0041] Figure 8 In Figure 7 the double-pulse test simulation schematic diagram of the embodiment shown. Among them, the time-current curve with a triangular symbol is the curve of the current of the L1 inductor changing with time, the time-voltage curve with a square symbol is the curve of the gate voltage of the power device PD changing with time, and the time-current curve with a dot symbol is the curve of the gate current of the power device PD changing with time.

[0042] Figure 9 It is the turn-off curve of the power device PD at about 40 μs. The time-voltage curve with a triangular symbol represents the change of the gate voltage of the power device PD with time, and the time-current curve with a square symbol represents the change of the gate current of the power device PD with time. At about 40 μs, the gate voltage of the power device PD drops from -1.26 V to about -9.7 V and enters the Miller plateau. The gate current of the power device PD is -87 mA. After that, the gate voltage of the power device PD reaches -18.6 V, and the power device PD is completely turned off. The maximum peak value of the gate current of the power device PD is about -143 mA, and then it decreases to the Miller plateau, and the gate current is about -87 mA. The duration of the gate drive current pulse is 1.14 μs.

[0043] Verified by SPICE simulation, Figure 7 in the drive circuit DB of the embodiment shown, the source and drain of the 1 P-type field-effect transistor PFET included in the first-stage drive circuit DB1 are swapped, and / or the source and drain of the 50 N-type field-effect transistors NFET included in the first-stage drive circuit DB1 are swapped; the source and drain of the 3 P-type field-effect transistors PFET included in the second-stage drive circuit DB2 are swapped, and / or the source and drain of the 150 N-type field-effect transistors NFET included in the second-stage drive circuit DB2 are swapped, and the same function can be obtained.

[0044] In some embodiments, the present disclosure also specifically describes Figure 2 the preparation process of the semiconductor device shown as follows: The first step: epitaxially grow the first 3C-SiC layer 102 and the second 3C-SiC layer 103 with a target thickness of 25 nm to 30 nm on the carbon surface and the silicon surface of the 4H-SiC substrate 101 respectively. Among them, n-type lightly doped (doping concentration < 10 15 cm -3 ) or intrinsic 3C-SiC is epitaxially grown on the carbon surface of the 4H-SiC substrate 101, and p-type lightly doped (doping concentration < 10 15 cm -3), or intrinsic 3C-SiC. A spontaneously polarized two-dimensional electron gas (2DEG) is formed at the interface between the first 3C-SiC layer 102 and the 4H-SiC substrate 101, and a spontaneously polarized two-dimensional hole gas (2DHG) is formed at the interface between the second 3C-SiC layer 103 and the 4H-SiC substrate 101, as Figure 10 shown.

[0045] Step 2: Fabricate a through-silicon carbide via (TSV) in a specified area of the above epitaxial wafer, as Figure 11 shown. For example, by dry etching, the bias power is 1 kW, the ICP power is 4 kW, the flow rates of etching gases such as SF6 / O2 / Ar are 6 sccm / 6 sccm / 8 sccm, the reaction chamber pressure is 15 mTorr, and the ambient temperature is 20°C.

[0046] Step 3: Deposit a dielectric layer to isolate the filling metal of the following interconnect pillar 104 from conducting with the 4H-SiC substrate 101, the first 3C-SiC layer 102, and the second 3C-SiC layer 103. The dielectric layer material on the inner wall of the through-silicon carbide via (TSV) may include materials such as silicon oxide, silicon nitride, and polymer, and the deposition process may be PECVD, SACVD, ALD, and thermal oxidation.

[0047] Step 4: Deposit a barrier layer, and the barrier layer material may include metals or metal compounds such as Ta, TaN / Ta, and TiN.

[0048] Step 5: Deposit a seed layer, and a seed layer made of Cu material is grown after the barrier layer, which is used for conduction in the subsequent electroplating filling process and provides Cu crystal nuclei to obtain more uniform crystallization.

[0049] Step 6: Use the electrochemical plating (ECP) process to fill the conductive material in the through-silicon carbide via (TSV). The conductive materials that can be filled by ECP include Cu, W, polysilicon, etc. The present disclosure can use Cu metal for electroplating filling, and the wafer is annealed after filling to make the grains of the conductive metal filler more uniform.

[0050] Step 7: After the Cu electroplating is completed, a Cu metal layer with uneven thickness is deposited on the surface of the wafer. Chemical mechanical polishing (CMP) is used to remove the excess Cu metal to planarize the surface, and only the Cu metal within the through-hole TSV is retained as the interconnect posts 104 (including the first interconnect post 1041, the second interconnect post 1042, and the third interconnect post 1043). In this step, the dielectric layer, the barrier layer, and the seed layer on the surface of the 4H-SiC substrate 101 are synchronously removed, and only the dielectric layer, the barrier layer, and the seed layer within the through-hole TSV are retained. The cross-section of the final wafer is as shown in Figure 12 shown, Figure 12 and the dielectric layer, the barrier layer, and the seed layer are not shown.

[0051] Step 8: By surface deposition of ohmic metal and dry etching, the first electrode S1, the second electrode D1, the source electrodes S3 and D3 on the surface of the first 3C-SiC layer 102, and the third electrode S2 and the fourth electrode D2 on the surface of the second 3C-SiC layer 103 are realized. Further, by surface deposition of Schottky metal and etching, the first gate G1 and the gate G3 on the surface of the first 3C-SiC layer 102, and the second gate G2 on the surface of the second 3C-SiC layer 103 are realized.

[0052] Step 9: In the region between the first interconnect post 1041 and the second interconnect post 1042, and in the region between the first interconnect post 1041 and the power device PD, P-type doping atoms are implanted from the side where the carbon surface of the 4H-SiC substrate 101 is located to form the first isolation structure 105 that penetrates the first 3C-SiC layer 102 and extends into the 4H-SiC substrate 101 in the region between the first interconnect post 1041 and the second interconnect post 1042, and the third isolation structure 107 that penetrates the first 3C-SiC layer 102 and extends into the 4H-SiC substrate 101 in the region between the first interconnect post 1041 and the power device PD. N-type doping atoms can also be implanted from the side where the silicon surface of the 4H-SiC substrate 101 is located in the region between the second interconnect post 1042 and the third interconnect post 1043 to obtain the second isolation structure 106 that penetrates the second 3C-SiC layer 103 and extends into the 4H-SiC substrate 101.

[0053] Step 10: Dielectric layer deposition, via opening, and metallization interconnect are performed on the first 3C-SiC layer 102 and the second 3C-SiC layer 103 to achieve Figure 2 the electrical connection between various parts of the device as shown.

[0054] Based on the same inventive concept, embodiments of the present disclosure provide a power device, including the semiconductor device provided in the embodiments of the present disclosure. Since the principle of the power device for solving problems is similar to that of the semiconductor device, the implementation of the power device provided in the embodiments of the present disclosure can refer to the implementation of the semiconductor device provided in the embodiments of the present disclosure, and the repeated parts will not be described again.

[0055] In some embodiments, the power device provided in the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, home appliances, etc. Of course, in addition to including semiconductor devices, the power device provided in the present disclosure may also include other structures. For example, when the power device is a radar, it further includes: a transmitter, an antenna, a receiver, etc.; when the power device is a mixer, it may further include: an input port and an output port, etc.

[0056] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0057] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A semiconductor device, characterized in that, Comprising: A driving circuit, the driving circuit includes an N-type field effect transistor and a P-type field effect transistor arranged at intervals. Wherein, the N-type field effect transistor includes a 4H-SiC substrate, a first 3C-SiC layer located on the side where the carbon surface of the 4H-SiC substrate is located, and a first gate, a first electrode and a second electrode located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The P-type field effect transistor includes the 4H-SiC substrate, a second 3C-SiC layer located on the side where the silicon surface of the 4H-SiC substrate is located, and a second gate, a third electrode and a fourth electrode located on the side of the second 3C-SiC layer away from the 4H-SiC substrate; Interconnection posts, penetrating the 4H-SiC substrate, the interconnection posts are insulated from the first 3C-SiC layer, the 4H-SiC substrate and the second 3C-SiC layer. The interconnection posts include a first interconnection post, a second interconnection post and a third interconnection post. The first interconnection post connects the first gate and the second gate. The second interconnection post connects the first electrode and the third electrode. The third interconnection post connects the fourth electrode and one end of a constant voltage source. The other end of the constant voltage source and the second electrode are both grounded.

2. The semiconductor device according to claim 1, wherein It further includes a first isolation structure and a second isolation structure; The first 3C-SiC layer is also located in the area where the P-type field effect transistor is located. The first isolation structure penetrates the first 3C-SiC layer in the area where the P-type field effect transistor is located and extends into the 4H-SiC substrate; The second 3C-SiC layer is also located in the area where the N-type field effect transistor is located. The second isolation structure penetrates the second 3C-SiC layer in the area where the N-type field effect transistor is located and extends into the 4H-SiC substrate.

3. The semiconductor device according to claim 2, wherein, The first isolation structure is a groove structure or a P-type doping structure, and the second isolation structure is a groove structure or an N-type doping structure.

4. The semiconductor device according to claim 2, wherein, The interconnection posts specifically penetrate the first 3C-SiC layer, the 4H-SiC substrate and the second 3C-SiC layer.

5. The semiconductor device according to claim 4, wherein, It further includes: A seed layer, a barrier layer and a dielectric layer penetrating the first 3C-SiC layer, the 4H-SiC substrate and the second 3C-SiC layer. Wherein, the seed layer is in contact with the interconnection posts, the dielectric layer is in contact with the first 3C-SiC layer, the 4H-SiC substrate and the second 3C-SiC layer, and the barrier layer is located between the seed layer and the dielectric layer.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode. One of the third electrode and the fourth electrode is a source electrode, and the other is a drain electrode.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that, The thicknesses of the first 3C-SiC layer and the second 3C-SiC layer are both 25nm to 30nm.

8. The semiconductor device according to claim 1, wherein The driving circuit includes a first-stage driving circuit. The first-stage driving circuit includes the N-type field effect transistor and the P-type field effect transistor. The first gate is the input terminal of the pulse gate signal, and the first electrode is the output terminal of the driving signal.

9. The semiconductor device according to claim 1, wherein The driving circuit includes a first-stage driving circuit and a second-stage driving circuit. The first-stage driving circuit and the second-stage driving circuit respectively include the N-type field effect transistor and the P-type field effect transistor; The first gate of the first-stage driving circuit is the input terminal of the pulsed gate signal. The first gate of the second-stage driving circuit is electrically connected to the first electrode of the first-stage driving circuit, and the first electrode of the second-stage driving circuit is the output terminal of the driving signal.

10. The semiconductor device according to claim 8 or 9, characterized in that, It further includes a power device disposed at an interval from the driving circuit. The power device includes the 4H-SiC substrate, the first 3C-SiC layer, the second 3C-SiC layer, and the gate, source, and drain located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The gate of the power device is electrically connected to the driving signal output terminal, the source of the power device is grounded, and the drain of the power device is electrically connected to the load.

11. The semiconductor device according to claim 10, wherein, It further includes a third isolation structure located between the region where the power device is located and the region where the driving circuit is located. The third isolation structure penetrates the first 3C-SiC layer and extends into the 4H-SiC substrate.

12. The semiconductor device according to claim 11, wherein The third isolation structure is a groove structure or a P-type doping structure.

13. A power device, characterized in that, It includes the semiconductor device according to any one of claims 1 to 12.

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