Preparation method of semiconductor device
By removing the oxide layer after performing a light doping process on the semiconductor substrate and forming a second oxide layer with uniform thickness, the problem of uneven morphology of the source and drain trench of PMOS devices is solved, and the stability of device performance and production efficiency are improved.
Patent Information
- Application Number
- CN202311836821.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, the source and drain groove morphology of PMOS devices has large differences, resulting in unstable performance and affecting production line capacity.
After performing a light doping process on the semiconductor substrate, the first oxide layer is removed by a wet process to form a second oxide layer with a smaller thickness fluctuation, and then the oxide layer and part of the substrate are removed in turn to form a source-drain trench and an epitaxial structure is constructed therein.
It improves the morphological uniformity of the source and drain trench, stabilizes the device performance, simplifies the processing flow, and improves production efficiency.
Smart Images
Figure CN120264853A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor device. Background Art
[0002] With the development of technology, the critical dimension (CD) of devices is getting smaller and smaller. It is often necessary to adopt an embedded epitaxial structure in the source-drain region to change the stress in the channel region, thereby improving the carrier mobility and thus the performance of the device. For PMOS devices, the embedded epitaxial layer usually adopts a germanium-silicon epitaxial structure (SiGe).
[0003] In the related art, the steps before and after forming the above epitaxial structure usually include: selectively performing a corresponding light doping process on the source-drain regions of the PMOS device. Then, the oxide layer on the surface of the source-drain regions of the PMOS device and a part of the thickness of the substrate are removed to form source-drain trenches (grooves), and then a germanium-silicon structure is epitaxially formed inside and outside the source-drain trenches. However, in practice, the overall morphology of some of the above source-drain trenches often shows abnormal conditions (for example, the morphology differences of different source-drain trenches are relatively large), resulting in the risk that the performance of the PMOS device cannot meet the standards and seriously affecting the production line capacity. Summary of the Invention
[0004] The purpose of the present invention is to provide a method for manufacturing a semiconductor device, which can efficiently improve the morphology uniformity of the source-drain trenches.
[0005] To solve the above technical problems, the method for manufacturing a semiconductor device provided by the present invention includes:
[0006] Providing a semiconductor substrate, which includes a first gate structure and first source-drain regions located on both sides of the first gate structure;
[0007] Performing a light doping process on the first source-drain regions, and a first oxide layer is formed on the first source-drain regions after the light doping process;
[0008] Removing the first oxide layer by a wet process to expose the surface of the semiconductor substrate;
[0009] Performing an oxidation process to form a second oxide layer on the surface of the first source-drain regions, and the thickness fluctuation of the second oxide layer is smaller than the thickness fluctuation of the first oxide layer;
[0010] Sequentially removing the second oxide layer of the first source-drain regions and a part of the thickness of the semiconductor substrate to form source-drain trenches, and forming an epitaxial structure in the source-drain trenches as its source-drain structure.
[0011] Optionally, a second gate structure and second source / drain regions located on both sides of the second gate structure are further included on the semiconductor substrate. After performing corresponding lightly doped processes on both the first source / drain regions and the second source / drain regions, the wet process and the oxidation process are then performed. Among them, the steps of performing the lightly doped process on the first source / drain regions include:
[0012] Form a patterned photoresist layer to cover the second gate structure and the second source / drain regions, and expose the first gate structure and the first source / drain regions;
[0013] Perform lightly doped ion implantation on the first source / drain regions;
[0014] Use an ashing process to remove the patterned photoresist layer, and a first oxide layer with a first thickness is formed on the surface of the first source / drain regions.
[0015] Optionally, after forming the patterned photoresist layer, perform a rework lithography rework process on the abnormal patterned photoresist layer, and then perform the lightly doped process and the ashing process. A first oxide layer with a second thickness is formed on the surface of the first source / drain regions, and the second thickness is greater than the first thickness.
[0016] Optionally, the first gate structure and the first source / drain regions are used to form a P-type transistor of a semiconductor device, and the epitaxial structure includes a germanium-silicon structure.
[0017] Optionally, the etching solution for the wet process includes diluted hydrofluoric acid, and over-etching is used to remove the first oxide layer.
[0018] Optionally, the thickness fluctuation of the second oxide layer is less than or equal to 20 angstroms.
[0019] Optionally, the steps of forming the second oxide layer include: introducing oxygen or oxygen plasma into the surface of the semiconductor substrate, and performing dry thermal oxidation to form a second oxide layer with a third thickness.
[0020] Optionally, the third thickness is equal to the first thickness.
[0021] Optionally, the oxidation process also simultaneously forms a third oxide layer covering the second source / drain regions.
[0022] Optionally, the steps of forming the source / drain trenches include:
[0023] Form a patterned mask layer on the semiconductor substrate, and its opening exposes the second oxide layer;
[0024] Perform a dry etching process to sequentially remove the second oxide layer and a part of the thickness of the semiconductor substrate to form a transition trench;
[0025] The transition trench is anisotropically wet-etched to form the source / drain trench in the first source / drain region.
[0026] In summary, after performing a lightly doped process on the first source / drain regions on both sides of the first gate structure in the present invention, a wet process is used to remove the first oxide layer on the surface of the first source / drain regions to expose the surface of the semiconductor substrate, and then an oxidation process is performed to form a second oxide layer on the surface of the first source / drain regions. Subsequently, the second oxide layer of the first source / drain regions and a part of the thickness of the semiconductor substrate are sequentially removed to form the source / drain trenches, and an epitaxial structure is formed in the source / drain trenches to serve as the source / drain structure thereof. In the present invention, by removing the first oxide layer on the surface of the first source / drain regions after the lightly doped process and then re-oxidizing to form a second oxide layer with a relatively small thickness fluctuation (uniform thickness), a unified etching time can be adopted for the first source / drain regions with and without photoresist rework to form a transition trench with a relatively stable size (mainly depth), and then a source / drain trench with a better morphology (i.e., improving the morphology uniformity of the source / drain trench) is formed, so as to prevent abnormal morphology of the source / drain trench caused by a large fluctuation in the thickness of the oxide layer on the premise that the etching rates of the oxide layer and the semiconductor substrate are different. Moreover, in this embodiment, a unified processing method is adopted for the first source / drain regions with or without photoresist rework. Compared with the related art in which different processing methods are adopted for the first source / drain regions with or without photoresist rework respectively, it is more simple and feasible and has high practicability. Description of the Drawings
[0027] Those of ordinary skill in the art should understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention.
[0028] Figure 1 is a flowchart of the method for manufacturing a semiconductor device provided in this embodiment;
[0029] Figures 2a to 2h are schematic structural diagrams corresponding to the respective steps of the method for manufacturing a semiconductor device provided in this embodiment.
[0030] In the drawings:
[0031] 10 - semiconductor substrate; AA - first region; BB - second region; 21 - first gate structure; 22 - first source / drain region; 23 - second gate structure; 24 - second source / drain region; 25 - patterned photoresist layer; 26 - lightly doped region; 27 - first oxide layer; 28 - third oxide layer; 29 - second oxide layer; 31 - patterned mask layer; 31a - hard material layer; 31b - filling material layer; 31c - photoresist layer; 32 - sidewall; 33 - transition trench; 34 - source / drain trench; 35 - epitaxial structure. Detailed Embodiments
[0032] To make the objectives, advantages and features of the present invention more clear, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes use different scales.
[0033] As used in the present invention, the singular forms "a", "an" and "the" include plural objects. The term "or" is generally used in the sense of including "and / or". The term "several" is generally used in the sense of including "at least one". The term "at least two" is generally used in the sense of including "two or more". In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features, unless the content clearly indicates otherwise.
[0034] This embodiment provides a method for manufacturing a semiconductor device.
[0035] Figure 1 is a flowchart of the method for manufacturing a semiconductor device provided in this embodiment.
[0036] As Figure 1 shown, the method for manufacturing a semiconductor device provided in this embodiment includes:
[0037] S01: Provide a semiconductor substrate, which includes a first gate structure and first source / drain regions located on both sides of the first gate structure;
[0038] S02: Perform a lightly doped process on the first source / drain regions, and a first oxide layer is formed on the first source / drain regions after the lightly doped process;
[0039] S03: Remove the first oxide layer by a wet process to expose the surface of the semiconductor substrate;
[0040] S04: Perform an oxidation process to form a second oxide layer on the surface of the first source / drain regions, and the thickness fluctuation of the second oxide layer is smaller than that of the first oxide layer;
[0041] S05: Remove the second oxide layer of the first source / drain regions and a part of the thickness of the semiconductor substrate in sequence to form source / drain trenches, and form an epitaxial structure in the source / drain trenches to serve as its source / drain structure.
[0042] Figures 2a to 2h This is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method of the semiconductor device provided in this embodiment. Next, the manufacturing method of the semiconductor device will be described in detail with reference to Figures 2a to 2h this.
[0043] First, please refer to Figure 2a , and perform step S01 to provide a semiconductor substrate 10, which includes a first gate structure 21 and first source / drain regions 22 located on both sides of the first gate structure 21.
[0044] The material of the semiconductor substrate 10 may include any suitable substrate material well-known to those skilled in the art. For example, it may be at least one of the materials mentioned below: silicon, glass, quartz, plastic, etc.
[0045] The semiconductor substrate 10 may include several different regions for forming transistors with different electrical properties and different performances. For example, it includes a first region AA and a second region BB. A first gate structure 21 and a first source / drain region 22 are provided on the first region AA, and the first source / drain region 22 is disposed on both sides of the first gate structure 21. A second gate structure 23 and a second source / drain region 24 are provided on the second region BB, and the second source / drain region 24 is disposed on both sides of the second gate structure 23. In this embodiment, the first region AA may be used to form PMOS transistors in the core region, and the second region BB may be used to form other transistors, such as NMOS transistors in the core region, NMOS transistors in the IO region, and PMOS transistors in the IO region, etc.
[0046] In addition, in some examples, the first gate structure 21 and the second gate structure 23 may be dummy gate structures for forming metal gates.
[0047] Next, perform step S02 to perform a lightly doped process on the first source / drain region 22, and a first oxide layer 27 is formed on the first source / drain region 22 after the lightly doped process.
[0048] Specifically, please refer to Figure 2b , and form a patterned photoresist layer 25 to cover the second gate structure 23 and the second source / drain region 24, and expose the first gate structure 21 and the first source / drain region 22.
[0049] Please refer to Figure 2c, a lightly doped ion implantation is performed on the first source / drain region 22 to form a lightly doped region 26, and the patterned photoresist layer 25 is removed by an ashing process. A first oxide layer 27 with a first thickness is formed on the surface of the first source / drain region 22. Among them, the ashing process may include oxygen or oxygen plasma and is carried out at a temperature of, for example, 200 °C to 350 °C to remove the patterned photoresist layer 25, and thus a first oxide layer 27 with a first thickness is thermally oxidized on the surface of the first source / drain region 22. The first thickness may be, for example, 15 Å to 25 Å. Of course, the first oxide layer 27 may also include a thinner native oxide layer formed on the first source / drain region 22 before the ashing process. It can be understood that during the process of removing the patterned photoresist, as the second source / drain region 24 is gradually exposed, a third oxide layer 28 may also be formed on the surface of the second source / drain region 24, and the third oxide layer 28 also includes the original oxide layer on its surface. In addition, the third oxide layer 28 may also include the oxide layer formed during the corresponding lightly doped process, that is, before or after forming the first oxide layer 27, a corresponding lightly doped process is performed on the second gate structure 23 and the second source / drain region 24.
[0050] Specifically, after forming the patterned photoresist layer 25 and before performing the lightly doped ion implantation, the patterned photoresist layer 25 is also inspected (appearance), and for the abnormal (unqualified) patterned photoresist layer 25, a photolithography rework process is performed, that is, the abnormal patterned photoresist layer 25 is removed by an ashing process, and then the patterned photoresist layer 25 is re-formed. The first oxide layer 27 with the reworked patterned photoresist layer 25 has undergone at least two ashing processes and has a longer exposure time, and its second thickness is greater than the first thickness. The second thickness may be, for example, 25 Å to 45 Å.
[0051] Therefore, the thickness of the first oxide layer 27 has a relatively large fluctuation range, and its fluctuation range can cover the first thickness and the second thickness. Taking the first thickness as 15 Å to 45 Å as an example, its thickness fluctuation can reach 30 Å (that is, up to 100% of the average thickness).
[0052] Next, please refer to Figure 2d , perform step S03, and use a wet process to remove the first oxide layer 27 to expose the surface of the semiconductor substrate 10. Among them, the etching solution for the wet process may include diluted hydrofluoric acid, and its concentration may be, for example, 0.02%. And preferably, a moderate over-etching (for example, the etching time is extended by several seconds) is adopted to ensure that the first oxide layer 27 of the first source / drain region 22 is completely removed to expose the surface of the first source / drain region 22. Of course, the third oxide layer 28 on the second source / drain region 24 is also removed synchronously to expose the surface of the second source / drain region 24. In addition, the above wet process can also achieve a cleaning effect on the semiconductor substrate 10.
[0053] Next, please refer toFigure 2e , perform step S04 , perform an oxidation process to form a second oxide layer 29 on the surface of the first source and drain region 22 , and the thickness fluctuation of the second oxide layer 29 is smaller than the thickness fluctuation of the first oxide layer 27 .
[0054] Compared with the first oxide layer 27 formed by different steps, the present embodiment adopts a unified oxidation process to form the second oxide layer 29 on the surface of the first source and drain region 22 on different semiconductor substrates 10, and the fluctuation of the third thickness of the second oxide layer 29 will be significantly smaller than the thickness fluctuation of the first oxide layer 27, that is, the second oxide layer 29 has a smaller thickness fluctuation (more uniform thickness). Of course, the thickness fluctuation of the second oxide layer 29 depends on the oxidation process used and its process control. Taking the dry thermal oxidation process used in the present embodiment as an example, the third thickness can be 20 angstroms to 24 angstroms, and its fluctuation range does not exceed 4 angstroms (i.e., does not exceed 18% of the average thickness). In addition, oxygen or oxygen plasma is introduced into the surface of the semiconductor substrate 10 at a temperature of, for example, 25°C to 500°C, in addition to forming the second oxide layer 29 on the surface of the first source and drain region 22, the second oxide layer 29 is also formed on the surface of the second source and drain region 24 simultaneously, wherein the thickness fluctuation range of the second oxide layer 29 is less than or equal to 20 angstroms.
[0055] In a preferred example, the conditions of the oxidation process can be controlled so that the third thickness of the second oxide layer 29 is kept as consistent as possible with the first thickness, that is, the thickness of the second oxide layer 29 is consistent with the thickness of the first oxide layer 27 that has not undergone the photoresist rework process, so that the subsequent etching process for forming the source and drain grooves 34 is consistent with the etching process in the related technology (not adopting the inventive method).
[0056] In addition, similar to the second oxide layer 29 of the first source / drain region 22 , the thickness of the second oxide layer 29 of the second source / drain region 24 is also relatively stable, which is beneficial to the process stability when the second source / drain region 24 is subsequently opened.
[0057] Next, step S04 is performed to sequentially remove the second oxide layer 29 of the first source / drain region 22 and a portion of the semiconductor substrate 10 to form source / drain trenches 34 , and to form epitaxial structures 35 in the source / drain trenches 34 as source / drain structures.
[0058] For details, please refer to Figure 2f, a patterned mask layer 31 is formed on a semiconductor substrate 10, covering the second region BB, and the surface of the second oxide layer 29 in the first region AA is exposed through its opening. Among them, the mask layer may include a hard material layer 31a, a filling material layer 31b, and a photoresist layer 31c formed in sequence. The hard material layer 31a covers the outer walls of the source / drain regions and the gate structure, and the filling material layer 31b is filled above the gate structure. When patterning the mask layer, that is, when opening the hard material layer 31a on the first source / drain region 22, the hard material layer 31a covering the sidewall of the first gate structure 21 is retained and used as the sidewall 32 of the first gate structure 21. Of course, during the process of opening the hard material layer 31a on the first source / drain region 22, the photoresist layer 31c and the filling material layer 31b on the second region BB may also be partially or completely removed, and the remaining hard material layer 31a is used as the patterned mask layer 31.
[0059] Please refer to Figure 2g , using the patterned mask layer 31, a dry etching process is performed to sequentially remove the second oxide layer 29 and a part of the thickness of the semiconductor substrate 10 to form a transition trench 33. In the above dry etching process, the different materials of the second oxide layer 29 and the semiconductor substrate 10 result in different etching rates. Under the same etching time, the thickness fluctuation of the second oxide layer 29 will directly affect the etching time of the semiconductor substrate 10, and further affect the depth of the formed transition trench 33. In this embodiment, due to the small thickness fluctuation of the second oxide layer 29, a transition trench 33 with relatively stable dimensions (mainly depth) can be formed in the first source / drain region 22 with or without photoresist rework through a unified etching time, and its shape can be, for example, bowl-shaped. Thus, it is not difficult to understand that in the related art, due to the large thickness difference of the oxide layers on the source / drain regions on different semiconductor layers (with or without photoresist rework), the depth fluctuation of the formed trenches is large, which further affects the size of the subsequent formed epitaxial structure 35 and the performance of the device.
[0060] Moreover, in this embodiment, a unified processing method is adopted for the first source / drain region 22 with or without photoresist rework. Compared with the related art where different processing methods are adopted for the first source / drain region 22 with or without photoresist rework respectively, it is more simple and feasible and has high practicability.
[0061] Please refer to Figure 2h, the transition trench 33 is anisotropically wet-etched to form a source / drain trench 34 in the first source / drain region 22, and an epitaxial structure 35 is epitaxially formed in the source / drain trench 34 as the source / drain structure. In this embodiment, for example, TMAH (tetramethylammonium hydroxide) can be used to anisotropically etch the silicon exposed in the transition trench 33 to form, for example, a Σ-shaped source / drain trench 34. Taking the first region AA for forming the PMOS transistors in the core region as an example, the epitaxial structure 35 may include a germanium-silicon epitaxy. It should be particularly noted that in other examples of this embodiment, the first region AA can also be used to form NMOS transistors in the core region, and the corresponding epitaxial structure formed can be a carbon-silicon epitaxy.
[0062] In summary, after performing a lightly doped process on the first source / drain regions on both sides of the first gate structure in the present invention, a wet process is used to remove the first oxide layer on the surface of the first source / drain regions to expose the surface of the semiconductor substrate, and then an oxidation process is performed to form a second oxide layer on the surface of the first source / drain regions. Then, the second oxide layer and a part of the thickness of the semiconductor substrate in the first source / drain regions are sequentially removed to form source / drain trenches, and an epitaxial structure is formed in the source / drain trenches as their source / drain structures. In the present invention, by removing the first oxide layer on the surface of the first source / drain regions after the lightly doped process and then re-oxidizing to form a second oxide layer with a relatively small thickness fluctuation (uniform thickness), a unified etching time can be used for the first source / drain regions with and without photoresist rework to form transition trenches with relatively stable dimensions (mainly depth), and then form source / drain trenches with better morphology (i.e., improve the morphology uniformity of the source / drain trenches), so as to prevent abnormal source / drain trench morphology caused by large fluctuations in the thickness of the oxide layer under the premise that the etching rates of the oxide layer and the semiconductor substrate are different. Moreover, in this embodiment, a unified treatment method is adopted for the first source / drain regions with and without photoresist rework. Compared with the related art where different treatment methods are adopted for the first source / drain regions with and without photoresist rework respectively, it is more simple and feasible and has high practicability.
[0063] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a semiconductor substrate, on which a first gate structure and first source / drain regions located on both sides of the first gate structure are included; Performing a lightly doped process on the first source / drain regions, and a first oxide layer is formed on the first source / drain regions after the lightly doped process; Removing the first oxide layer by a wet process to expose the surface of the semiconductor substrate; Performing an oxidation process to form a second oxide layer on the surface of the first source / drain regions, and the thickness fluctuation of the second oxide layer is smaller than that of the first oxide layer; Removing the second oxide layer of the first source / drain regions and a part of the semiconductor substrate with a certain thickness in sequence to form source / drain trenches, and forming an epitaxial structure in the source / drain trenches to serve as its source / drain structure.
2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, A second gate structure and second source / drain regions located on both sides of the second gate structure are further included on the semiconductor substrate. After performing corresponding lightly doped processes on the first source / drain regions and the second source / drain regions, the wet process and the oxidation process are then performed. Among them, the steps of performing the lightly doped process on the first source / drain regions include: Forming a patterned photoresist layer to cover the second gate structure and the second source / drain regions, and exposing the first gate structure and the first source / drain regions; Performing lightly doped ion implantation on the first source / drain regions; Removing the patterned photoresist layer by an ashing process, and a first oxide layer with a first thickness is formed on the surface of the first source / drain regions.
3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, After forming the patterned photoresist layer, performing a rework lithography rework process on the abnormal patterned photoresist layer, then performing the lightly doped process and the ashing process, and a first oxide layer with a second thickness is formed on the surface of the first source / drain regions, and the second thickness is greater than the first thickness.
4. The method for manufacturing a semiconductor device according to claim 1, wherein The first gate structure and the first source / drain regions are used to form a P-type transistor of a semiconductor device, and the epitaxial structure includes a germanium-silicon structure.
5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The etching solution of the wet process includes diluted hydrofluoric acid, and over-etching is used to remove the first oxide layer.
6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The thickness fluctuation of the second oxide layer is less than or equal to 20 angstroms.
7. The method for manufacturing a semiconductor device according to claim 2, wherein, The steps of forming the second oxide layer include: introducing oxygen or oxygen plasma into the surface of the semiconductor substrate, and performing dry thermal oxidation to form a second oxide layer with a third thickness.
8. The method for manufacturing a semiconductor device according to claim 7, wherein, The third thickness is equal to the first thickness.
9. The method for manufacturing a semiconductor device according to claim 2, wherein, The oxidation process also synchronously forms a third oxide layer covering the second source / drain regions.
10. The method for manufacturing a semiconductor device according to claim 1, wherein, The steps of forming the source / drain trenches include: Forming a patterned mask layer on the semiconductor substrate, and its opening exposes the second oxide layer; Performing a dry etching process to remove the second oxide layer and a part of the semiconductor substrate with a certain thickness in sequence to form transition trenches; Performing anisotropic wet etching on the transition trenches to form the source / drain trenches in the first source / drain regions.