Image sensor

Abstract

An image sensor is provided and includes a top layer including: a first floating diffusion (FD) wiring structure connected to an FD node; and a first shielding structure beside the first floating diffusion wiring structure. The image sensor further includes an intermediate layer bonded to the top layer and below the top layer, where the intermediate layer includes: a source follower gate; a source follower source region; a second FD wiring structure connected to the first FD wiring structure and the source follower gate; a second shielding structure connected to the first shielding structure and the source follower source region; and a source follower bonding pad between the second shielding structure and the source follower source region and spaced apart from the source follower gate.

Description

[0001] This application is based on and claims priority to Korean Patent Application Nos. 10-2024-0001067, filed with the Korean Intellectual Property Office on January 3, 2024, and 10-2024-0046950, filed with the Korean Intellectual Property Office on April 5, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure relate to an image sensor, and more particularly, to an image sensor capable of increasing conversion gain. Background Art

[0003] An image sensor for capturing an image and converting the image into an electrical signal is used not only in consumer electronic devices (such as digital cameras, mobile phone cameras, and portable video cameras), but also in cameras installed in automobiles, security devices, and robots. The pixels of the image sensor are becoming smaller, and as the pixels become smaller, the floating diffusion capacitance increases, which reduces the conversion gain. Therefore, it is necessary to increase the conversion gain. Summary of the Invention

[0004] According to an embodiment of the present disclosure, there is provided an image sensor capable of increasing conversion gain.

[0005] According to an embodiment of the present disclosure, an image sensor may be provided and includes a top layer including: a first substrate; a floating diffusion (FD) node within the first substrate; a first FD wiring structure connected to the FD node; and a first shielding structure beside the first FD wiring structure. The image sensor may further include: an intermediate layer bonded to the top layer and below the top layer, wherein the intermediate layer includes: a second substrate; a source follower gate on the second substrate; a source follower source region within the second substrate; a second FD wiring structure connected to the first FD wiring structure and the source follower gate; a second shielding structure connected to the first shielding structure and the source follower source region; and a source follower landing pad between the second shielding structure and the source follower source region and spaced apart from the source follower gate. The image sensor may further include: a bottom layer bonded to the intermediate layer and below the intermediate layer, wherein the bottom layer includes: a third substrate; and a transistor on the third substrate.

[0006] According to an embodiment of the present disclosure, an image sensor may be provided and includes a top layer that includes: a first substrate; a floating diffusion (FD) node within the first substrate; a first FD wiring structure connected to the FD node; and a first shielding structure beside the first FD wiring structure. The image sensor may further include: an intermediate layer bonded to the top layer and below the top layer, wherein the intermediate layer includes: a second substrate including a second front surface and a second back surface opposite the second front surface; a source follower gate on the second front surface of the second substrate; a source follower source region within the second substrate; a second FD wiring structure connected to the first FD wiring structure and the source follower gate; and a second shielding structure connected to the first shielding structure and the source follower source region. The image sensor may further include: a bottom layer bonded to the intermediate layer and below the intermediate layer, wherein the bottom layer includes: a third substrate; and a transistor on the third substrate, wherein the second shielding structure includes: a second shielding bonding pad bonded to a first shielding bonding pad included in the first shielding structure; and an impurity region within the second substrate and connected to the second shielding bonding pad.

[0007] According to an embodiment of the present disclosure, an image sensor may be provided and includes a top layer that includes: a first substrate; a pixel isolation layer within the first substrate and defining pixels; a photodiode disposed within the first substrate and forming a pixel; a transfer transistor for transferring an electrical signal generated by the photodiode; a floating diffusion (FD) node within the first substrate and connected to the transfer transistor; a first FD wiring structure connected to the FD node; a first shielding structure beside the first FD wiring structure; and a first wiring layer spaced apart from the first FD wiring structure and the first shielding structure. The image sensor may further include: an intermediate layer bonded to the top layer and below the top layer, wherein the intermediate layer includes: a second substrate; a source follower gate on the second substrate; a source follower source region within the second substrate; a second FD wiring structure connected to the first FD wiring structure and the source follower gate; a second shielding structure connected to the first shielding structure and the source follower source region; a source follower bonding pad between the second shielding structure and the source follower source region and surrounding the source follower gate; and a second wiring layer spaced apart from the second FD wiring structure and the second shielding structure. The image sensor may further include: a bottom layer bonded to the intermediate layer and below the intermediate layer, wherein the bottom layer includes: a third substrate; a transistor disposed on the third substrate; a third wiring layer connected to the transistor; and a third via plug between the transistor and the third wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram showing an image sensor according to an embodiment.

[0010] Figure 2 is the circuit diagram of the image sensor according to the embodiment.

[0011] Figure 3 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0012] Figure 4 is along Figure 3 a plan view taken along line X-X'.

[0013] Figure 5 is along Figure 3 a plan view taken along line X-X'.

[0014] Figure 6 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0015] Figure 7 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0016] Figure 8 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0017] Figure 9 is along Figure 8 a plan view taken along line Y-Y'.

[0018] Figure 10 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0019] Figure 11 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0020] Figure 12 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0021] Figure 13 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0022] Figure 14 is a schematic cross-sectional view for describing the structure of the image sensor according to the embodiment.

[0023] Figure 15A and Figure 15B are cross-sectional views for describing the method of manufacturing the Figure 3 image sensor according to the embodiment.

[0024] Figures 16A to 16D are for describing the manufacturing according to the embodimentFigure 8 Cross-sectional view of a method of an image sensor. Detailed implementation

[0025] In the present disclosure, it should be understood that when any element is referred to as "fastened", "joined", or "connected" to another element, the element can be directly fastened, joined, or connected to the other element, or there may be another element therebetween. On the other hand, in the description, when any element is referred to as "directly fastened", "directly joined", or "directly connected" to another element, it should be understood that there are no other elements therebetween.

[0026] Figure 1 It is a block diagram showing an image sensor according to an embodiment.

[0027] Specifically, the image sensor 100 may include a pixel array 110, a row driver 120, a ramp signal generator 130, a count number generator 140, an analog-to-digital conversion (ADC) circuit 150, a data output circuit 180, and a timing controller 190. The image sensor 100 may further include a signal processor 195. The components including the ADC circuit 150 and the data output circuit 180 may be referred to as a readout circuit.

[0028] The pixel array 110 may include a plurality of row lines RL and a plurality of column lines CL. The pixel array 110 may include a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in rows and columns. The plurality of pixels PX may be active pixel sensors (APS).

[0029] Each of the plurality of pixels PX may include at least one photoelectric conversion element, and the pixel PX may detect light by using the photoelectric conversion element and output an image signal, which is an electrical signal converted from the detected light. For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode (PPD).

[0030] Each of the plurality of pixels PX may detect light in a specific spectral region. For example, a part of the plurality of pixels PX may convert light in the red spectral region into an electrical signal, convert light in the green spectral region into an electrical signal, or convert light in the blue spectral region into an electrical signal. However, the embodiments of the present disclosure are not limited thereto, and at least some of the plurality of pixels may convert light in the white spectral region into an electrical signal.

[0031] In another example, at least some of the plurality of pixels PX may convert light in different color spectral regions into electrical signals. For example, at least some of the plurality of pixels PX may convert light in any one of the yellow spectral region, the cyan spectral region, and the magenta spectral region into an electrical signal.

[0032] A color filter may be disposed above each of a plurality of pixels PX to transmit light in a specific spectral region through the color filter. The color that can be detected by the corresponding pixel in the pixel PX may be determined according to the color filter. However, embodiments of the present disclosure are not limited thereto. According to some embodiments, a specific photoelectric conversion element may convert light in a specific wavelength band into an electrical signal according to the level of an electrical signal applied to the corresponding photoelectric conversion element.

[0033] According to some embodiments, each of the plurality of pixels PX may have a dual conversion gain. The dual conversion gain includes a low conversion gain and a high conversion gain. Here, the conversion gain refers to the ratio at which the charge accumulated in the floating diffusion node (or floating diffusion region) is converted into a voltage. The charge generated by the photoelectric conversion element is transferred to the floating diffusion node FDN (see, for example Figure 3 ), and accumulates in the floating diffusion node FDN, and the charge accumulated in the floating diffusion node FDN may be converted into a voltage according to the conversion gain. At this time, the conversion gain may vary according to the capacitance of the floating diffusion node FDN. When the capacitance increases, the conversion gain may decrease. When the capacitance decreases, the conversion gain may increase.

[0034] The row driver 120 may drive the pixel array 110 row by row. The row driver 120 may decode the row control signal (e.g., address signal) received from the timing controller 190. The row driver 120 may select at least one row line RL from among a plurality of row lines RL constituting the pixel array 110 in response to the decoded row control signal.

[0035] For example, the row driver 120 may generate a selection signal for selecting one from among a plurality of rows. The selection signal may be sent to the pixel array 110 through the row line RL. The pixel array 110 outputs pixel signals (e.g., pixel voltages) from the row selected by the selection signal provided by the row driver 120. The pixel signal may include a reset signal and an image signal. The row driver 120 may send a control signal to the pixel array 110. The control signal may be a signal for outputting a pixel signal. The pixel PX may output a pixel signal by operating in response to the control signal.

[0036] The ramp signal generator 130 may generate a ramp signal (e.g., ramp voltage) under the control of the timing controller 190, and the level of the ramp signal rises or falls at a specific slope. The ramp signal RAMP may be provided to each of a plurality of correlated double sampling (CDS) circuits 160 provided in the ADC circuit 150.

[0037] The count code generator 140 can generate a count code CCD under the control of the timing controller 190. The count code CCD can be provided to each of the plurality of counter circuits 170. According to some embodiments, the count code generator 140 can be implemented as a Gray code generator. The count code generator 140 can generate a plurality of code values with a resolution according to the set number of bits as the count code CCD. For example, when a 10-bit code is set, the count code generator 140 can generate a count code CCD including 1024 code values that increase or decrease sequentially.

[0038] The ADC circuit 150 can include a plurality of CDS circuits 160 and a plurality of counter circuits 170. The ADC circuit 150 can convert the pixel signals input from the pixel array 110 into pixel values as digital signals. Each pixel signal received through each of the plurality of column lines CL is converted into a pixel value as a digital signal by the CDS circuit 160 and the counter circuit 170.

[0039] The CDS circuit 160 can compare the pixel signal received through the column line CL with the ramp signal RAMP, and output the result of the comparison as a comparison result signal. When the level of the ramp signal RAMP is the same as the level of the pixel signal, the CDS circuit 160 can output a comparison signal that changes from a first level (e.g., logic high) to a second level (e.g., logic low). The time point of the level transition of the comparison signal can be determined according to the level of the pixel signal.

[0040] The CDS circuit 160 can sample the pixel signal provided from the pixel PX according to the CDS method. The CDS circuit 160 can sample the reset signal received as the pixel signal, compare the reset signal with the ramp signal RAMP, and generate a comparison signal according to the reset signal. Thereafter, the CDS circuit 160 can sample the image signal related to the reset signal, compare the image signal with the ramp signal RAMP, and generate a comparison signal according to the image signal.

[0041] The counter circuit 170 can count the time point of the level transition of the comparison signal output from the CDS circuit 160, and output a count value. According to some embodiments, the counter circuit 170 can include a latch circuit and a calculation circuit. The latch circuit receives the count code CCD from the count code generator 140 and the comparison signal from the CDS circuit 160, and can latch the code value of the count code CCD at the time point of the level transition of the comparison signal.

[0042] The latch circuit can latch the code value corresponding to the reset signal. For example, the latch circuit can latch the code value corresponding to the reset signal and the code value corresponding to the image signal. For example, the latch circuit can latch the value of the image signal. The calculation circuit can calculate the values of the reset signal and the image signal, and generate the value of the image signal from which the reset level of the pixel PX has been removed. The counter circuit 170 can output the value of the image signal from which the reset level has been removed as the pixel value.

[0043] Regarding this embodiment, it has been described that the image sensor 100 includes the count code generator 140, and the counter circuit 170 includes a circuit that latches the code value of the count code CCD received from the count code generator 140. However, the embodiments of the present disclosure are not limited thereto.

[0044] According to some embodiments, the image sensor 100 may not include a separate count code generator 140, and the counter circuit 170 may be implemented by an increment counter, a calculation circuit, an increment / decrement counter, or a bitwise inversion counter in which the count value is sequentially increased based on the count clock signal provided from the timing controller 190.

[0045] The data output circuit 180 can temporarily store and then output the pixel value output from the ADC circuit 150. The data output circuit 180 can include a plurality of column memories 181 and a column decoder 182. The column memories 181 store the pixel values received from the counter circuit 170. According to some embodiments, the plurality of column memories 181 may each be provided in the counter circuit 170. The plurality of pixel values stored in the plurality of column memories 181 can be output as image data IDT under the control of the column decoder 182.

[0046] The timing controller 190 can output control signals to the row driver 120, the ramp signal generator 130, the count code generator 140, the ADC circuit 150, and the data output circuit 180, so as to control the operations or timings of the row driver 120, the ramp signal generator 130, the count code generator 140, the ADC circuit 150, and the data output circuit 180.

[0047] The signal processor 195 can perform noise reduction processing, gain adjustment, waveform formulation, interpolation processing, white balance processing, gamma processing, edge enhancement processing, sharpening, etc. on the image data. In some embodiments, the signal processor 195 may be provided in a processor external to the image sensor 100.

[0048] Figure 2 is a circuit diagram of an image sensor according to an embodiment.

[0049] Refer to Figure 2, the image sensor 100 may include a plurality of photodiodes PD, a plurality of transfer transistors TX, a floating diffusion node FDN, a conversion gain transistor DCG, a reset transistor RX, a source follower transistor SF, and a selection transistor SEL.

[0050] The transfer transistor TX, the conversion gain transistor DCG, the reset transistor RX, the source follower transistor SF, and the selection transistor SEL respectively include a transfer gate TG, a conversion gain gate, a reset gate, a source follower gate SFG, and a selection gate.

[0051] According to some embodiments, the transfer gate TG may be a vertical gate. According to some embodiments, the conversion gain gate, the reset gate, the source follower gate SFG, and the selection gate may each be a planar gate.

[0052] The photodiode PD may generate charges in proportion to the amount of incident light. The photodiode PD may generate electrons (i.e., negative charges) and holes (i.e., positive charges) in response to the incident light.

[0053] According to some embodiments, eight photodiodes PD may be provided. The eight photodiodes PD may share one floating diffusion node FDN, a reset transistor RX, a conversion gain transistor DCG, a source follower transistor SF, and a selection transistor SEL. However, providing eight photodiodes PD is only an exemplary embodiment, and the number of photodiodes PD is not limited thereto.

[0054] The transfer gate TG is disposed between the photodiode PD and the floating diffusion node FDN, and may transfer the charges generated by the photodiode PD to the floating diffusion node FDN. The transfer transistor TX may include a transfer gate TG, a drain region connected to the photodiode PD, and a source region connected to the floating diffusion node FDN.

[0055] The conversion gain transistor DCG may include a conversion gain gate, a source region connected to the drain region of the reset transistor RX, and a source region connected to the floating diffusion node FDN.

[0056] The conversion gain transistor DCG may change the capacitance of the floating diffusion node FDN according to a conversion gain signal. When the conversion gain transistor DCG is turned on, the capacitance of the floating diffusion node FDN increases, so the image sensor 100 may operate in a low conversion gain mode. Conversely, when the conversion gain transistor DCG is turned off, the capacitance of the floating diffusion node FDN decreases, so the image sensor 100 may operate in a high conversion gain mode.

[0057] The reset transistor RX may include a reset gate, a source region connected to a power supply voltage Vpix, and a drain region connected to a source region of the conversion gain transistor DCG. When the reset transistor RX is turned on according to a reset control signal and the conversion gain transistor DCG is turned on according to a conversion gain signal, the floating diffusion node FDN may be reset based on the power supply voltage Vpix. Specifically, the charge accumulated in the floating diffusion node FDN may be discharged, and the floating diffusion node FDN may be reset. At this time, a reset signal corresponding to the voltage level of the floating diffusion node FDN may be output.

[0058] The source follower transistor SF may include a source follower gate SFG connected to the floating diffusion node FDN, a source follower source region SFS connected to a source region of the selection transistor SEL, and a drain region connected to the power supply voltage Vpix.

[0059] The potential of the floating diffusion node FDN changes according to the amount of charge accumulated in the floating diffusion node FDN, and the source follower transistor SF may amplify the potential change in the floating diffusion node FDN and output the amplified potential change to the source follower source region SFS.

[0060] A gate-source capacitor Cgs may be formed between the source follower transistor SF and the floating diffusion node FDN. The gate-source capacitor Cgs is different from the parasitic capacitance applied to the floating diffusion node FDN. The gate-source capacitor Cgs may reduce the value of the parasitic capacitance applied to the floating diffusion node FDN. As a result, the conversion gain may increase due to the gate-source capacitor Cgs.

[0061] The selection transistor SEL may include a selection gate, a source region connected to a source of the source follower transistor SF, and a drain region connected to a line of the output voltage Vout.

[0062] Figure 3 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0063] Specifically, the image sensor EX1 may be Figure 1 an embodiment of the image sensor 100. The image sensor EX1 may include Figure 1 the pixels PX. The image sensor EX1 may include a top layer 200, an intermediate layer 300, and a bottom layer 400.

[0064] In the image sensor EX1, the intermediate layer 300 and the top layer 200 may be stacked on the bottom layer 400. The image sensor EX1 may include three layers with the intermediate layer 300 and the top layer 200 stacked on the bottom layer 400. The image sensor EX1 may include three layers where the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other. The image sensor EX1 may include a floating diffusion (FD) wiring structure FLS and a shielding structure SHS.

[0065] The transistors described below may include planar transistors, multi-bridge channel (MBC) transistors, gate-all-around (GAA) transistors, or fin field-effect transistors (fin FETs).

[0066] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side landing pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first floating diffusion (FD) wiring structure 210, and a first shielding structure 220.

[0067] The first substrate 201 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate 201 may include a first front surface 201f and a first back surface 201b opposite to the first front surface 201f. A photodiode PD (see Figure 2 ) may be disposed on the first substrate 201.

[0068] According to some embodiments, one photodiode PD (see Figure 2 ) may be provided corresponding to one color filter 217 and one lens 219. According to some embodiments, a plurality of photodiodes PD (see Figure 2 ) may be arranged corresponding to one color filter 217 and one lens 219.

[0069] The color filter 217 and the lens 219 may be disposed on the first back surface 201b of the first substrate 201. The color filter 217 and the lens 219 may be sequentially stacked on the first back surface 201b of the first substrate 201.

[0070] The pixel isolation layer 215 may be provided within the first substrate 201. The pixel isolation layer 215 may be used to Figure 1Multiple pixels PX therein are isolated from each other. The pixel isolation layer 215 may include two or more materials. The pixel isolation layer 215 may include, for example, a semiconductor material and an insulating material having a refractive index different from that of the first substrate 201. The semiconductor material may include, for example, a polysilicon film doped with impurities or a silicon germanium film. The impurities doped into the polysilicon film or the silicon germanium film may be, for example, one of boron, phosphorus, and arsenic. The insulating material may include, for example, silicon oxide. The pixel isolation layer 215 may include a metal film instead of a semiconductor material.

[0071] The first transistor 203 may be disposed on the first front surface 201f. For example, the first transistor 203 may include, but is not limited to, a transfer transistor TX (see Figure 2 ). When the first transistor 203 corresponds to the transfer transistor TX (see Figure 2 ), a part of the first source and drain regions constituting the first transistor 203 may be a floating diffusion node FDN. For convenience, illustrations of other regions in the first source and drain regions are omitted.

[0072] In this specification, the first horizontal direction D1 is defined as the direction parallel to the first front surface 201f of the first substrate 201, the second horizontal direction D2 is defined as the direction parallel to the first front surface 201f of the first substrate 201 and intersecting the first horizontal direction D1, and the vertical direction D3 is defined as the direction perpendicular to the first front surface 201f of the first substrate 201.

[0073] The first contact plug 206 and the first wiring layer 205 may be connected to the first transistor 203. The first contact plug 206 and the first wiring layer 205 may be disposed on the first front surface 201f of the first substrate 201. A plurality of first wiring layers 205 may be provided. Among the plurality of first wiring layers 205, two different first wiring layers 205 in the first wiring layer 205 may be located at different vertical levels. In other words, the plurality of first wiring layers 205 may form a multi-layer structure.

[0074] In this specification, the term "vertical level" is defined as the height from an arbitrary point to a specific point in the vertical direction D3. For example, the vertical level of the first wiring layer 205 may correspond to the height from the third back surface 401b of the third substrate 401 to the first wiring layer 205 in the vertical direction D3.

[0075] In this specification, the expression "connected" corresponds to the concept that includes not only the direct contact between one component and another component but also the indirect connection through another component. In addition, the expression "connected" corresponds to the concept that includes the electrical connection between one component and another component.

[0076] The first contact plug 206 can connect at least two first wiring layers 205 at different vertical levels to each other. The first contact plug 206 can connect the first wiring layer 205 and the first front-side bonding pad 204 to each other. The first front-side bonding pad 204 can be disposed at the bottom of the top layer 200. The first front-side bonding pad 204 can be connected to the second front-side bonding pad 304. The first wiring layer 205 and the first contact plug 206 can be connected to the second front-side bonding pad 304 through the first front-side bonding pad 204. The first wiring layer 205, the first contact plug 206, and the first front-side bonding pad 204 can include a metal (e.g., copper (Cu) or tungsten (W)).

[0077] The floating diffusion node FDN can be disposed within the first substrate 201. The floating diffusion node FDN can correspond to Figure 2 the floating diffusion node FDN. The floating diffusion node FDN can be a region doped with impurities in the first substrate 201. The impurities can have P-type conductivity or N-type conductivity.

[0078] The first via plug 213 can be connected to the floating diffusion node FDN. The first via plug 213 can be disposed on the first front surface 201f of the first substrate 201. The first via plug 213 can include a metal (e.g., Cu or W).

[0079] The first FD wiring structure 210 can be connected to the first via plug 213. The first FD wiring structure 210 can be disposed on the first front surface 201f of the first substrate 201. The first FD wiring structure 210 can be connected to the floating diffusion node FDN through the first via plug 213. The first FD wiring structure 210 can be connected to the floating diffusion node FDN.

[0080] The first FD wiring structure 210 can include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. A plurality of first FD wiring layers 207 can be provided. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 in the first FD wiring layer 207 can be located at different vertical levels. In other words, the plurality of first FD wiring layers 207 can form a multilayer structure. At least one of the plurality of first FD wiring layers 207 and at least one of the plurality of first wiring layers 205 can be located at the same vertical level.

[0081] The first FD plug 208 can connect at least two first FD wiring layers 207 at different vertical levels to each other. The first FD plug 208 can connect the first FD wiring layer 207 and the first FD bonding pad 209 to each other. The first FD bonding pad 209 can be disposed at the bottom of the top layer 200. The first FD wiring layer 207 and the first FD plug 208 can be connected to the second FD bonding pad 309 through the first FD bonding pad 209. The first FD wiring layer 207, the first FD plug 208, and the first FD bonding pad 209 can include a metal (e.g., Cu or W).

[0082] Figure 4 is a plan view taken along Figure 3 the line X-X'.

[0083] Referring to Figure 3 and Figure 4 , the first shielding structure 220 can be disposed on the first front surface 201f of the first substrate 201. The first shielding structure 220 can include a first shielding wiring layer 221, a first shielding plug 222, and a first shielding bonding pad 223.

[0084] A plurality of first shielding wiring layers 221 can be provided. Among the plurality of first shielding wiring layers 221, two different first shielding wiring layers in the first shielding wiring layer 221 can be located at different vertical levels. In other words, the plurality of first shielding wiring layers 221 can form a multi-layer structure. At least one of the plurality of first shielding wiring layers 221 and at least one of the plurality of first wiring layers 205 can be located at the same vertical level.

[0085] The first shielding plug 222 can connect at least two first shielding wiring layers 221 at different vertical levels to each other. The first shielding plug 222 can connect the first shielding wiring layer 221 and the first shielding bonding pad 223 to each other. The first shielding bonding pad 223 can be disposed at the bottom of the top layer 200. The first shielding wiring layer 221 and the first shielding plug 222 can be connected to the second shielding bonding pad 323 through the first shielding bonding pad 223. The first shielding wiring layer 221, the first shielding plug 222, and the first shielding bonding pad 223 can include a metal (e.g., Cu or W).

[0086] The first shielding structure 220 can be spaced apart from the first FD wiring structure 210 in a first horizontal direction D1 and a second horizontal direction D2. The first shielding structure 220 can be spaced apart from the first wiring layer 205 and the first contact plug 206 in the first horizontal direction D1 and the second horizontal direction D2. The first shielding structure 220 can surround the floating diffusion node FDN and the first FD wiring structure 210. Specifically, the first shielding wiring layer 221 can surround the first FD wiring layer 207 at the same vertical level as the first shielding wiring layer 221. A plurality of first shielding wiring layers 221 can be respectively arranged at all the vertical levels where a plurality of first FD wiring layers 207 are respectively arranged. Accordingly, each of the plurality of first FD wiring layers 207 can be surrounded by at least one first shielding wiring layer 221.

[0087] Return reference Figure 3 , the first insulating layer 211 can be disposed on a first front surface 201f of the first substrate 201. The first wiring layer 205, the first contact plug 206, the first FD wiring structure 210, the first shielding structure 220, and the first via plug 213 can be arranged in the first insulating layer 211. However, the first insulating layer 211 may not cover the bottom surfaces of the first front-side bonding pad 204, the first FD bonding pad 209, and the first shielding bonding pad 223. The first insulating layer 211 can have a single-layer structure or a multi-layer structure. The first insulating layer 211 can include an insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof).

[0088] The intermediate layer 300 can include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a back-side bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front-side bonding pad 304, a second via plug 313, a second floating diffusion (FD) wiring structure 310, a second shielding structure 320, and a second insulating layer 311.

[0089] The first front-side bonding pad 204 included in the top layer 200 can be bonded to the second front-side bonding pad 304 included in the intermediate layer 300. The first FD bonding pad 209 included in the top layer 200 can be bonded to the second FD bonding pad 309 included in the intermediate layer 300. The first shielding bonding pad 223 included in the top layer 200 can be bonded to the second shielding bonding pad 323 included in the intermediate layer 300. The first insulating layer 211 included in the top layer 200 can be bonded to the second insulating layer 311 included in the intermediate layer 300. The top layer 200 and the intermediate layer 300 can have a boundary surface F-F at which the front surfaces of the top layer 200 and the intermediate layer 300 are bonded to each other.

[0090] The second substrate 301 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second substrate 301 may include a second front surface 301f and a second back surface 301b opposite to the second front surface 301f. The second transistor 303 may be formed on the second front surface 301f.

[0091] The second transistor 303 may be disposed on the second front surface 301f. The second transistor 303 may include Figure 2 any one of the transistors described in Figure 2 except for the source follower transistor SF (see Figure 2 ). For example, the second transistor 303 may include a conversion gain transistor DCG (see Figure 2 ), a reset transistor RX (see Figure 2 ), and a selection transistor SEL (see Figure 3 ). In

[0092] Figure 2 Figure 2 Figure 2 Figure 2

[0093]

[0093]

[0094]

[0095] The second contact plug 306 can connect at least two second wiring layers 305 at different vertical levels to each other. The second contact plug 306 can connect the second wiring layer 305 and the second front-side bonding pad 304 to each other. The second front-side bonding pad 304 can be disposed on top of the intermediate layer 300. The second front-side bonding pad 304 can be connected to the first front-side bonding pad 204. The second wiring layer 305 and the second contact plug 306 can be connected to the first front-side bonding pad 204 through the second front-side bonding pad 304. The second wiring layer 305, the second contact plug 306, the second via plug 313, and the second front-side bonding pad 304 can include a metal (e.g., Cu or W).

[0096] The second FD wiring structure 310 can be connected to the second via plug 313. The second FD wiring structure 310 can be disposed on the second front surface 301f of the second substrate 301. The second FD wiring structure 310 can be connected to the source follower gate SFG through the second via plug 313. The second FD wiring structure 310 can be connected to the source follower gate SFG.

[0097] The second FD wiring structure 310 can include a second FD wiring layer 307, a second FD plug 308, and a second FD bonding pad 309. A plurality of second FD wiring layers 307 can be provided. Among the plurality of second FD wiring layers 307, two different second FD wiring layers 307 in the second FD wiring layer 307 can be located at different vertical levels. In other words, the plurality of second FD wiring layers 307 can form a multi-layer structure. At least one of the plurality of second FD wiring layers 307 and at least one of the plurality of second wiring layers 305 can be located at the same vertical level.

[0098] The second FD plug 308 can connect at least two second FD wiring layers 307 at different vertical levels to each other. The second FD plug 308 can connect the second FD wiring layer 307 and the second FD bonding pad 309 to each other. The second FD bonding pad 309 can be disposed on top of the intermediate layer 300. The second FD bonding pad 309 can connect the second FD wiring layer 307 and the second FD plug 308 to the first FD bonding pad 209. The second FD wiring layer 307, the second FD plug 308, and the second FD bonding pad 309 can include a metal (e.g., Cu or W).

[0099] Refer to Figure 3 and Figure 4 and, the second shielding structure 320 can be disposed on the second front surface 301f of the second substrate 301. The second shielding structure 320 can include a second shielding wiring layer 321, a second shielding plug 322, and a second shielding bonding pad 323.

[0100] A plurality of second shielding wiring layers 321 can be provided. Among the plurality of second shielding wiring layers 321, two different second shielding wiring layers 321 in the second shielding wiring layer 321 can be located at different vertical levels. In other words, the plurality of second shielding wiring layers 321 can form a multi-layer structure. At least one of the plurality of second shielding wiring layers 321 and at least one of the plurality of second wiring layers 305 can be located at the same vertical level.

[0101] The second shielding plug 322 can connect at least two second shielding wiring layers 321 at different vertical levels to each other. The second shielding plug 322 can connect the second shielding wiring layer 321 and the second shielding bonding pad 323 to each other. The second shielding bonding pad 323 can be provided at the top of the intermediate layer 300. The second shielding wiring layer 321 and the second shielding plug 322 can be connected to the first shielding bonding pad 223 through the second shielding bonding pad 323. The second shielding wiring layer 321, the second shielding plug 322, and the second shielding bonding pad 323 can include a metal (e.g., Cu or W).

[0102] The second shielding structure 320 can be spaced apart from the second FD wiring structure 310 in the first horizontal direction D1 and the second horizontal direction D2. The second shielding structure 320 can be spaced apart from the second wiring layer 305 and the second contact plug 306 in the first horizontal direction D1 and the second horizontal direction D2. The second shielding structure 320 can surround the second FD wiring structure 310. Specifically, the second shielding wiring layer 321 can surround the second FD wiring layer 307 at the same vertical level as the second shielding wiring layer 321. The plurality of second shielding wiring layers 321 can be respectively arranged at all vertical levels where the plurality of second FD wiring layers 307 are respectively arranged. Therefore, each of the plurality of second FD wiring layers 307 can be surrounded by at least one second shielding wiring layer 321.

[0103] The second shielding structure 320 can be connected to the source follower source region SFS through the source follower via SFV. The second shielding structure 320 can be connected to the source follower source region SFS.

[0104] Return to reference Figure 3, the second insulating layer 311 may be disposed on the second front surface 301f of the second substrate 301. The second insulating layer 311 may also be disposed between the backside bonding through hole 330 and the second substrate 301. The second wiring layer 305, the second contact plug 306, the second FD wiring structure 310, the second shielding structure 320, and the second via plug 313 are disposed in the second insulating layer 311. However, the second insulating layer 311 may not cover the top surfaces of the second front-side bonding pad 304, the second FD bonding pad 309, and the second shielding bonding pad 323. The second insulating layer 311 may have a single-layer structure or a multi-layer structure. The second insulating layer 311 may include an insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof).

[0105] Referring to Figure 3 and Figure 4 , the first FD wiring structure 210 and the second FD wiring structure 310 may together constitute the FD wiring structure FLS. The first shielding structure 220 and the second shielding structure 320 may together constitute the shielding structure SHS.

[0106] The FD wiring structure FLS may be connected to the floating diffusion node FDN and the source follower gate SFG. The shielding structure SHS may be connected to the source follower source region SFS. The shielding structure SHS may surround the floating diffusion node FDN and the FD wiring structure FLS. In a plan view, the floating diffusion node FDN and the FD wiring structure FLS may be disposed within the shielding structure SHS.

[0107] Return reference Figure 3 , the bottom layer 400 may include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, a third contact plug 406, a third front-side bonding pad 409, a third via plug 413, and a third insulating layer 411.

[0108] The backside bonding through hole 330 included in the intermediate layer 300 may be bonded to the third front-side bonding pad 409 included in the bottom layer 400. The second substrate 301 and the second insulating layer 311 included in the intermediate layer 300 may be bonded to the third insulating layer 411 included in the bottom layer 400. The intermediate layer 300 and the bottom layer 400 may have a boundary surface B-F at which the back surface of the intermediate layer 300 and the front surface of the bottom layer 400 are bonded to each other.

[0109] The third substrate 401 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The third substrate 401 may include a third front surface 401f and a third back surface 401b opposite to the third front surface 401f. The third transistors 403 may be disposed on the third front surface 401f. In Figure 3In [the figure], the fourth source and drain regions forming the third transistor 403 are disposed in the third substrate 401, but their illustration is omitted for convenience.

[0110] The third contact plug 406 and the third wiring layer 405 can be connected to the third transistor 403 through the third via plug 413. The third wiring layer 405 can be connected to the third front-side bonding pad 409 through the third contact plug 406. The third contact plug 406 and the third wiring layer 405 can be connected to the third front-side bonding pad 409. The third front-side bonding pad 409, the third wiring layer 405, the third contact plug 406, and the third via plug 413 can include a metal (e.g., Cu or W).

[0111] The third insulating layer 411 can be disposed on the third front surface 401f of the third substrate 401. The third wiring layer 405, the third contact plug 406, and the third via plug 413 can be disposed in the third insulating layer 411. However, the third insulating layer 411 may not cover the top surface of the third front-side bonding pad 409. The third insulating layer 411 can have a single-layer structure or a multi-layer structure. The third insulating layer 411 can include an insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof).

[0112] An image sensor EX1 according to an embodiment of the present disclosure can include a floating diffusion node FDN, an FD wiring structure FLS connected to the floating diffusion node FDN and a source follower gate SFG, and a shielding structure SHS connected to a source follower source region SFS. The shielding structure SHS can be spaced apart from the floating diffusion node FDN and the FD wiring structure FLS in a first horizontal direction D1 and a second horizontal direction D2. The shielding structure SHS can surround the floating diffusion node FDN and the FD wiring structure FLS. Accordingly, a capacitance can be formed between the FD wiring structure FLS and the shielding structure SHS. The capacitance can correspond to the gate-source capacitance Cgs described above with reference to Figure 2 Since Figure 2 the gate-source capacitance Cgs is formed between the FD wiring structure FLS and the shielding structure SHS, the conversion gain can be increased.

[0113] Figure 5 is a plan view taken along the line X-X' of Figure 3 . Hereinafter, the arrangement of the shielding structure SHS will be described with reference to Figure 3 and Figure 5 . Hereinafter, only the description different from the description given above with reference to Figure 3 and Figure 4 will be given, and the description the same as the description given above can be omitted.

[0114] Refer to Figure 3 and Figure 5, the shielding structure SHS may not surround the floating diffusion node FDN and the FD wiring structure FLS. The first shielding structure 220 included in the shielding structure SHS may be disposed on both sides of the FD wiring structure FLS and extend in the second horizontal direction D2. Optionally, the first shielding structure 220 included in the shielding structure SHS may be disposed on both sides of the FD wiring structure FLS and extend in the first horizontal direction D1.

[0115] The second shielding structure 320 included in the shielding structure SHS may be disposed on both sides of the FD wiring structure FLS and extend in the second horizontal direction D2. Optionally, the second shielding structure 320 included in the shielding structure SHS may be disposed on both sides of the FD wiring structure FLS and extend in the first horizontal direction D1. The first shielding structure 220 and the second shielding structure 320 may be stacked on each other in the vertical direction D3 or may not be stacked on each other in the vertical direction D3. However, the first shielding structure 220 and the second shielding structure 320 may be connected to each other.

[0116] Optionally, the first shielding structure 220 and the second shielding structure 320 may each be provided only on one side of the FD wiring structure FLS and extend in the first horizontal direction D1 or the second horizontal direction D2. Even in this case, a capacitance may be formed between the shielding structure SHS including the first shielding structure 220 and the second shielding structure 320 and the FD wiring structure FLS.

[0117] According to an embodiment, the first shielding structures 220 disposed on both sides of the FD wiring structure FLS may be connected to each other. According to an embodiment, the second shielding structures 320 disposed on both sides of the FD wiring structure FLS may be connected to each other.

[0118] In the image sensor EX1 according to an embodiment of the present disclosure, the shielding structure SHS may not surround the FD wiring structure FLS. The first shielding structure 220 and the second shielding structure 320 of the shielding structure SHS may each be disposed on both sides or only one side of the FD wiring structure FLS. Therefore, the area occupied by the shielding structure SHS in the image sensor EX1 can be reduced. In addition, even in this case, a capacitance may be formed between the shielding structure SHS and the FD wiring structure FLS, and the conversion gain can be increased. For the above reasons, the integration degree and the conversion gain of the image sensor EX1 can be improved.

[0119] Figure 6 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0120] Specifically, the image sensor EX2 may be Figure 1 an embodiment of the image sensor 100. The image sensor EX2 may include Figure 1The pixel PX. Except that the top layer 200 is different from the top layer 200 of the image sensor EX1, the image sensor EX2 can be Figure 3 substantially the same as the image sensor EX1 of Figure 6 In Figure 3 and Figure 4 the description given above with reference to

[0121] The image sensor EX2 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX2 may include three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other.

[0122] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220.

[0123] The first FD wiring structure 210 may include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. A plurality of first FD wiring layers 207 may be provided. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 in the first FD wiring layer 207 may be located at different vertical levels. In other words, the plurality of first FD wiring layers 207 may form a multi-layer structure.

[0124] For example, any one of the plurality of first FD wiring layers 207 may be provided at a first vertical level LV1, and another one of the plurality of first FD wiring layers 207 may be provided at a second vertical level LV2. The first vertical level LV1 and the second vertical level LV2 may be located between the first front surface 201f of the first substrate 201 and the bottom surface of the top layer 200. The second vertical level LV2 may be different from the first vertical level LV1. For example, the second vertical level LV2 may be lower than the first vertical level LV1.

[0125] Any one of the plurality of first wiring layers 205 may be provided at a first vertical level LV1, and another one of the plurality of first wiring layers 205 may be provided at a second vertical level LV2. According to an embodiment, in addition to the first vertical level LV1 and the second vertical level LV2, there may be other vertical levels at which the first FD wiring layer 207 and the first wiring layer 205 are arranged. This may vary according to the embodiment of the image sensor EX2 to be manufactured.

[0126] The first shielding structure 220 may include a first shielding wiring layer 221, a first shielding plug 222, and a first shielding bonding pad 223. The first shielding wiring layer 221 may be disposed at a part of the vertical level where the first FD wiring layer 207 is arranged, and may not be disposed at some other vertical levels. For example, as Figure 6 shown in, the first shielding wiring layer 221 may be disposed at the first vertical level LV1 and may not be disposed at the second vertical level LV2. The first shielding bonding pad 223 and the first shielding wiring layer 221 disposed at the first vertical level LV1 may be connected to each other through the first shielding plug 222. The first shielding wiring layer 221 disposed at the first vertical level LV1 may surround the first FD wiring structure 210.

[0127] The description of the first shielding wiring layer 221 may also be similarly applied to the second shielding wiring layer 321 that constitutes the intermediate layer 300. In other words, the second shielding wiring layer 321 may be disposed at a part of the vertical level where the second FD wiring layer 307 is arranged, and may not be disposed at some other vertical levels. This may vary according to the embodiments of the image sensor EX2 to be manufactured. However, for the sake of simplicity of explanation, the repeated description of the second shielding wiring layer 321 and the second FD wiring layer 307 may be omitted.

[0128] According to an embodiment of the present disclosure, the first shielding wiring layer 221 of the image sensor EX2 may be disposed at a part of the vertical level where the first FD wiring layer 207 is arranged, and may not be arranged at some other vertical levels. For example, the first shielding wiring layer 221 may be disposed at the first vertical level LV1 and may not be disposed at the second vertical level LV2. In other words, the first shielding wiring layer 221 may be omitted at a specific vertical level. Therefore, it is possible to determine whether to omit the first shielding wiring layer 221 according to the integration degree of various wirings arranged at each vertical level. Even in this case, a capacitance may be formed between the shielding structure SHS and the FD wiring structure FLS. Therefore, the conversion gain of the image sensor EX2 can be improved, and at the same time, the wiring freedom can be increased.

[0129] Figure 7 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0130] Specifically, the image sensor EX3 may be Figure 1 an embodiment of the image sensor 100. The image sensor EX3 may include Figure 1 the pixels PX. Except that the top layer 200 and the intermediate layer 300 of the image sensor EX3 are different from the top layer 200 and the intermediate layer 300 of the image sensor EX1, the image sensor EX3 may be substantially the same as Figure 3 the image sensor EX1. In Figure 7 it is the same as that referred to aboveFigure 3 and Figure 4 A description identical to the description given may be briefly given or omitted.

[0131] Referring to Figure 7 , the image sensor EX3 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX3 may include three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other.

[0132] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220.

[0133] The first FD wiring structure 210 may include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. A plurality of first FD wiring layers 207 may be provided. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 in the first FD wiring layer 207 may be located at different vertical levels. In other words, the plurality of first FD wiring layers 207 may form a multi-layer structure.

[0134] For example, any one of the plurality of first FD wiring layers 207 may be provided at a first vertical level LV1, and another one of the plurality of first FD wiring layers 207 may be provided at a second vertical level LV2. The first vertical level LV1 and the second vertical level LV2 may be located between the first front surface 201f of the first substrate 201 and the bottom surface of the top layer 200. The second vertical level LV2 may be different from the first vertical level LV1. For example, the second vertical level LV2 may be lower than the first vertical level LV1.

[0135] Any one of the plurality of first wiring layers 205 may be provided at a first vertical level LV1, and another one of the plurality of first wiring layers 205 may be provided at a second vertical level LV2. According to an embodiment, in addition to the first vertical level LV1 and the second vertical level LV2, there may be other vertical levels at which the first FD wiring layer 207 and the first wiring layer 205 are arranged. This may vary according to the embodiment of the image sensor EX3 to be manufactured.

[0136] The first shielding structure 220 may include a first shielding wiring layer 221, a first shielding plug 222, and a first shielding bonding pad 223. A plurality of first shielding wiring layers 221 may be provided. Any one of the first shielding wiring layers 221 may be provided at a first vertical level LV1, and another one of the first shielding wiring layers 221 may be provided at a second vertical level LV2.

[0137] The horizontal width of the first shielding wiring layer 221 provided at the first vertical level LV1 may be different from the horizontal width of the first shielding wiring layer 221 provided at the second vertical level LV2. The horizontal width of the first shielding wiring layer 221 refers to the width of the first shielding wiring layer 221 in the first horizontal direction D1 or the width of the first shielding wiring layer 221 in the second horizontal direction D2.

[0138] Although Figure 7 the first shielding wiring layer 221 shown at different vertical levels has different horizontal widths from each other, the first shielding wiring layer 221 at the same vertical level may have different horizontal widths from each other.

[0139] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a backside bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front side bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shielding structure 320, and a second insulating layer 311.

[0140] The second FD wiring structure 310 may include a second FD wiring layer 307, a second FD plug 308, and a second FD bonding pad 309. A plurality of second FD wiring layers 307 may be provided. Among the plurality of second FD wiring layers 307, two different second FD wiring layers 307 in the second FD wiring layers 307 may be located at different vertical levels. In other words, the plurality of second FD wiring layers 307 may form a multilayer structure.

[0141] For example, any one of the plurality of second FD wiring layers 307 may be provided at the third vertical level LV3, and another one of the plurality of second FD wiring layers 307 may be provided at the fourth vertical level LV4. The third vertical level LV3 and the fourth vertical level LV4 may be located between the top surface of the intermediate layer 300 and the second front surface 301f of the second substrate 301. The third vertical level LV3 may be different from the fourth vertical level LV4. For example, the fourth vertical level LV4 may be lower than the third vertical level LV3.

[0142] Any one of the plurality of second wiring layers 305 may be provided at the third vertical level LV3, and another one of the plurality of second wiring layers 305 may be provided at the fourth vertical level LV4. According to an embodiment, in addition to the third vertical level LV3 and the fourth vertical level LV4, there may be other vertical levels at which the second FD wiring layer 307 and the second wiring layer 305 are arranged. This may vary according to the embodiment of the image sensor EX3 to be manufactured.

[0143] The second shielding structure 320 may include a second shielding wiring layer 321, second shielding plugs 322, and second shielding bonding pads 323. A plurality of second shielding wiring layers 321 may be provided. Any one of the second shielding wiring layers 321 may be provided at a third vertical level LV3, and another one of the second shielding wiring layers 321 may be provided at a fourth vertical level LV4.

[0144] The minimum distance between the second FD wiring layer 307 provided at the third vertical level LV3 and the second shielding wiring layer 321 provided at the third vertical level LV3 may be a first distance L1. The first distance L1 may be a distance in a first horizontal direction D1 or a second horizontal direction D2. The maximum distance between the second FD wiring layer 307 provided at the third vertical level LV3 and the second shielding wiring layer 321 provided at the third vertical level LV3 may be a second distance L2. The second distance L2 may be a distance in the first horizontal direction D1 or the second horizontal direction D2.

[0145] The horizontal distance between the second FD wiring layer 307 provided at the fourth vertical level LV4 and the second shielding wiring layer 321 provided at the fourth vertical level LV4 may be a third distance L3. The third distance L3 may be a distance in the first horizontal direction D1 or the second horizontal direction D2. The third distance L3 may vary.

[0146] The first distance L1 and the second distance L2 may be different from each other. In other words, at the same vertical level, the horizontal distance between the second FD wiring layer 307 and the second shielding wiring layer 321 may vary. Additionally, the third distance L3 may be different from the first distance L1 and the second distance L2. In other words, at different vertical levels, the horizontal distance between the second FD wiring layer 307 and the second shielding wiring layer 321 may vary. In other words, the horizontal distance between the FD wiring structure FLS and the shielding structure SHS may vary.

[0147] An image sensor EX3 according to an embodiment of the present disclosure may include an FD wiring structure FLS and a shielding structure SHS. The horizontal distance between the FD wiring structure FLS and the shielding structure SHS may vary. Even in such a case, a capacitance may be formed between the shielding structure SHS and the FD wiring structure FLS. Therefore, the conversion gain of the image sensor EX3 may be improved while the wiring freedom may be increased.

[0148] Figure 8 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment. Figure 9 is a plan view taken along the Figure 8 line Y-Y'.

[0149] Specifically, the image sensor EX4 may be Figure 1An embodiment of the image sensor 100. The image sensor EX4 may include Figure 1 pixels PX. The image sensor EX4 may be substantially the same as the image sensor EX1, except that the intermediate layer 300 is different from the intermediate layer 300 of the image sensor EX1. Figure 3 In Figure 8 and Figure 9 , descriptions that are the same as those given above with reference to Figure 3 and Figure 4 are briefly given or omitted.

[0150] Referring to Figure 8 and Figure 9 , the image sensor EX4 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX4 may include three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other.

[0151] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220.

[0152] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a source follower bonding pad SLP, a back-side bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front-side bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shielding structure 320, and a second insulating layer 311.

[0153] The source follower bonding pad SLP may be disposed between the source follower source region SFS and the source follower via SFV. The source follower bonding pad SLP may connect the source follower source region SFS and the source follower via SFV. At least a part of the source follower bonding pad SLP may be inserted into the source follower source region SFS. The shielding structure SHS may be connected to the source follower source region SFS through the source follower via SFV and the source follower bonding pad SLP. The shielding structure SHS may be connected to the source follower source region SFS.

[0154] The vertical level of the top surface of the source follower bonding pad SLP can be substantially the same as the vertical level of the top surface of the second transistor 303 and the vertical level of the top surface of the source follower gate SFG. In this specification, the expression "substantially the same" can mean not only mathematically the same but also include the concept of the error range in the process. The top surface of the source follower bonding pad SLP can be coplanar with the top surface of the second transistor 303 and the top surface of the source follower gate SFG.

[0155] In a plan view, the source follower bonding pad SLP can surround the source follower gate SFG. In a plan view, the source follower bonding pad SLP can have various shapes (such as a polygonal shape, a circular shape, or an oval shape). The source follower bonding pad SLP can be spaced apart from the source follower gate SFG in a first horizontal direction D1 and a second horizontal direction D2.

[0156] The source follower bonding pad SLP can include the same material as the source follower gate SFG. The source follower bonding pad SLP and the source follower gate SFG can include the same material. The source follower bonding pad SLP can include a conductive material. For example, the source follower bonding pad SLP can include polysilicon doped with impurities.

[0157] An image sensor EX4 according to an embodiment of the present disclosure can include a source follower bonding pad SLP disposed between a source follower source region SFS and a source follower via SFV. The source follower bonding pad SLP can connect a shielding structure SHS and the source follower source region SFS. In a plan view, the source follower bonding pad SLP can surround the source follower gate SFG. Accordingly, a capacitance can also be formed between the source follower gate SFG and the source follower bonding pad SLP and between the source follower gate SFG and the shielding structure SHS. Accordingly, the capacitance formed between the shielding structure SHS and the FD wiring structure FLS can become larger. Accordingly, the conversion gain of the image sensor EX4 can be further improved.

[0158] Figure 10 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0159] Specifically, the image sensor EX5 can be Figure 1 an embodiment of the image sensor 100. The image sensor EX5 can include Figure 1 the pixels PX. Except that the intermediate layer 300 of the image sensor EX5 is different from the intermediate layer 300 of the image sensor EX4, the image sensor EX5 can be substantially the same as Figure 8 and Figure 9 the image sensor EX4. In Figure 10 , compared with the above reference to Figure 8 and Figure 9The same description given can be briefly given or omitted.

[0160] Referring to Figure 10 , the top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220.

[0161] The intermediate layer 300 may include a device isolation layer STI, a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a source follower bonding pad SLP, a back-side bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front-side bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shielding structure 320, and a second insulating layer 311.

[0162] The device isolation layer STI may be disposed in the second substrate 301. The device isolation layer STI may provide electrical insulation between the plurality of second transistors 303. According to an embodiment, the device isolation layer STI may be disposed in contact with the source follower source region SFS. The device isolation layer STI may be inserted downward in the vertical direction D3 from the second front surface 301f of the second substrate 301.

[0163] The source follower bonding pad SLP may be disposed between the source follower source region SFS and the source follower via SFV. The source follower bonding pad SLP may connect the source follower source region SFS and the source follower via SFV. At least a part of the source follower bonding pad SLP may be inserted into the source follower source region SFS. At least another part of the source follower bonding pad SLP may be inserted into the device isolation layer STI. The source follower bonding pad SLP may be disposed on the source follower source region SFS and on the device isolation layer STI. The source follower bonding pad SLP may simultaneously contact the source follower source region SFS and the device isolation layer STI.

[0164] Figure 11 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0165] Specifically, the image sensor EX6 may be Figure 1 an embodiment of the image sensor 100. The image sensor EX6 may include Figure 1 the pixels PX. Except that the top layer 200 of the image sensor EX6 is different from the top layer 200 of the image sensor EX1, the image sensor EX6 may be substantially the same as Figure 3 the image sensor EX1. InFigure 11 In, the description that is the same as the description given above with reference to Figure 3 and Figure 4 can be given briefly or omitted.

[0166] With reference to Figure 11 , the image sensor EX6 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX6 may include three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other.

[0167] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220.

[0168] The first FD wiring structure 210 may include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. A plurality of first FD wiring layers 207 may be provided. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 in the first FD wiring layer 207 may be located at different vertical levels. In other words, the plurality of first FD wiring layers 207 may form a multi-layer structure.

[0169] For example, any one of the plurality of first FD wiring layers 207 may be provided at a first vertical level LV1, and another one of the plurality of first FD wiring layers 207 may be provided at a second vertical level LV2. The first vertical level LV1 and the second vertical level LV2 may be located between the first front surface 201f of the first substrate 201 and the bottom surface of the top layer 200. The second vertical level LV2 may be different from the first vertical level LV1. For example, the second vertical level LV2 may be lower than the first vertical level LV1.

[0170] Any one of the plurality of first wiring layers 205 may be provided at a first vertical level LV1, and another one of the plurality of first wiring layers 205 may be provided at a second vertical level LV2. According to an embodiment, in addition to the first vertical level LV1 and the second vertical level LV2, there may be other vertical levels at which the first FD wiring layer 207 and the first wiring layer 205 are arranged. This may vary according to the embodiment of the image sensor EX6 to be manufactured.

[0171] Unlike Figure 3 the image sensor EX1, Figure 11 the first shielding structure 220 of the image sensor EX6 Figure 3 may not include a first shielding wiring layer 221 (see Figure 3). Therefore, the first shielding wiring layer 221 (see Figure 3 ) can be omitted at the first vertical and horizontal LV1 and the second vertical and horizontal LV2. The first shielding structure 220 may include only the first shielding bonding pad 223.

[0172] Even when the first shielding structure 220 includes only the first shielding bonding pad 223, a capacitance can be formed between the shielding structure SHS and the FD wiring structure FLS. Therefore, the conversion gain of the image sensor EX6 can be increased, and at the same time, the wiring freedom of the image sensor EX6 can be increased.

[0173] Figure 12 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0174] Specifically, the image sensor EX7 can be Figure 1 an embodiment of the image sensor 100. The image sensor EX7 may include Figure 1 the pixels PX. Except that the top layer 200 and the intermediate layer 300 are different from the top layer 200 and the intermediate layer 300 of the image sensor EX1, the image sensor EX7 may be substantially the same as Figure 3 the image sensor EX1. In Figure 12 , the same description as that given above with reference to Figure 3 and Figure 4 may be briefly given or omitted.

[0175] Referring to Figure 12 , the image sensor EX7 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX7 may include three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other.

[0176] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220.

[0177] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a back-side bonding pad 332, a second wiring layer 305, a second contact plug 306, a second front-side bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shielding structure 320, a second connection via plug 340, and a second insulating layer 311.

[0178] The first front-side bonding pad 204 included in the top layer 200 can be bonded to the back-side bonding pad 332 included in the intermediate layer 300. The first insulating layer 211 included in the top layer 200 can be bonded to the second insulating layer 311 included in the intermediate layer 300. The top layer 200 and the intermediate layer 300 can have a boundary surface F-B, at which the front surface of the top layer 200 and the back surface of the intermediate layer 300 are bonded to each other.

[0179] The second substrate 301 can include a second front surface 301f and a second back surface 301b opposite to the second front surface 301f. The second transistor 303 and the source-follower gate SFG can be arranged on the second front surface 301f. In Figure 12 it, the second source and drain regions constituting the second transistor 303 are arranged in the second substrate 301, but their illustration is omitted for convenience.

[0180] The second wiring layer 305 and the second contact plug 306 can be connected to the second transistor 303 through the second via plug 313. The second wiring layer 305 and the second contact plug 306 can be connected to the second front-side bonding pad 304. The second wiring layer 305 and the second contact plug 306 can be connected to the back-side bonding pad 332 through the second connection via plug 340. The second connection via plug 340 can be provided in the through hole VHO' penetrating the second substrate 301.

[0181] The back-side bonding pad 332 can be disposed adjacent to the second back surface 301b of the second substrate 301. The back-side bonding pad 332 can be disposed in the upper part of the intermediate layer 300. The back-side bonding pad 332 can be connected to the first front-side bonding pad 204.

[0182] The second FD wiring structure 310 can further include a first connection via plug 314 penetrating the second substrate 301. The first connection via plug 314 can be spaced apart from the second substrate 301, and the second insulating layer 311 is disposed between the first connection via plug 314 and the second substrate 301. The second FD bonding pad 309 can be connected to the second FD wiring layer 307 and the second FD plug 308 through the first connection via plug 314. The first connection via plug 314 can be connected to the source-follower gate SFG through the second FD wiring layer 307 and the second FD plug 308.

[0183] The second shielding structure 320 can further include a shielding via plug 324 penetrating the second substrate 301. Different from Figure 3 the second shielding structure 320 of Figure 12 the second shielding structure 320 of Figure 3). The shielding via plug 324 may be spaced apart from the second substrate 301, and the second insulating layer 311 is disposed between the shielding via plug 324 and the second substrate 301. The second shielding bonding pad 323 may be connected to the second shielding wiring layer 321 and the source follower via SFV through the shielding via plug 324. The shielding via plug 324 may be connected to the source follower source region SFS through the second shielding wiring layer 321 and the source follower via hole SFV. According to an embodiment, the first shielding structure 220 and the second shielding structure 320 may be connected to each other.

[0184] The length of the first connection via plug 314 in the vertical direction may be greater than the length of the second FD plug 308 in the vertical direction. The length of the second connection via plug 340 in the vertical direction may be greater than the length of the second contact plug 306 in the vertical direction. The length of the shielding via plug 324 in the vertical direction may be greater than the length of the source follower via SFV in the vertical direction. The first connection via plug 314, the second connection via plug 340, and the shielding via plug 324 may include a metal (e.g., Cu or W).

[0185] The second insulating layer 311 may be disposed on the second back surface 301b and the second front surface 301f of the second substrate 301. The second insulating layer 311 may have a single-layer structure or a multi-layer structure. The second insulating layer 311 may not cover the top surface of the second FD bonding pad 309, the top surface of the second shielding bonding pad 323, the top surface of the backside bonding pad 332, and the bottom surface of the second front-side bonding pad 304.

[0186] Figure 13 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0187] Specifically, the image sensor EX8 may be Figure 1 an embodiment of the image sensor 100. The image sensor EX8 may include Figure 1 the pixels PX. Except that the intermediate layer 300 is different from the intermediate layer 300 of the image sensor EX7, the image sensor EX8 may be substantially the same as Figure 12 the image sensor EX7. In Figure 13 , the same description as that given above with reference to Figure 12 may be briefly given or omitted.

[0188] Referring to Figure 13 , the source follower bonding pad SLP may be disposed between the source follower source region SFS and the source follower via SFV. The source follower source region SFS and the source follower via SFV may be connected to each other through the source follower bonding pad SLP. The bottom surface of the source follower bonding pad SLP may be coplanar with the bottom surface of the source follower gate SFG and the bottom surface of the second transistor 303.

[0189] At least a portion of the source follower bonding pad SLP may be inserted into the source follower source region SFS. The shielding structure SHS may be connected to the source follower source region SFS through the source follower via SFV and the source follower bonding pad SLP. The shielding structure SHS may be connected to the source follower source region SFS.

[0190] In a plan view, similar to that in Figure 9 the source follower bonding pad SLP may surround the source follower gate SFG. In a plan view, the source follower bonding pad SLP may have various shapes (such as, a polygonal shape, a circular shape, or an oval shape). The source follower bonding pad SLP may be spaced apart from the source follower gate SFG in a first horizontal direction D1 and a second horizontal direction D2.

[0191] The source follower bonding pad SLP may include a conductive material. For example, the source follower bonding pad SLP may include polysilicon doped with impurities.

[0192] Figure 14 is a schematic cross-sectional view for describing the structure of an image sensor according to an embodiment.

[0193] Specifically, the image sensor EX9 may be Figure 1 an embodiment of the image sensor 100 of Figure 1 The image sensor EX9 may include Figure 3 the pixels PX of Figure 14 Except that the intermediate layer 300 is different from the intermediate layer 300 of the image sensor EX1, the image sensor EX9 may be substantially the same as Figure 3 the image sensor EX1 of

[0194] Referring to Figure 14 the image sensor EX9 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX9 may include three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other.

[0195] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220.

[0196] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a source follower bonding pad SLP, a backside bonding pad 332, a second wiring layer 305, a second contact plug 306, a second frontside bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shielding structure 320, a second connection via plug 340, and a second insulating layer 311.

[0197] The first frontside bonding pad 204 included in the top layer 200 may be bonded to the backside bonding pad 332 included in the intermediate layer 300. The first insulating layer 211 included in the top layer 200 may be bonded to the second insulating layer 311 included in the intermediate layer 300. The top layer 200 and the intermediate layer 300 may have a boundary surface F-B, at which the front surface of the top layer 200 and the back surface of the intermediate layer 300 are bonded to each other.

[0198] The second substrate 301 may include a second front surface 301f and a second back surface 301b opposite to the second front surface 301f. The second transistors 303 and the source follower gate SFG may be disposed on the second front surface 301f. In Figure 14 it, the second source and drain regions constituting the second transistors 303 are disposed in the second substrate 301, but their illustrations are omitted for convenience.

[0199] The second wiring layer 305 and the second contact plug 306 may be connected to the second transistors 303 through the second via plug 313. The second wiring layer 305 and the second contact plug 306 may be connected to the second frontside bonding pad 304. The second wiring layer 305 and the second contact plug 306 may be connected to the backside bonding pad 332 through the second connection via plug 340. The second connection via plug 340 may be disposed in a through hole VHO' penetrating the second substrate 301.

[0200] The backside bonding pad 332 may be disposed adjacent to the second back surface 301b of the second substrate 301. The backside bonding pad 332 may be disposed in the upper part of the intermediate layer 300. The backside bonding pad 332 may be connected to the first frontside bonding pad 204.

[0201] The second FD wiring structure 310 may further include a first connection via plug 314 penetrating the second substrate 301. The first connection via plug 314 may be spaced apart from the second substrate 301, and the second insulating layer 311 is disposed between the first connection via plug 314 and the second substrate 301.

[0202] The second FD bonding pad 309 can be connected to the second FD wiring layer 307 and the second FD plug 308 through the first connection via plug 314. According to an embodiment, the second FD wiring layer 307 connected to the first connection via plug 314 can be connected to the second FD plug 308, and the second FD plug 308 is connected to the source follower gate SFG. The first connection via plug 314 can be connected to the source follower gate SFG through the second FD wiring layer 307 and the second FD plug 308.

[0203] The length of the first connection via plug 314 in the vertical direction can be greater than the length of the second FD plug 308 in the vertical direction. The length of the second connection via plug 340 in the vertical direction can be greater than the length of the second contact plug 306 in the vertical direction. The first connection via plug 314 and the second connection via plug 340 can include a metal (e.g., Cu or W).

[0204] The second insulating layer 311 can be disposed on the second back surface 301b and the second front surface 301f of the second substrate 301. The second insulating layer 311 can have a single-layer structure or a multi-layer structure. The second insulating layer 311 may not cover the top surface of the second FD bonding pad 309, the top surface of the second shielding bonding pad 323, the top surface of the backside bonding pad 332, and the bottom surface of the second front-side bonding pad 304.

[0205] The second shielding structure 320 can further include an impurity region 350 disposed in the second substrate 301 and a shielding connection plug 352 connecting the impurity region 350 and the second shielding wiring layer 321. The impurity region 350 can be a region doped with impurities in the second substrate 301. The impurities can have P-type conductivity or N-type conductivity.

[0206] The impurity region 350 can be connected to the second shielding bonding pad 323 through the second shielding plug 322. The impurity region 350 can be connected to the second shielding wiring layer 321 through the shielding connection plug 352. In a plan view, the impurity region 350 can have an annular shape.

[0207] The second shielding wiring layer 321 can be connected to the source follower source region SFS through the source follower via SFV and the source follower bonding pad SLP. The shielding connection plug 352 can include a metal (e.g., Cu or W).

[0208] The source follower bonding pad SLP can be disposed between the source follower source region SFS and the source follower via SFV. The source follower source region SFS and the source follower via SFV can be connected to each other through the source follower bonding pad SLP. The bottom surface of the source follower bonding pad SLP can be coplanar with the bottom surface of the source follower gate SFG and the bottom surface of the second transistor 303.

[0209] At least a portion of the source follower bonding pad SLP may be inserted into the source follower source region SFS. The shielding structure SHS may be connected to the source follower source region SFS through the source follower via SFV and the source follower bonding pad SLP. The shielding structure SHS may be connected to the source follower source region SFS.

[0210] In a plan view, similar to that in Figure 9 the source follower bonding pad SLP may surround the source follower gate SFG. In a plan view, the source follower bonding pad SLP may have various shapes (such as a polygonal shape, a circular shape, or an oval shape). The source follower bonding pad SLP may be spaced apart from the source follower gate SFG in a first horizontal direction D1 and a second horizontal direction D2.

[0211] The source follower bonding pad SLP may include a conductive material. For example, the source follower bonding pad SLP may include polysilicon doped with impurities.

[0212] Figure 15A and Figure 15B are cross-sectional views for describing a method of manufacturing an Figure 3 image sensor according to an embodiment.

[0213] Specifically, the same description as that given above with reference to Figure 3 may be briefly given or omitted. Referring to Figure 15A , the top layer 200 may be prepared. The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front-side bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shielding structure 220. The first substrate 201 may include a first front surface 201f and a first back surface 201b opposite to the first front surface 201f.

[0214] The intermediate layer 300 may be prepared. The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a back-side bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front-side bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shielding structure 320, and a second insulating layer 311.

[0215] The second substrate 301 may include a second front surface 301f and a second back surface 301b opposite to the second front surface 301f. A through-hole VHO penetrating the second front surface 301f and the second back surface 301b may be formed in the second substrate 301. A backside bonding through via 330 insulated by the second insulating layer 311 may be formed in the through-hole VHO.

[0216] The first front side bonding pad 204 constituting the roof layer 200 is bonded to the second front side bonding pad 304 constituting the middle layer 300 in the direction indicated by the arrow. The first insulating layer 211 constituting the roof layer 200 is bonded to the second insulating layer 311 constituting the middle layer 300 in the direction indicated by the arrow. When the first front side bonding pad 204 and the second front side bonding pad 304 are formed of a Cu layer, the Cu pads may be bonded to each other. At this time, the first FD bonding pad 209 and the second FD bonding pad 309 may be bonded to each other, and the first shield bonding pad 223 and the second shield bonding pad 323 may be bonded to each other.

[0217] Reference Figure 15B , prepared as above Figure 15A The top layer 200 and the middle layer 300 are bonded to each other. Next, a bottom layer 400 is prepared. The bottom layer 400 may include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, a third contact plug 406, a third front side bonding pad 409, a third via plug 413 and a third insulating layer 411.

[0218] The second insulating layer 311 constituting the middle layer 300 and the second substrate 301 are bonded to the third insulating layer 411 constituting the bottom layer 400 in the direction indicated by the arrow. The backside bonding through-via 330 and the third front side bonding pad 409 may be bonded to each other. When the backside bonding through-via 330 and the third front side bonding pad 409 are formed of a Cu layer, the Cu via and the Cu pad may be bonded to each other. Through the above process, a Figure 3 Image sensor EX1.

[0219] Figures 16A to 16D is used to describe the manufacturing method according to the embodiment Figure 8 A cross-sectional view of an image sensor method. In detail, Figures 16A to 16D It is used to describe manufacturing Figure 8 FIG. 4 is a cross-sectional view of an intermediate layer 300 of an image sensor EX4.

[0220] Reference Figure 16A , a second substrate 301 may be prepared. The second substrate 301 may include a second front surface 301f and a second back surface 301b opposite to the second front surface 301f. The source follower source region SFS may be formed by performing an impurity implantation process on the second substrate 301.

[0221] After forming the photomask layer on the second front surface 301f of the second substrate 301, an exposure and development process may be performed on the photomask layer. Due to the exposure and development process, a photomask pattern PM may be formed from the photomask layer. The photomask pattern PM may include an opening OP that exposes a part of the source follower source region SFS.

[0222] An etching process may be performed on the second substrate 301 by using the photomask pattern PM as an etching mask. Due to the etching process, the part of the source follower source region SFS exposed through the opening OP is etched, and thus a recess RS (see Figure 16B ) may be formed downward in the vertical direction D3 from the second front surface 301f of the second substrate 301.

[0223] Referring to Figure 16B , the photomask pattern PM may be removed. Subsequently, a preliminary conductive layer GL covering the second front surface 301f of the second substrate 301 may be formed. The preliminary conductive layer GL may include, for example, polysilicon or metal. The preliminary conductive layer GL may fill the recess RS.

[0224] Referring to Figure 16C , the second transistor 303, the source follower gate SFG, and the source follower bonding pad SLP may be formed by patterning Figure 16B the preliminary conductive layer GL. Specifically, the second transistor 303 formed by patterning the preliminary conductive layer GL may be the transistor gate of the second transistor 303. The second transistor 303, the source follower gate SFG, and the source follower bonding pad SLP may be formed simultaneously from the preliminary conductive layer GL.

[0225] Referring to Figure 16D , subsequently, a second via plug 313, a second wiring layer 305, a second contact plug 306, a second FD wiring structure 310, a second shielding structure 320, a second front-side bonding pad 304, and a back-side bonding through hole 330 may be formed. Thus, the intermediate layer 300 of Figure 8 the image sensor EX4 may be manufactured.

[0226] Next, similar to that described with reference to Figure 15A and Figure 15B , the top layer 200 and the bottom layer 400 may be prepared, the top layer 200 and the intermediate layer 300 may be bonded to each other, and the intermediate layer 300 and the bottom layer 400 may be bonded to each other. Thus, the image sensor EX4 of Figure 8 may be manufactured.

[0227] Although non-limiting example embodiments have been specifically shown and described with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising: A top layer, comprising: a first substrate; a floating diffusion node within the first substrate; a first floating diffusion wiring structure connected to the floating diffusion node; and a first shielding structure beside the first floating diffusion wiring structure; An intermediate layer, bonded to the top layer and below the top layer, wherein the intermediate layer comprises: a second substrate; a source follower gate on the second substrate; a source follower source region within the second substrate; a second floating diffusion wiring structure connected to the first floating diffusion wiring structure and the source follower gate; a second shielding structure connected to the first shielding structure and the source follower source region; and a source follower bonding pad between the second shielding structure and the source follower source region and spaced apart from the source follower gate; and A bottom layer, bonded to the intermediate layer and below the intermediate layer, wherein the bottom layer comprises: a third substrate; and a transistor on the third substrate.

2. The image sensor according to claim 1, wherein, The first shielding structure is horizontally spaced apart from the first floating diffusion wiring structure and surrounds the first floating diffusion wiring structure, and wherein the second shielding structure is horizontally spaced apart from the second floating diffusion wiring structure and surrounds the second floating diffusion wiring structure.

3. The image sensor according to claim 1, wherein, The first floating diffusion wiring structure comprises: a first floating diffusion wiring layer at a first vertical level; and a second floating diffusion wiring layer at a second vertical level different from the first vertical level, and wherein the first shielding structure comprises: a first shielding wiring layer at only one of the first vertical level and the second vertical level.

4. The image sensor according to claim 1, wherein, The top surfaces of the source follower gate and the source follower bonding pad are coplanar with each other.

5. The image sensor according to claim 1, wherein, The first shielding structure comprises: a first shielding wiring layer at the first vertical level; and a second shielding wiring layer at a second vertical level different from the first vertical level, and wherein the horizontal distance from the first floating diffusion wiring structure to the first shielding wiring layer is different from the horizontal distance from the first floating diffusion wiring structure to the second shielding wiring layer.

6. The image sensor according to claim 1, wherein, The first shielding structure comprises: a first shielding wiring layer at the first vertical level; and a second shielding wiring layer at a second vertical level different from the first vertical level, and wherein the horizontal width of the first shielding wiring layer is different from the horizontal width of the second shielding wiring layer.

7. The image sensor according to claim 1, wherein, The intermediate layer further comprises: a device isolation layer within the second substrate and in contact with the source follower source region, and wherein at least a part of the source follower bonding pad is in contact with the device isolation layer.

8. The image sensor according to claim 1, wherein, The second floating diffusion wiring structure comprises: a second floating diffusion bonding pad bonded to the first floating diffusion bonding pad included in the first floating diffusion wiring structure; and a first connection via plug connected to the second floating diffusion bonding pad and penetrating the second substrate.

9. The image sensor according to claim 8, wherein, The second shielding structure comprises: a second shielding bonding pad bonded to the first shielding bonding pad included in the first shielding structure; and a shielding via plug connected to the second shielding bonding pad and penetrating the second substrate.

10. The image sensor according to claim 1, wherein, The first shielding structure includes: a plurality of first shielding wiring layers disposed at different vertical levels from each other; and first shielding plugs connecting the plurality of first shielding wiring layers disposed at different vertical levels to each other in the vertical direction, and wherein the plurality of first shielding wiring layers extend in the horizontal direction.

11. The image sensor according to any one of claims 1 to 10, wherein, The source follower bonding pad surrounds the source follower gate.

12. An image sensor, comprising: A top layer, including: a first substrate; a floating diffusion node within the first substrate; a first floating diffusion wiring structure connected to the floating diffusion node; and a first shielding structure beside the first floating diffusion wiring structure; An intermediate layer bonded to the top layer and below the top layer, wherein the intermediate layer includes: a second substrate including a second front surface and a second back surface opposite to the second front surface; a source follower gate on the second front surface of the second substrate; a source follower source region within the second substrate; a second floating diffusion wiring structure connected to the first floating diffusion wiring structure and the source follower gate; and a second shielding structure connected to the first shielding structure and the source follower source region; and A bottom layer bonded to the intermediate layer and below the intermediate layer, wherein the bottom layer includes: a third substrate; and transistors on the third substrate, wherein the second shielding structure includes: a second shielding bonding pad bonded to a first shielding bonding pad included in the first shielding structure; and an impurity region within the second substrate and connected to the second shielding bonding pad.

13. The image sensor according to claim 12, wherein, The second shielding structure further includes: A second shielding wiring layer spaced apart from the second substrate; A second shielding plug connecting the impurity region and the second shielding bonding pad; and A shielding connection plug connecting the impurity region and the second shielding wiring layer.

14. The image sensor according to claim 13, wherein, The intermediate layer further includes: a source follower bonding pad between the source follower source region and the second shielding plug, and wherein at least a portion of the source follower bonding pad is surrounded by the source follower source region.

15. The image sensor according to claim 14, wherein, The second floating diffusion wiring structure includes: a second floating diffusion bonding pad bonded to a first floating diffusion bonding pad included in the first floating diffusion wiring structure; and a first connection via plug connected to the second floating diffusion bonding pad and penetrating the second substrate.

16. The image sensor according to claim 12, wherein, The first shielding structure surrounds the first floating diffusion wiring structure, and wherein the second shielding structure surrounds the second floating diffusion wiring structure.

17. The image sensor according to any one of claims 12 to 16, wherein, The top layer includes a first front-side bonding pad, wherein the intermediate layer includes a second front-side bonding pad and a second back-side bonding pad, wherein the bottom layer includes a third front-side bonding pad, wherein the first front-side bonding pad is bonded to the second back-side bonding pad, and wherein the second front-side bonding pad is bonded to the third front-side bonding pad.

18. An image sensor, comprising: The top layer includes: a first substrate; a pixel isolation layer within the first substrate and defining pixels; a photodiode disposed within the first substrate and forming a pixel; a transfer transistor for transferring an electrical signal generated by the photodiode; a floating diffusion node within the first substrate and connected to the transfer transistor; a first floating diffusion wiring structure connected to the floating diffusion node; a first shielding structure beside the first floating diffusion wiring structure; and a first wiring layer spaced apart from the first floating diffusion wiring structure and the first shielding structure; The intermediate layer is bonded to the top layer and beneath the top layer. The intermediate layer includes: a second substrate; a source follower gate on the second substrate; a source follower source region within the second substrate; a second floating diffusion wiring structure connected to the first floating diffusion wiring structure and the source follower gate; a second shielding structure connected to the first shielding structure and the source follower source region; a source follower bonding pad between the second shielding structure and the source follower source region and surrounding the source follower gate; and a second wiring layer spaced apart from the second floating diffusion wiring structure and the second shielding structure; and The bottom layer is bonded to the intermediate layer and beneath the intermediate layer. The bottom layer includes: a third substrate; a plurality of transistors disposed on the third substrate; a third wiring layer connected to a transistor among the plurality of transistors; and a third via plug between the transistor and the third wiring layer.

19. The image sensor according to claim 18, wherein, The top surface of the source follower bonding pad is coplanar with the top surface of the source follower gate.

20. The image sensor according to claim 18 or 19, wherein The first floating diffusion wiring structure includes: a first floating diffusion wiring layer at a first vertical level; and a second floating diffusion wiring layer at a second vertical level different from the first vertical level, and wherein the first shielding structure includes: a first shielding wiring layer at only one of the first vertical level and the second vertical level.

Images