Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate, a plurality of sub-pixels, a plurality of first scanning lines (GA1), a plurality of second scanning lines (GA2) and a plurality of data lines (DA), wherein the sub-pixels, the first scanning lines (GA1), the second scanning lines (GA2) and the data lines (DA) are all arranged on the substrate; the sub-pixel comprises a sub-pixel driving circuit, and the sub-pixel driving circuit comprises a driving transistor (T3), a capacitor structure (C2), a compensation transistor (T2) and a data write-in transistor (T4); grid electrodes (T2-g1 and T2-g2) of the compensation transistor (T2) are coupled with the corresponding first scanning lines (GA1), a first pole of the compensation transistor (T2) is coupled with a second pole of the driving transistor (T3), and a second pole of the compensation transistor (T2) is coupled with a grid electrode (T3-g) of the driving transistor (T3); a gate (T4-g) of the data write-in transistor (T4) is coupled with a corresponding second scanning line (GA2), a first pole of the data write-in transistor (T4) is coupled with a corresponding data line (DA), a second pole of the data write-in transistor (T4) is coupled with a first end of the capacitor structure (C2), and a second end of the capacitor structure (C2) is coupled with a gate (T3-g) of the driving transistor (T3).

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) displays are self-luminous screens made of organic materials. They do not require the backlight panel used in LCD screens. When current passes through the light-emitting layer formed by the organic material, the sub-pixels will emit light on their own. Therefore, compared with LCD screens, AMOLED displays have display advantages such as purer colors and higher contrast, and have huge market prospects.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of sub-pixels, a plurality of first scan lines, a plurality of second scan lines, and a plurality of data lines, all disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit, the sub-pixel driving circuit comprising a driving transistor, a capacitor structure, a compensation transistor, and a data writing transistor;

[0007] The gate of the compensation transistor is coupled to the corresponding first scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the gate of the data writing transistor is coupled to the corresponding second scan line, the first electrode of the data writing transistor is coupled to the corresponding data line, the second electrode of the data writing transistor is coupled to the first end of the capacitor structure, and the second end of the capacitor structure is coupled to the gate of the driving transistor.

[0008] Optionally, the driving transistor includes a top gate, a bottom gate and a driving active layer, at least a portion of the bottom gate is located between the top gate and the substrate, and at least a portion of the driving active layer is located between the top gate and the bottom gate; the top gate and the bottom gate are coupled via a first conductive connection portion.

[0009] Optionally, the capacitor structure includes a first plate and a second plate, the first plate is located between the second plate and the substrate; the first plate and the bottom gate form an integrated structure, and the second plate and the second pole of the data writing transistor form an integrated structure.

[0010] Optionally, the capacitor structure further includes a third electrode plate, the second electrode plate is located between the first electrode plate and the third electrode plate, and the third electrode plate is coupled to the first conductive connection portion.

[0011] Optionally, the first scanning line includes a plurality of first scanning portions and a plurality of second scanning portions, the first scanning portions and the second scanning portions are alternately arranged along the first direction, and adjacent first scanning portions and second scanning portions are coupled;

[0012] The orthographic projection of the first scanning portion on the base substrate and the orthographic projection of the capacitor structure on the base substrate are arranged along a first direction; the second scanning portion extends along an extension direction of a portion of a boundary of the capacitor structure.

[0013] Optionally, the data writing transistor includes a dual-gate transistor.

[0014] Optionally, the data writing transistor includes a data writing active layer, the gate of the data writing transistor has a U-shaped structure, and the orthographic projection of the gate of the data writing transistor on the substrate has two overlapping areas with the orthographic projection of the data writing active layer on the substrate.

[0015] Optionally, the display substrate further includes a first initialization signal layer and a first reset signal line;

[0016] The sub-pixel driving circuit also includes a first reset transistor, the gate of the first reset transistor is coupled to the corresponding first reset signal line, the first electrode of the first reset transistor is coupled to the first initialization signal layer, and the second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first reset transistor and / or the compensation transistor include an oxide transistor.

[0017] Optionally, the first initialization signal layer includes multiple first initialization signal lines and multiple second initialization signal lines, the first initialization signal line includes at least a portion extending along a first direction, the second initialization signal line includes at least a portion extending along a second direction, the first direction intersects with the second direction, and the first initialization signal line is coupled to the second initialization signal line.

[0018] Optionally, the display substrate further includes a second initialization signal layer and a second reset signal line;

[0019] The sub-pixel driving circuit further includes a second reset transistor, wherein a gate of the second reset transistor is coupled to the corresponding second reset signal line, a first electrode of the second reset transistor is coupled to the second initialization signal layer, and a second electrode of the second reset transistor is coupled to an anode of a light-emitting element included in the sub-pixel;

[0020] The second initialization signal layer includes multiple third initialization signal lines and multiple fourth initialization signal lines, the third initialization signal lines include at least a portion extending along the first direction, the fourth initialization signal lines include at least a portion extending along the second direction, and the third initialization signal lines are coupled to the fourth initialization signal lines.

[0021] Optionally, the display substrate further includes a cathode layer and at least one cathode compensation layer, at least part of the cathode compensation layer is located between the cathode layer and the base substrate, and the cathode compensation layer includes a plurality of cathode compensation lines coupled to the cathode layer.

[0022] Optionally, the display substrate includes a first cathode compensation layer and a second cathode compensation layer, at least a portion of the first cathode compensation layer is located between the second cathode compensation layer and the base substrate; the first cathode compensation layer includes a plurality of first cathode compensation lines, the first cathode compensation lines include at least a portion extending along the first direction; the second cathode compensation layer includes a plurality of second cathode compensation lines, the second cathode compensation lines include at least a portion extending along the second direction; the first cathode compensation lines are coupled to the second cathode compensation lines.

[0023] Optionally, the second initialization signal line, the fourth initialization signal line and the second cathode compensation line are sequentially arranged in a cycle along the first direction.

[0024] Optionally, the first reset transistor includes a first reset active layer, and the compensation transistor includes a compensation active layer;

[0025] The display substrate further includes a plurality of power lines, each of the power lines including at least a portion extending along the second direction; an orthographic projection of the power lines on the base substrate at least partially overlaps with an orthographic projection of the first reset active layer on the base substrate; and / or an orthographic projection of the power lines on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate.

[0026] Optionally, the display substrate further includes a plurality of power compensation lines, each of the power compensation lines including at least a portion extending along a first direction, the first direction intersecting the second direction; and the power compensation lines are coupled to the power lines.

[0027] Optionally, the data line is located between the power line and the second initialization signal line; and / or, the data line is located between the power line and the fourth initialization signal line; and / or, the data line is located between the power line and the second cathode compensation line.

[0028] Optionally, the display substrate further includes a plurality of first light-emitting control signal lines and a plurality of second light-emitting control signal lines; the sub-pixel driving circuit further includes a power control transistor and a light-emitting control transistor;

[0029] The gate of the power control transistor is coupled to the corresponding first light emitting control signal line, the first electrode of the power control transistor is coupled to the corresponding power line, and the second electrode of the power control transistor is coupled to the first electrode of the driving transistor;

[0030] The gate of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is coupled to the anode of the light-emitting element included in the sub-pixel.

[0031] Optionally, within the layout area of ​​the same sub-pixel driving circuit, the first initialization signal line, the first reset signal line, the second scanning line, the first scanning line, the first light-emitting control signal line, the power compensation line, the second light-emitting control signal line, the second reset signal line, the third initialization signal line and the first cathode compensation line are arranged in sequence along the second direction.

[0032] Optionally, the display substrate includes a first source-drain metal layer, and the first initialization signal line, the first reset signal line, the second scan line, the first scan line, the first light-emitting control signal line, the power compensation line, the second light-emitting control signal line, the second reset signal line, the third initialization signal line and the first cathode compensation line are all set in the same layer and material as the first source-drain metal layer.

[0033] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0035] FIG1 is a schematic diagram of a circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0036] FIG2 is a timing diagram of the operation of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0037] FIG3 is a schematic cross-sectional view of a portion of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0038] FIG4 is a schematic diagram of the layout of a light shielding layer in a display substrate provided by an embodiment of the present disclosure;

[0039] FIG5 is a schematic diagram of the layout of a polysilicon active layer in a display substrate provided by an embodiment of the present disclosure;

[0040] FIG6 is a schematic diagram of the layout of the first gate metal layer in the display substrate provided by an embodiment of the present disclosure;

[0041] FIG7 is a schematic diagram of the layout of the second gate metal layer in the display substrate provided by an embodiment of the present disclosure;

[0042] FIG8 is a schematic diagram of the layout of an oxide active layer in a display substrate provided by an embodiment of the present disclosure;

[0043] FIG9 is a schematic diagram of the layout of the third gate metal layer in the display substrate provided by an embodiment of the present disclosure;

[0044] FIG10 is a schematic diagram showing the layout of some via holes on an interlayer insulating layer in a display substrate according to an embodiment of the present disclosure;

[0045] FIG11 is a schematic diagram showing the layout of some via holes on an interlayer insulating layer in a display substrate according to an embodiment of the present disclosure;

[0046] FIG12 is a schematic diagram showing the layout of a first source / drain metal layer in a display substrate provided by an embodiment of the present disclosure;

[0047] FIG13 is a schematic diagram of a via hole formed on a first planar layer in a display substrate provided by an embodiment of the present disclosure;

[0048] FIG14 is a schematic diagram showing the layout of a second source / drain metal layer in a display substrate provided by an embodiment of the present disclosure;

[0049] FIG15 is a schematic diagram showing the layout of a polysilicon active layer and a first gate metal layer in a display substrate provided by an embodiment of the present disclosure;

[0050] FIG16 is a schematic diagram of a layout with a light shielding layer added based on FIG15;

[0051] FIG17 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG16;

[0052] FIG18 is a schematic diagram showing the layout of an oxide active layer, a second gate metal layer, and a third gate metal layer in a display substrate provided by an embodiment of the present disclosure;

[0053] FIG19 is a schematic diagram of a layout in which an interlayer insulating layer and a first source / drain metal layer are added on the basis of FIG16 ;

[0054] FIG20 is a schematic diagram of a layout in which an interlayer insulating layer and a first source / drain metal layer are added on the basis of FIG18 ;

[0055] FIG21 is a schematic diagram of a layout in which an oxide active layer, a second gate metal layer, and a third gate metal layer are added to FIG15;

[0056] FIG22 is a schematic diagram of a layout in which an interlayer insulating layer and a first source / drain metal layer are added on the basis of FIG21;

[0057] FIG23 is a schematic diagram of a layout in which a first planarization layer and a second source / drain metal layer are added to FIG22 ;

[0058] FIG24 is a schematic diagram showing the layout of the first source-drain metal layer and the second source-drain metal layer in the display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0060] Active matrix displays achieve display control of individual sub-pixels by controlling the current flowing through each sub-OLED device. Under this principle, after displaying each frame of an AMOLED display, the sub-pixels need to be initialized and then rewritten with the data signal corresponding to the next frame of the image. This data signal is used to control the device current and thus display the next frame of the image. In this process, the accuracy of the data signal writing will strictly affect the current flowing through the drive transistor and the OLED device, thereby affecting the brightness of the sub-pixel. As the demand for high-frequency display increases, the increase in display frequency will lead to insufficient compensation for the threshold voltage Vth of the drive transistor, as well as difficulty in writing data signals when displaying low grayscale and black state.

[0061] Referring to Figures 1, 6, 7, 9, 15, 18, and 21 to 24, embodiments of the present disclosure provide a display substrate comprising: a base substrate, and a plurality of sub-pixels, a plurality of first scan lines GA1, a plurality of second scan lines GA2, and a plurality of data lines DA, all disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit, the sub-pixel driving circuit comprising a driving transistor T3, a capacitor structure C2, a compensation transistor T2, and a data writing transistor T4;

[0062] The gate of the compensation transistor T2 (such as T2-g1 and T2-g2) is coupled to the corresponding first scan line GA1, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3; the gate T4-g of the data writing transistor T4 is coupled to the corresponding second scan line GA2, the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, the second electrode of the data writing transistor T4 is coupled to the first end of the capacitor structure C2, and the second end of the capacitor structure C2 is coupled to the gate T3-g of the driving transistor T3.

[0063] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along the second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction. The plurality of columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes the horizontal direction, and the second direction includes the vertical direction, but is not limited thereto.

[0064] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element (ie, the above-mentioned OLED device). The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0065] Illustratively, the plurality of first scan lines GA1 are arranged along the second direction, and at least a portion of the first scan lines GA1 extends along the first direction. The plurality of first scan lines GA1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits. The first scan lines GA1 are respectively coupled to the gates of the compensation transistors T2 (e.g., T2-g1 and T2-g2) in a corresponding row of sub-pixel driving circuits to provide a first scan signal to the gates of the compensation transistors T2 (e.g., T2-g1 and T2-g2).

[0066] Exemplarily, the plurality of second scan lines GA2 are arranged along the second direction, and at least a portion of the second scan lines GA2 extends along the first direction. The plurality of second scan lines GA2 correspond one-to-one to the plurality of rows of sub-pixel driving circuits. The second scan lines GA2 are respectively coupled to the gates T4-g of the data write transistors T4 in a corresponding row of sub-pixel driving circuits to provide a second scan signal to the gates T4-g of the data write transistors T4.

[0067] Exemplarily, the plurality of data lines DA are arranged along the first direction, and at least a portion of the data lines DA extends along the second direction. The plurality of data lines DA correspond one-to-one to the plurality of columns of sub-pixel driving circuits. The data lines DA are respectively coupled to the first electrodes of the data write transistors T4 in the corresponding column of sub-pixel driving circuits to provide data signals to the first electrodes of the data write transistors T4.

[0068] As shown in Figures 1 and 23, the display substrate exemplarily includes a first reset signal line Rst1, a second reset signal line Rst2, a first emission control signal line EM1, a second emission control signal line EM2, a first initialization signal layer Vinit1, a second initialization signal layer Vinit2, a power line VDD, and a cathode layer. The sub-pixel driving circuit includes a driving transistor T3, a capacitor structure C2, a compensation transistor T2, a data writing transistor T4, a first reset transistor T1, a second reset transistor T7, a power control transistor T5, an emission control transistor T6, and a storage capacitor Cst.

[0069] The gate of the first reset transistor T1 (such as: T1-g1 and T1-g2) is coupled to the corresponding first reset signal line Rst1, the first electrode of the first reset transistor T1 is coupled to the first initialization signal layer Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3.

[0070] The gate of the compensation transistor T2 (such as T2-g1 and T2-g2) is coupled to the corresponding first scan line GA1, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0071] A gate T4-g of the data writing transistor T4 is coupled to the corresponding second scan line GA2, a first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and a second electrode of the data writing transistor T4 is coupled to a first end of the capacitor structure C2. A second end of the capacitor structure C2 is coupled to the gate T3-g of the driving transistor T3.

[0072] The gate T5-g of the power control transistor T5 is coupled to the corresponding first light emitting control signal line EM1, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0073] The gate T6-g of the light-emitting control transistor T6 is coupled to the corresponding second light-emitting control signal line EM2, the first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, the second electrode of the light-emitting control transistor T6 is coupled to the anode of the corresponding light-emitting element, and the cathode of the light-emitting element receives the negative power supply signal VSS.

[0074] The gate of the second reset transistor T7 is coupled to the corresponding second reset signal line Rst2, the first electrode of the seventh transistor T7 is coupled to the corresponding second initialization signal layer Vinit2, and the second electrode of the seventh transistor T7 is coupled to the corresponding anode of the light emitting element.

[0075] The first plate Cst1 of the storage capacitor Cst is coupled to the gate T3 - g of the driving transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power line VDD.

[0076] Exemplarily, the first reset transistor T1 and the compensation transistor T2 include oxide transistors, and the driving transistor T3, the data writing transistor T4, the power control transistor T5, the light emission control transistor T6 and the second reset transistor T7 include low-temperature polysilicon transistors.

[0077] As shown in FIG2 , the driving principle of the above pixel driving circuit is as follows:

[0078] In the P1 period: the power control transistor T5 remains in the on state of the previous frame, the first reset signal transmitted by the first reset signal line Rst1 is at a high level, the first reset transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal layer Vinit1 is written into the gate T3-g of the driving transistor T3 (ie, the N1 node), resetting the N1 node.

[0079] During period P2, the power control transistor T5 remains on from the previous frame. The first reset signal transmitted by the first reset signal line Rst1 is at a low level. The first scan signal transmitted by the first scan line GA1 is at a high level. The compensation transistor T2 is turned on, and the power signal transmitted by the power line VDD compensates the threshold voltage Vth of the driving transistor T3. After compensation, the potential of the N1 node is Vth + Vdd, where Vdd is the voltage value of the power signal. The potential of the first electrode of the driving transistor T3 (i.e., the N2 node) is Vdd.

[0080] In the P3 period: the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 is at a high level, the power control transistor T5 is turned off, the first scanning signal transmitted by the first scanning line GA1 is at a low level, the compensation transistor T2 is turned off, the second scanning signal transmitted by the second scanning line GA2 is at a low level, the data writing transistor T4 is turned on, and the data signal transmitted by the data line DA is written to the first end of the capacitor structure C2. Through the coupling effect of the capacitor structure C2, the potential of the N1 node becomes: Vth+Vdd+Vdata, Vdata is the voltage value of the data signal, and the potential of the N2 node remains Vdd.

[0081] In the P4 period: the second scanning signal transmitted by the second scanning line GA2 is at a high level, the data writing transistor T4 is turned off, the second reset signal transmitted by the second reset signal line Rst2 is at a low level, the second reset transistor T7 is turned on, and the second initialization signal transmitted by the second initialization signal layer Vinit2 is written to the anode of the light-emitting element (ie, the N4 node), and the N4 node is reset.

[0082] During period P5, the first emission control signal transmitted by the first emission control signal line EM1 and the second emission control signal transmitted by the second emission control signal line EM2 are both at a low level. The power control transistor T5 and the emission control transistor T6 are both on, and all other switching transistors are off, causing the light-emitting element to emit light. In this state, Vgs = Vth + Vdd + Vdata - Vdd = Vth + Vdata.

[0083] Leakage current Id = K(Vgs-Vth)^2 = K(Vth+Vdata-Vth)^2 = K(Vdata)^2

[0084] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, by setting the gate of the compensation transistor T2 (such as: T2-g1 and T2-g2) to be coupled with the corresponding first scan line GA1, the gate T4-g of the data writing transistor T4 is coupled with the corresponding second scan line GA2, and the second electrode of the data writing transistor T4 can be coupled to the gate T3-g of the driving transistor T3 through the capacitor structure C2, so that the compensation transistor T2 and the data writing transistor T4 can be independently controlled, thereby realizing threshold compensation of the driving transistor T3 and writing of the data signal, which can be performed separately at different time periods. In this way, under high-frequency display conditions, sufficient compensation of the threshold voltage of the driving transistor T3 can be ensured, and at the same time, problems such as difficulty in writing data signals when displaying low grayscale and black state can be overcome.

[0085] Furthermore, the sub-pixel driving circuit includes a capacitor structure C2, which can stabilize the voltage of the N1 node through the capacitor structure C2, thereby preventing the potential of the N1 node from being affected by leakage of the data writing transistor T4.

[0086] As shown in Figures 4 to 6, 12, 15 and 22, in some embodiments, the driving transistor T3 includes a top gate T3-g1, a bottom gate T3-g2 and a driving active layer 23, at least a portion of the bottom gate T3-g2 is located between the top gate T3-g1 and the substrate, and at least a portion of the driving active layer 23 is located between the top gate T3-g1 and the bottom gate T3-g2; the top gate T3-g1 and the bottom gate T3-g2 are coupled by a first conductive connection portion 31.

[0087] As shown in FIG3 , the display substrate exemplarily includes a buffer layer BF, a light shielding layer, a polysilicon active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, an oxide active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2. A passivation layer PVX may also be provided on the display substrate as needed. The passivation layer PVX may be located between the first source / drain metal layer SD1 and the first planarization layer PLN1, or between the first planarization layer PLN1 and the second source / drain metal layer SD2.

[0088] Exemplarily, the top gate T3-g1 is provided in the same layer and material as the first gate metal layer, the bottom gate T3-g2 is provided in the same layer and material as the light shielding layer, and the top gate T3-g1 can be reused as the first plate Cst1 of the storage capacitor Cst. The first conductive connection portion 31 is provided in the same layer and material as the first source / drain metal layer.

[0089] Exemplarily, the orthographic projection of the top gate T3-g1 on the base substrate at least partially overlaps with the orthographic projection of the driving active layer 23 on the base substrate. The orthographic projection of the bottom gate T3-g2 on the base substrate at least partially overlaps with the orthographic projection of the driving active layer 23 on the base substrate.

[0090] Exemplarily, the bottom gate T3-g2 includes a gate body portion T3-g21 and a gate protrusion T3-g22. The orthographic projection of the gate body portion T3-g21 on the substrate at least partially overlaps with the orthographic projection of the top gate T3-g1 on the substrate, and the orthographic projection of the gate protrusion T3-g22 on the substrate does not overlap with the orthographic projection of the top gate T3-g1 on the substrate. Exemplarily, the first conductive connection portion 31 is coupled to the top gate T3-g1 and the gate protrusion T3-g22, respectively.

[0091] For example, when the first conductive connection portion 31 and the first source / drain metal layer are provided in the same layer and made of the same material, since the film layer between the first conductive connection portion 31 and the bottom gate T3-g2 is relatively far apart, connection to the bottom gate T3-g2 can be achieved by drilling the interlayer insulating layer twice at different depths. More specifically, the interlayer insulating layer can be divided into a first interlayer insulating layer and a second interlayer insulating layer, with the first interlayer insulating layer located between the substrate and the second interlayer insulating layer. The second interlayer insulating layer can be drilled first, and then the first interlayer insulating layer can be drilled within the hole to ultimately achieve connection.

[0092] The driving transistor T3 is configured as described above to include a top gate T3-g1 and a bottom gate T3-g2, and the top gate T3-g1 and the bottom gate T3-g2 are coupled through the first conductive connection portion 31, so that signals can be written to the top gate T3-g1 and the bottom gate T3-g2 at the same time, thereby realizing fast data signal writing and fast compensation of the driving transistor T3.

[0093] As shown in Figures 4, 5, 16 and 17, in some embodiments, the capacitor structure C2 includes a first plate C21 and a second plate C22, and the first plate C21 of the capacitor structure C2 is located between the second plate C22 of the capacitor structure C2 and the substrate; the first plate C21 of the capacitor structure C2 and the bottom gate T3-g2 form an integrated structure, and the second plate C22 of the capacitor structure C2 and the second electrode of the data writing transistor T4 form an integrated structure.

[0094] As shown in Figures 7 and 20, the capacitor structure C2 also exemplarily includes a third plate C23. The second plate C22 of the capacitor structure C2 is located between the first plate C21 of the capacitor structure C2 and the third plate C23. The third plate C23 is coupled to the first conductive connection portion 31. For example, the third plate C23 is provided in the same layer and material as the second gate metal layer, and the second plate Cst2 of the storage capacitor Cst is provided in the same layer and material as the second gate metal layer.

[0095] The capacitor structure C2 is configured to include a first plate, a second plate, and a third plate C23, so that the capacitor structure C2 can be formed into a sandwich structure, which can increase the facing area between the plates of the capacitor structure C2 and better realize the capacitance of the capacitor structure C2.

[0096] As shown in FIG17 and FIG20 , in some embodiments, the first scanning line GA1 includes a plurality of first scanning portions GA11 and a plurality of second scanning portions GA12 , wherein the first scanning portions GA11 and the second scanning portions GA12 are alternately arranged along a first direction, and adjacent first scanning portions GA11 and second scanning portions GA12 are coupled;

[0097] The orthographic projection of the first scanning portion GA11 on the base substrate and the orthographic projection of the capacitor structure C2 on the base substrate are arranged along a first direction; the second scanning portion GA12 extends along an extension direction of a portion of a boundary of the capacitor structure C2.

[0098] Illustratively, the first scanning portion GA11 and the second scanning portion GA12 are formed as an integrated structure.

[0099] Exemplarily, the orthographic projection of the second scanning portion GA12 on the substrate is arranged around a portion of the orthographic projection of the capacitor structure C2 on the substrate.

[0100] Exemplarily, the first scanning portion GA11 is coupled to the gates of the compensation transistors T2 (eg, T2 - g1 and T2 - g2 ).

[0101] In the display substrate provided by the above embodiment, by setting the second scanning part GA12 to extend along the extension direction of a part of the boundary of the capacitor structure C2, it is beneficial to reduce the overall layout space occupied by the sub-pixel driving circuit and reduce the layout difficulty of the sub-pixel driving circuit in a limited layout space.

[0102] As shown in FIG. 5 , FIG. 6 and FIG. 15 , in some embodiments, the data writing transistor T4 includes a dual-gate transistor.

[0103] Exemplarily, the data writing transistor T4 includes a data writing active layer 24, the gate T4-g of the data writing transistor T4 has a U-shaped structure, and the gate T4-g of the data writing transistor T4 on the substrate has two overlapping areas with the projection of the data writing active layer 24 on the substrate.

[0104] Exemplarily, at least a portion of the data writing active layer 24 extends along the second direction, and the two overlapping regions are arranged along the second direction.

[0105] During the P5 period, the N5 node is in a floating state. Potential fluctuations at the N5 node can affect the stability of the N1 node, thereby affecting display brightness. The data write transistor T4 is configured as a dual-gate transistor to effectively prevent leakage at the N5 node and ensure the stability of the N5 node potential, thereby effectively improving the stability of the N1 node within the pixel frame and enhancing display brightness retention.

[0106] As shown in Figures 7 to 9, 17, 18, 20, and 22 to 24, in some embodiments, the display substrate further includes a first initialization signal layer Vinit1 and a first reset signal line Rst1; the sub-pixel driving circuit further includes a first reset transistor T1, the gate of the first reset transistor T1 (such as: T1-g1 and T1-g2) is coupled to the corresponding first reset signal line Rst1, the first electrode of the first reset transistor T1 is coupled to the first initialization signal layer Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3; the first reset transistor T1 and / or the compensation transistor T2 include oxide transistors.

[0107] Exemplarily, the display substrate includes a plurality of first reset signal lines Rst1 arranged along the second direction, wherein the first reset signal lines Rst1 include at least a portion extending along the first direction. The plurality of first reset signal lines Rst1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits. The first reset signal lines Rst1 are respectively coupled to the gates of the first reset transistors T1 (e.g., T1-g1 and T1-g2) in a corresponding row of sub-pixel driving circuits to provide a first reset signal to the coupled first reset transistors T1.

[0108] The above-mentioned configuration in which the first reset transistor T1 and / or the compensation transistor T2 include oxide transistors can reduce leakage risk of the first reset transistor T1 and / or the compensation transistor T2 and improve the stability of the N1 node and the brightness retention rate within the pixel frame.

[0109] As shown in Figures 12, 14 and 24, in some embodiments, the first initialization signal layer Vinit1 includes multiple first initialization signal lines Vinit11 and multiple second initialization signal lines Vinit12, the first initialization signal line Vinit11 includes at least a portion extending along the first direction, the second initialization signal line Vinit12 includes at least a portion extending along the second direction, the first direction intersects with the second direction, and the first initialization signal line Vinit11 is coupled to the second initialization signal line Vinit12.

[0110] Exemplarily, the plurality of first initialization signal lines Vinit11 are arranged along the second direction, and the first initialization signal lines Vinit11 are provided in the same layer and material as the first source / drain metal layer. The plurality of second initialization signal lines Vinit12 are arranged along the first direction, and the second initialization signal lines Vinit12 are provided in the same layer and material as the second source / drain metal layer.

[0111] Exemplarily, each of the first initialization signal lines Vinit11 is coupled to the plurality of second initialization signal lines Vinit12 .

[0112] The above configuration enables the first initialization signal layer Vinit1 to form a grid structure, effectively reducing the loading of the first initialization signal layer Vinit1, improving the uniformity of the first initialization signal layer Vinit1 in transmitting the first initialization signal, and effectively improving the display quality of the display substrate.

[0113] As shown in Figures 6, 12, 14, 15, 22 to 24, in some embodiments, the display substrate further includes a second initialization signal layer Vinit2 and a second reset signal line Rst2; the sub-pixel driving circuit further includes a second reset transistor T7, the gate T7-g of the second reset transistor T7 is coupled to the corresponding second reset signal line Rst2, the first electrode of the second reset transistor T7 is coupled to the second initialization signal layer Vinit2, and the second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element included in the sub-pixel; the second initialization signal layer Vinit2 includes a plurality of third initialization signal lines Vinit21 and a plurality of fourth initialization signal lines Vinit22, the third initialization signal line Vinit21 includes at least a portion extending along the first direction, the fourth initialization signal line Vinit22 includes at least a portion extending along the second direction, and the third initialization signal line Vinit21 is coupled to the fourth initialization signal line Vinit22.

[0114] Exemplarily, the display substrate includes a plurality of second reset signal lines Rst2 arranged along the second direction, each second reset signal line Rst2 including at least a portion extending along the first direction. The plurality of second reset signal lines Rst2 correspond one-to-one to the plurality of rows of sub-pixel driving circuits. The second reset signal line Rst2 is coupled to a gate T7-g of each second reset transistor T7 in a corresponding row of sub-pixel driving circuits, and is configured to provide a second reset signal to the coupled second reset transistor T7.

[0115] Exemplarily, the plurality of third initialization signal lines Vinit21 are arranged along the second direction, and the third initialization signal lines Vinit21 are provided in the same layer and material as the first source / drain metal layer. The plurality of fourth initialization signal lines Vinit22 are arranged along the first direction, and the fourth initialization signal line Vinit22 is provided in the same layer and material as the second source / drain metal layer.

[0116] Exemplarily, each of the third initialization signal lines Vinit21 is coupled to the plurality of fourth initialization signal lines Vinit22 .

[0117] The above configuration enables the second initialization signal layer Vinit2 to form a grid structure, effectively reducing the loading of the second initialization signal layer Vinit2, improving the uniformity of the second initialization signal layer Vinit2 in transmitting the second initialization signal, and effectively improving the display quality of the display substrate.

[0118] In some embodiments, the display substrate further includes a cathode layer and at least one cathode compensation layer, at least a portion of the cathode compensation layer is located between the cathode layer and the base substrate, and the cathode compensation layer includes a plurality of cathode compensation lines coupled to the cathode layer.

[0119] As shown in Figures 12, 14 and 24, exemplarily, the display substrate includes a first cathode compensation layer and a second cathode compensation layer, at least a portion of the first cathode compensation layer is located between the second cathode compensation layer and the base substrate; the first cathode compensation layer includes a plurality of first cathode compensation lines VSS1, and the first cathode compensation lines VSS1 include at least a portion extending along the first direction; the second cathode compensation layer includes a plurality of second cathode compensation lines VSS2, and the second cathode compensation lines VSS2 include at least a portion extending along the second direction; the first cathode compensation lines VSS1 are coupled to the second cathode compensation lines VSS2.

[0120] Exemplarily, the first cathode compensation layer and the first source / drain metal layer are provided in the same layer and made of the same material. The second cathode compensation layer and the second source / drain metal layer are provided in the same layer and made of the same material.

[0121] Exemplarily, the first cathode compensation layer includes a plurality of first cathode compensation lines VSS1 arranged along the second direction, and the second cathode compensation layer includes a plurality of second cathode compensation lines VSS2 arranged along the first direction.

[0122] Exemplarily, each of the first cathode compensation lines VSS1 is coupled to each of the plurality of second cathode compensation lines VSS2 .

[0123] Exemplarily, the display substrate includes a display area and a peripheral area located around the display area, and the cathode compensation layer is coupled to the cathode layer in the peripheral area, but the present invention is not limited thereto.

[0124] The display substrate is configured to include a first cathode compensation layer and a second cathode compensation layer, so that the cathode compensation layer can be formed into a grid shape, thereby effectively reducing the load of the cathode layer and reducing the cross-voltage of the display substrate.

[0125] As shown in FIG. 24 , in some embodiments, the second initialization signal line Vinit12 , the fourth initialization signal line Vinit22 , and the second cathode compensation line VSS2 are sequentially and cyclically arranged along the first direction.

[0126] Exemplarily, in the layout area of ​​three columns of sub-pixel driving circuits adjacent along the first direction, the second initialization signal line Vinit12 is located in the layout area of ​​the first column of sub-pixel driving circuits, the fourth initialization signal line Vinit22 is located in the layout area of ​​the second column of sub-pixel driving circuits, and the second cathode compensation line VSS2 is located in the layout area of ​​the third column of sub-pixel driving circuits.

[0127] Exemplarily, a layout area of ​​three columns of sub-pixel driving circuits is taken as a circulation unit, and the display substrate includes a plurality of circulation units arranged along the first direction.

[0128] The above configuration can improve the display effect of the display substrate while better reducing the layout difficulty of the display substrate.

[0129] As shown in FIG7 , FIG8 , FIG9 , FIG14 , FIG18 and FIG23 , in some embodiments, the first reset transistor T1 includes a first reset active layer 21 , and the compensation transistor T2 includes a compensation active layer 22 ;

[0130] The display substrate further includes a plurality of power lines VDD, each of the power lines VDD including at least a portion extending along a second direction; an orthographic projection of the power line VDD on the base substrate at least partially overlaps with an orthographic projection of the first reset active layer 21 on the base substrate; and / or an orthographic projection of the power line VDD on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer 22 on the base substrate.

[0131] As shown in FIG14 , the power line VDD exemplarily includes a plurality of first power supply portions VDD1 and a plurality of second power supply portions VDD2. The first power supply portions VDD1 and the second power supply portions VDD2 are alternately arranged along the second direction, and adjacent first power supply portions VDD1 and second power supply portions VDD2 are coupled. The width of the first power supply portion VDD1 along the first direction is greater than the width of the second power supply portion VDD2 along the first direction. The orthographic projections of the first power supply portions VDD1 on the base substrate at least partially overlap with the orthographic projections of the first reset active layer 21 on the base substrate; and / or the orthographic projections of the first power supply portions VDD1 on the base substrate at least partially overlap with the orthographic projections of the compensation active layer 22 on the base substrate.

[0132] Exemplarily, the first reset active layer 21 includes a first reset channel portion, the orthographic projection of the first reset channel portion on the substrate overlaps with the orthographic projection of the gate of the first reset transistor T1 (e.g., T1-g1 and T1-g2) on the substrate. The compensation active layer 22 includes a compensation channel portion, the orthographic projection of the compensation channel portion on the substrate overlaps with the orthographic projection of the gate of the compensation transistor T2 (e.g., T2-g1 and T2-g2) on the substrate. The orthographic projection of the first power supply portion VDD1 on the substrate overlaps the orthographic projection of the first reset channel portion on the substrate; and / or the orthographic projection of the first power supply portion VDD1 on the substrate overlaps the orthographic projection of the compensation channel portion on the substrate.

[0133] The first reset transistor T1 and the compensation transistor T2 include oxide transistors. The above configuration enables the power line VDD to block the channel portion of the oxide transistor, thereby achieving optical shielding and effectively improving the stability of the first reset transistor T1 and the compensation transistor T2.

[0134] As shown in Figures 12, 14, and 22 to 24, in some embodiments, the display substrate further includes a plurality of power compensation lines VDD3, the power compensation lines VDD3 including at least a portion extending along a first direction, the first direction intersecting the second direction; the power compensation lines VDD3 are coupled to the power lines VDD.

[0135] Exemplarily, the display substrate includes the plurality of power compensation lines VDD3 arranged along the second direction, and the power compensation lines VDD3 are provided in the same layer and with the same material as the first source / drain metal layer.

[0136] Exemplarily, the power compensation line VDD3 is coupled to the plurality of power lines VDD respectively.

[0137] The above arrangement enables the power line VDD and the power compensation line VDD3 to form a grid structure together. This arrangement effectively reduces the overall load of the film layer used to transmit the power signal and improves the display uniformity of the display substrate.

[0138] As shown in Figure 14, in some embodiments, the data line DA is located between the power line VDD and the second initialization signal line Vinit12; and / or, the data line DA is located between the power line VDD and the fourth initialization signal line Vinit22; and / or, the data line DA is located between the power line VDD and the second cathode compensation line VSS2.

[0139] The above configuration can effectively shield the interference of peripheral signals on the data signal transmitted by the data line DA, thereby effectively improving the stability of the data signal transmitted by the data line DA.

[0140] As shown in FIG12 , FIG14 , FIG15 and FIG23 , in some embodiments, the display substrate further includes a plurality of first light emission control signal lines EM1 and a plurality of second light emission control signal lines EM2 ; the sub-pixel driving circuit further includes a power control transistor T5 and a light emission control transistor T6 ;

[0141] The gate T5-g of the power control transistor T5 is coupled to the corresponding first light emitting control signal line EM1, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3;

[0142] The gate T6-g of the light-emitting control transistor T6 is coupled to the corresponding second light-emitting control signal line EM2, the first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light-emitting control transistor T6 is coupled to the anode of the light-emitting element included in the sub-pixel.

[0143] Exemplarily, the plurality of power lines VDD extend along the first direction, correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and are respectively coupled to the first electrodes of the power control transistors T5 in the corresponding column of sub-pixel driving circuits.

[0144] Exemplarily, the multiple first light-emitting control signal lines EM1 are arranged along the second direction, the multiple first light-emitting control signal lines EM1 correspond one-to-one to the multiple rows of sub-pixel driving circuits, and the first light-emitting control signal line EM1 is coupled to the gate T5-g of each power control transistor T5 included in the corresponding row of sub-pixel driving circuits.

[0145] Exemplarily, the multiple second light-emitting control signal lines EM2 are arranged along the second direction, the multiple second light-emitting control signal lines EM2 correspond one-to-one to the multiple rows of sub-pixel driving circuits, and the second light-emitting control signal lines EM2 are coupled to the gate T6-g of each light-emitting control transistor T6 included in the corresponding row of sub-pixel driving circuits.

[0146] The above configuration enables the power control transistor T5 and the light emission control transistor T6 to be independently controlled.

[0147] As shown in Figure 12, in some embodiments, within the layout area of ​​the same sub-pixel driving circuit, the first initialization signal line Vinit11, the first reset signal line Rst1, the second scan line GA2, the first scan line GA1, the first light-emitting control signal line EM1, the power compensation line VDD3, the second light-emitting control signal line EM2, the second reset signal line Rst2, the third initialization signal line Vinit21 and the first cathode compensation line VSS1 are arranged in sequence along the second direction.

[0148] Exemplarily, the display substrate includes a first source-drain metal layer and a second source-drain metal layer. The first initialization signal line Vinit11, the first reset signal line Rst1, the second scan line GA2, the first scan line GA1, the first emission control signal line EM1, the power compensation line VDD3, the second emission control signal line EM2, the second reset signal line Rst2, the third initialization signal line Vinit21, and the first cathode compensation line VSS1 are all provided in the same layer and material as the first source-drain metal layer. The power line VDD, the data line DA, the second initialization signal line Vinit12, the fourth initialization signal line Vinit22, and the second cathode compensation line VSS2 are all provided in the same layer and material as the second source-drain metal layer.

[0149] The above configuration helps to reduce the load on each signal line and can effectively improve the charging rate.

[0150] As shown in FIG. 5 , a driving active layer 23 , a data writing active layer 24 , a power control active layer 25 , a light emission control active layer 26 and a second reset active layer 27 are schematically shown.

[0151] As shown in FIG. 8 , the first reset active layer 21 and the compensation active layer 22 are illustrated.

[0152] As shown in FIG. 12 and FIG. 14 , a first conductive connection portion 31 , a second conductive connection portion 32 , a third conductive connection portion 33 , a fourth conductive connection portion 34 and a fifth conductive connection portion 35 are illustrated.

[0153] As shown in Figures 10, 11, 12, 19 and 20, the first conductive connection portion 31 is coupled to the top gate T3-g1 through the eighth via Via8, the first conductive connection portion 31 is coupled to the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2 through the via Via20, the first conductive connection portion 31 is coupled to the third electrode plate C23 of the capacitor structure C2 through the fifth via Via5, and the first conductive connection portion 31 is coupled to the bottom gate T3-g2 through the via Via22 and the via Via7.

[0154] The second conductive connection portion 32 is coupled to the first electrode of the data writing transistor T4 through the second via Via2 , and the second conductive connection portion 32 is coupled to the corresponding data line DA through the third via Via23 .

[0155] The third conductive connection portion 33 is coupled to the second electrode of the driving transistor T3 through a ninth via hole Via9 , and the third conductive connection portion 33 is coupled to the first electrode of the compensation transistor T2 through a twenty-first via hole Via21 .

[0156] As shown in Figures 13, 19, 23 and 24, the fourth conductive connection part 34 is coupled to the second electrode of the light emitting control transistor T6 through the fourteenth via Via14, and the fourth conductive connection part 34 is coupled to the fifth conductive connection part 35 through the twenty-fourth via Via24.

[0157] As shown in FIG13 and FIG24 , the first initialization signal line Vinit11 is coupled to the second initialization signal line Vinit12 through the twenty-fifth via Via25 , and the first initialization signal line Vinit11 is coupled to the first electrode of the first reset transistor T1 through the seventeenth via Via17 .

[0158] As shown in Figures 10, 11, 12, 19, and 20, the first reset signal line Rst1 is coupled to the gate T1-g2 of the first reset transistor T1 through the eighteenth via Via18. The first reset signal line Rst1 is coupled to the gate T1-g1 of the first reset transistor T1 through the first via Via1. It should be noted that the first reset transistor T1 comprises an oxide transistor, which includes a gate T1-g1 formed from a second gate metal layer and a gate T1-g2 formed from a third gate metal layer.

[0159] As shown in FIG. 10 , FIG. 12 , FIG. 19 and FIG. 20 , the second scan line GA2 is coupled to the gate T4 - g of the data writing transistor T4 through the third via hole Via3 .

[0160] As shown in Figures 10, 11, 12, 19, and 20, the first scan line GA1 is coupled to the gate T2-g2 of the compensation transistor T2 via a nineteenth via Via19, and the first scan line GA1 is coupled to the gate T2-g1 of the compensation transistor T2 via a fourth via Via4. It should be noted that the compensation transistor T2 comprises an oxide transistor, which includes a gate T2-g1 formed from a second gate metal layer and a gate T2-g2 formed from a third gate metal layer.

[0161] As shown in FIG. 10 , FIG. 12 , FIG. 19 and FIG. 20 , the first light emitting control signal line EM1 is coupled to the gate T5 - g of the power control transistor T5 through the tenth via hole Via10 .

[0162] As shown in Figures 10, 11, 12, 13, 19, 20 to 24, the power compensation line VDD3 is coupled to the first electrode of the power control transistor T5 through the eleventh via Via11, coupled to the second plate Cst2 of the storage capacitor Cst through the twelfth via Via12, and coupled to the power line VDD through the twenty-sixth via Via26. The second emission control signal line EM2 is coupled to the gate T6-g of the emission control transistor T6 through the thirteenth via Via13. The second reset signal line Rst2 is coupled to the gate T7-g of the second reset transistor T7 through the fifteenth via Via15. The third initialization signal line Vinit21 is coupled to the first electrode of the second reset transistor T7 through the sixteenth via Via16. The third initialization signal line Vinit21 is coupled to the fourth initialization signal line Vinit22 through the twenty-seventh via Via27. The first cathode compensation line VSS1 is coupled to the second cathode compensation line VSS2 through the twenty-eighth via hole Via28 .

[0163] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0164] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0165] In the display substrate provided by the above embodiment, by setting the gate of the compensation transistor to be coupled to the corresponding first scan line, and the gate of the data write transistor to be coupled to the corresponding second scan line, the second electrode of the data write transistor can be coupled to the gate of the drive transistor via a capacitor structure, so that the compensation transistor and the data write transistor can be independently controlled, achieving threshold compensation of the drive transistor and writing of the data signal, which can be performed separately at different time periods. In this way, under high-frequency display conditions, sufficient compensation of the threshold voltage of the drive transistor can be ensured, and at the same time, problems such as difficulty in writing data signals when displaying low grayscale and black states can be overcome. The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned display substrate, which will not be repeated here.

[0166] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0167] It should be noted that the layout area occupied by the sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0168] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0169] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0170] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0171] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0172] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0173] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0174] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A substrate, and a plurality of sub-pixels, a plurality of first scan lines, a plurality of second scan lines and a plurality of data lines all disposed on the substrate; the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor, a capacitor structure, a compensation transistor and a data writing transistor; The gate of the compensation transistor is coupled to the corresponding first scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the gate of the data writing transistor is coupled to the corresponding second scan line, the first electrode of the data writing transistor is coupled to the corresponding data line, the second electrode of the data writing transistor is coupled to the first end of the capacitor structure, and the second end of the capacitor structure is coupled to the gate of the driving transistor.

2. The display substrate according to claim 1, wherein: The driving transistor comprises a top gate, a bottom gate and a driving active layer, at least a portion of the bottom gate is located between the top gate and the substrate, and at least a portion of the driving active layer is located between the top gate and the bottom gate; The top gate and the bottom gate are coupled via a first conductive connection.

3. The display substrate according to claim 2, wherein: The capacitor structure includes a first plate and a second plate, wherein the first plate is located between the second plate and the substrate; the first plate and the bottom gate form an integral structure, and the second plate and the second electrode of the data writing transistor form an integral structure.

4. The display substrate according to claim 3, wherein: The capacitor structure further includes a third electrode plate, the second electrode plate is located between the first electrode plate and the third electrode plate, and the third electrode plate is coupled to the first conductive connection portion.

5. The display substrate according to any one of claims 1 to 4, wherein: The first scanning line includes a plurality of first scanning portions and a plurality of second scanning portions, the first scanning portions and the second scanning portions are alternately arranged along a first direction, and adjacent first scanning portions and second scanning portions are coupled; The orthographic projection of the first scanning portion on the substrate and the orthographic projection of the capacitor structure on the substrate are arranged along a first direction; the second scanning portion is arranged along the capacitor structure The portion of the boundary extends in the extension direction.

6. The display substrate according to claim 1, wherein: The data writing transistor includes a dual-gate transistor.

7. The display substrate according to claim 6, wherein: The data writing transistor comprises a data writing active layer, the gate of the data writing transistor is in a U-shaped structure, and the orthographic projection of the gate of the data writing transistor on the substrate has two overlapping areas with the orthographic projection of the data writing active layer on the substrate.

8. The display substrate according to claim 1, wherein: The display substrate further includes a first initialization signal layer and a first reset signal line; The sub-pixel driving circuit also includes a first reset transistor, a gate of the first reset transistor is coupled to the corresponding first reset signal line, a first electrode of the first reset transistor is coupled to the first initialization signal layer, and a second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first reset transistor and / or the compensation transistor include an oxide transistor.

9. The display substrate according to claim 8, wherein: The first initialization signal layer includes multiple first initialization signal lines and multiple second initialization signal lines, the first initialization signal line includes at least a portion extending along a first direction, the second initialization signal line includes at least a portion extending along a second direction, the first direction intersects with the second direction, and the first initialization signal line is coupled to the second initialization signal line.

10. The display substrate according to claim 9, wherein: The display substrate further includes a second initialization signal layer and a second reset signal line; The sub-pixel driving circuit further includes a second reset transistor, a gate of the second reset transistor is coupled to the corresponding second reset signal line, a first electrode of the second reset transistor is coupled to the second initialization signal layer, and a second electrode of the second reset transistor is coupled to the anode of the light-emitting element included in the sub-pixel; The second initialization signal layer includes a plurality of third initialization signal lines and a plurality of fourth initialization signal lines, the third initialization signal lines include at least a portion extending along the first direction, the fourth initialization signal lines include at least a portion extending along the second direction, and the third initialization signal lines are coupled to the fourth initialization signal lines.

11. The display substrate according to claim 10, wherein: The display substrate further includes a cathode layer and at least one cathode compensation layer, at least a portion of the cathode compensation layer is located between the cathode layer and the base substrate, and the cathode compensation layer includes a plurality of cathode compensation lines coupled to the cathode layer.

12. The display substrate according to claim 11, wherein: The display substrate includes a first cathode compensation layer and a second cathode compensation layer, at least a portion of the first cathode compensation layer is located between the second cathode compensation layer and the base substrate; the first cathode compensation layer includes a plurality of first cathode compensation lines, the first cathode compensation lines include at least a portion extending along the first direction; the second cathode compensation layer includes a plurality of second cathode compensation lines, the second cathode compensation lines include at least a portion extending along the second direction; the first cathode compensation lines are coupled to the second cathode compensation lines.

13. The display substrate according to claim 12, wherein: The second initialization signal line, the fourth initialization signal line and the second cathode compensation line are sequentially and cyclically arranged along the first direction.

14. The display substrate according to claim 12, wherein: The first reset transistor includes a first reset active layer, and the compensation transistor includes a compensation active layer; The display substrate further comprises a plurality of power lines, wherein the power lines include at least a portion extending along the second direction; an orthographic projection of the power lines on the base substrate at least partially overlaps with an orthographic projection of the first reset active layer on the base substrate; And / or, an orthographic projection of the power line on the substrate at least partially overlaps with an orthographic projection of the compensation active layer on the substrate.

15. The display substrate according to claim 14, wherein: The display substrate further includes a plurality of power compensation lines, each of which includes at least a portion extending along a first direction intersecting the first direction and the second direction; and the power compensation lines are coupled to the power lines.

16. The display substrate according to claim 14, wherein: The data line is located between the power line and the second initialization signal line; and / or, the data line is located between the power line and the fourth initialization signal line; and / or, the data line is located between the power line and the second cathode compensation line.

17. The display substrate according to claim 14, wherein: The display substrate further includes a plurality of first light emission control signal lines and a plurality of second light emission control signal lines; the sub-pixel driving circuit further includes a power supply control transistor and a light emission control transistor; The gate of the power control transistor is coupled to the corresponding first light emitting control signal line. The first electrode of the power control transistor is coupled to the corresponding power line, and the second electrode of the power control transistor is coupled to the first electrode of the driving transistor; The gate of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is coupled to the anode of the light-emitting element included in the sub-pixel.

18. The display substrate according to claim 17, wherein: In the layout area of ​​the same sub-pixel driving circuit, the first initialization signal line, the first reset signal line, the second scanning line, the first scanning line, the first light-emitting control signal line, the power compensation line, the second light-emitting control signal line, the second reset signal line, the third initialization signal line and the first cathode compensation line are arranged in sequence along the second direction.

19. The display substrate according to claim 18, wherein: The display substrate includes a first source-drain metal layer, and the first initialization signal line, the first reset signal line, the second scan line, the first scan line, the first light-emitting control signal line, the power compensation line, the second light-emitting control signal line, the second reset signal line, the third initialization signal line and the first cathode compensation line are all arranged in the same layer and with the same material as the first source-drain metal layer.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

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