Clocked comparator with series decision feedback equalization

Abstract

An input stage of a comparator includes: a first transistor, wherein a gate of the first transistor is coupled to a first input of the input stage; a second transistor, wherein a gate of the second transistor is coupled to a second input of the input stage; a third transistor coupled in series with the first transistor; and a fourth transistor coupled in series with the second transistor. The input stage also includes a fifth transistor, where a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor. The input stage also includes a sixth transistor, where a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit and priority of U.S. Patent Application Serial No. 17 / 985,498, filed on November 11, 2022, with the United States Patent and Trademark Office, the entire content of which is incorporated herein by reference in its entirety as if set forth fully hereinafter and for all applicable purposes. Background Art Technical Field

[0003] Aspects of the present disclosure generally relate to equalizers, and more particularly, to decision - feedback equalizers. Background Art

[0005] In a system, data may be transmitted from a transmitter to a receiver over a link using symbols. Due to non - idealities in the link (e.g., notches in the frequency response of the link due to reflections), the incoming symbols at the receiver are distorted. This distortion can cause the symbols to spread into each other, resulting in inter - symbol interference (ISI) at the receiver. The receiver may employ decision - feedback equalization (DFE) to reduce ISI. Summary of the Invention

[0006] The following presents a simplified summary of one or more specific implementations in order to provide a basic understanding of such specific implementations. This summary is not an exhaustive overview of all contemplated specific implementations, and is not intended to identify key or critical elements of all specific implementations, nor is it intended to depict the scope of any or all specific implementations. Its sole purpose is to present some concepts of one or more specific implementations in a simplified form as a prelude to the more detailed description that follows.

[0007] A first aspect relates to a comparator. The comparator includes an input stage. The input stage includes a first transistor, wherein the gate of the first transistor is coupled to a first input of the input stage; and a second transistor, wherein the gate of the second transistor is coupled to a second input of the input stage. The input stage further includes a third transistor serially coupled to the first transistor and a fourth transistor serially coupled to the second transistor. The input stage further includes a fifth transistor, wherein the gate of the fifth transistor is configured to receive a first decision - feedback signal, and the drain of the fifth transistor is coupled to the gate of the third transistor. The input stage further includes a sixth transistor, wherein the gate of the sixth transistor is configured to receive a second decision - feedback signal, and the drain of the sixth transistor is coupled to the gate of the fourth transistor.

[0008] The second aspect relates to a method of operating a comparator. The comparator includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the third transistor is coupled in series with the first transistor and coupled between the first transistor and a first node, and the fourth transistor is coupled in series with the second transistor and coupled between the second transistor and a second node. The method includes: driving a gate of the first transistor with a first signal; driving a gate of the second transistor with a second signal; adjusting a first voltage at the gate of the third transistor based on a first decision feedback signal; adjusting a second voltage at the gate of the fourth transistor based on a second decision feedback signal; and making a bit decision based on a third voltage on the first node and a fourth voltage on the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system in accordance with certain aspects of the present disclosure is shown.

[0010] Figure 2 An example of signal distortion caused by non-idealities in a link in accordance with certain aspects of the present disclosure is shown.

[0011] Figure 3 A conceptual diagram of decision feedback equalization in accordance with certain aspects of the present disclosure is shown.

[0012] Figure 4 An example of a comparator including a parallel differential pair for implementing decision feedback equalization (DFE) in accordance with certain aspects of the present disclosure is shown.

[0013] Figure 5 is a timing diagram showing exemplary waveforms of a comparator in accordance with certain aspects of the present disclosure Figure 4 therein.

[0014] Figure 6 An example of a comparator including a cascaded DFE in accordance with certain aspects of the present disclosure is shown.

[0015] Figure 7 An exemplary implementation of a first switch circuit and a second switch circuit in accordance with certain aspects of the present disclosure is shown.

[0016] Figure 8 An exemplary implementation of a regeneration stage in accordance with certain aspects of the present disclosure is shown.

[0017] Figure 9 An exemplary implementation of an inverter in a regeneration stage in accordance with certain aspects of the present disclosure is shown.

[0018] Figure 10 An example of a comparator including a cascaded DFE with multiple taps in accordance with certain aspects of the present disclosure is shown.

[0019] Figure 11 An example of a latch coupled to a comparator is shown in accordance with certain aspects of the present disclosure.

[0020] Figure 12 An example of a receiver including a time-interleaved comparator is shown in accordance with certain aspects of the present disclosure.

[0021] Figure 13A An example of a system including a comparator and a deserializer is shown in accordance with certain aspects of the present disclosure.

[0022] Figure 13B An example of a system including a comparator and a memory is shown in accordance with certain aspects of the present disclosure.

[0023] Figure 14 An example of a comparator configured for pseudo-differential signals is shown in accordance with certain aspects of the present disclosure.

[0024] Figure 15 Another example of a comparator including a cascaded DFE is shown in accordance with certain aspects of the present disclosure.

[0025] Figure 16 A flowchart exemplifying a method of operating a comparator in accordance with certain aspects of the present disclosure. Detailed Description

[0026] The following detailed description, presented in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. It will be apparent, however, to one of ordinary skill in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0027] Figure 1 An example of system 110 is shown, in which data is transmitted from transmitter 112 to receiver 114 via link 130 (e.g., a serial link). Transmitter 112 receives bits from a data source (not shown) and transmits these bits as a sequence of symbols via link 130. At receiver 114, limiter 140 (also referred to as a comparator) receives the symbols from link 130 and converts these symbols into a sequence of bits (i.e., a bit stream). The bit stream may be transmitted to a processor (not shown) or another circuit for further processing. It should be understood that receiver 114 may include Figure 1 one or more additional components not explicitly shown. System 110 may also include a serializer / deserializer (SerDes), a double data rate (DDR) dynamic random access memory (DRAM), and / or another circuit, as further discussed below.

[0028] As discussed above, transmitter 112 may send bits as symbols over link 130. In some aspects, each symbol carries one bit. Each symbol may be in the form of a pulse, where the amplitude of the pulse (e.g., voltage) represents the bit value (i.e., one or zero) of the corresponding bit. Limiter 140 receives the symbol and makes a bit decision based on the received symbol to obtain the corresponding bit. The bit decision may be made based on the voltage of the received symbol or another attribute of the received symbol.

[0029] Figure 2 An example is shown where transmitter 112 sends symbol 210 over link 130 that represents a bit value of one. As Figure 2 shown, the symbol 220 received at receiver 114 is distorted due to non-idealities in link 130 (e.g., finite bandwidth of link 130, reflections, etc.). In this example, the distortion spreads the symbol 220 received at receiver 114. This may cause symbol 220 to spread into the next symbol (not shown) at receiver 114, resulting in inter-symbol interference (ISI).

[0030] To reduce ISI, receiver 114 may employ decision feedback equalization. In this regard, Figure 3 is a conceptual diagram showing an example of decision feedback equalization implemented in receiver 114 according to some aspects.

[0031] In Figure 3 the example of, receiver 114 includes delay elements 315-1 to 315-n (e.g., latches), multipliers 320-1 to 320-n, and an adder 325. Adder 325 may be coupled between link 130 and the input of limiter 140. Delay elements 315-1 to 315-n are coupled in series, where the first delay element in delay elements 315-1 is coupled to the output of limiter 140. Each of multipliers 320-1 to 320-n is coupled to the output of a corresponding one of delay elements 315-1 to 315-n and is configured to multiply the output of the corresponding one of delay elements 315-1 to 315-n by a corresponding weight W1 to W n . Each weight may be positive or negative. In Figure 3 the example of, adder 325 is configured to add the outputs of multipliers 320-1 to 320-n to the current symbol received at receiver 114.

[0032] In operation, delay elements 315-1 to 315-n provide n previous bit decisions (e.g., n previous bit values) from limiter 140. Multipliers 320-1 to 320-n multiply the n previous bit decisions by corresponding weights W1 to W n。The adder 325 adds the outputs of the multipliers 320-1 to 320-n to obtain a weighted sum of the n previous bit decisions and adds this weighted sum to the current symbol at the receiver 114. The weighted sum can be positive or negative.

[0033] Thus, the weighted sum of the n previous bit decisions is added to the current symbol to reduce ISI. The weights W1 to W can be adjusted (i.e., programmed) according to the characteristics of the link 130 (e.g., the frequency response of the link 130). n values. Figure 3 An example of an n-tap decision feedback equalization is shown where the weighted sum of the n previous bit decisions is added to the current symbol. In this example, the decision feedback equalization implements a finite impulse response (FIR) filter where the weights W1 to W n correspond to the coefficients of the FIR filter.

[0034] It should be understood that any one of a variety of different circuits can be used to implement Figure 3 the exemplary decision feedback equalization conceptually illustrated in. It should also be understood that the decision feedback equalization can be implemented in various ways and Figure 3 two or more of the components shown in can be combined into one component and / or incorporated into the limiter 140. In other words, it should be understood that Figure 3 the examples are intended to illustrate the concept of decision feedback equalization and are not intended to limit the present disclosure to any one specific implementation of a decision feedback equalizer.

[0035] It should be understood that in some specific implementations, symbols can be transmitted over a differential serial link using differential signals. In these specific implementations, the differential signal includes a first signal and a second signal, where the bit value of the symbol is represented by the polarity of the differential signal. For example, when the first signal is greater than the second signal, the symbol can represent the bit value one, and when the second signal is greater than the first signal, the symbol can represent the bit value zero. An example of a DFE for differential signals is discussed below.

[0036] Figure 4 An example of a comparator 405 that can be used to implement a limiter (e.g., limiter 140) according to certain aspects is shown. The comparator 405 can also be referred to as a sense amplifier, a limiter, or another term. The comparator 405 is configured to receive a differential input signal including a first signal inp and a second signal inn and make a bit decision (i.e., resolve the data bit) based on the differential input signal. In this example, the comparator 405 uses a parallel differential pair and current summation to implement decision feedback equalization (DFE), as further discussed below.

[0037] In this example, comparator 405 includes an input stage 410 and a regeneration stage 460. The input stage 410 is configured to receive a differential input signal and generate a first voltage v1 and a second voltage v2 based on the differential input signal. The regeneration stage 460 is configured to resolve data bits based on the first voltage v1 and the second voltage v2, as further discussed below.

[0038] The input stage 410 includes an input differential pair 420, a feedback differential pair 430, a first current source 426, a second current source 436, a first switch 450, a second switch 452, a first capacitor 440, and a second capacitor 445. The input differential pair 420 and the feedback differential pair 430 are coupled in parallel, where the input differential pair 420 is driven by the differential input signal and the feedback differential pair 430 provides DFE, as further discussed below.

[0039] In this example, the input differential pair 420 includes a first transistor 422 and a second transistor 424. A first signal inp (e.g., a first input voltage) is input to the gate of the first transistor 422 and a second input signal inn (e.g., a second input voltage) is input to the gate of the second transistor 424. In Figure 4 the example shown, each of the first transistor 422 and the second transistor 424 is implemented with a corresponding n-type field effect transistor (NFET). However, it should be understood that the present disclosure is not limited to this example.

[0040] The first switch 450 is coupled between the supply rail 470 and the drain of the first transistor 422, and the second switch 452 is coupled between the supply rail 470 and the drain of the second transistor 424. The supply rail 470 has a supply voltage Vdd (e.g., provided by a power distribution network). The switches 450 and 452 are clocked by a clock signal clk. In Figure 4 the example shown, each of the switches 450 and 452 is implemented with a corresponding p-type field effect transistor (PFET), where the gate of the corresponding PFET is driven by the clock signal clk. As further discussed below, the first voltage v1 output by the input stage 410 is provided at a first node 412 between the first switch 450 and the first transistor 422, and the second voltage v2 output by the input stage 410 is provided by a second node 414 between the second switch 452 and the second transistor 424.

[0041] The first current source 426 is coupled between the sources of the first transistor 422 and the second transistor 424 and the low rail 475. The low rail 475 has a voltage Vss (i.e., a potential) that is lower than the supply voltage Vdd of the supply rail 470. For example, the low rail 475 may be coupled to ground. The first current source 426 is configured to provide a bias current Ibias to the first transistor 422 and the second transistor 424.

[0042] The feedback differential pair 430 includes a third transistor 432 and a fourth transistor 434. A first decision feedback signal dfp1 can be input to the gate of the third transistor 432, and a second decision feedback signal dfn1 can be input to the gate of the fourth transistor 434. The first decision feedback signal dfp1 can correspond to a previous bit decision of the comparator 405, and the second decision feedback signal dfn1 can correspond to the complement (i.e., the inverse code) of the previous bit decision of the comparator 405, or vice versa. The first decision feedback signal dfp1 and the second decision feedback signal dfn1 can come from a latch (not shown) coupled to the comparator 405, where the latch is configured to latch the previous bit decision of the comparator 405 and the complement of the previous bit decision of the comparator 405. The latch can be a set-reset (SR) latch or another type of latch. The drain of the third transistor 432 is coupled to the first node 412, and the drain of the fourth transistor 434 is coupled to the second node 414.

[0043] A second current source 436 is coupled between the sources of the third transistor 432 and the fourth transistor 434 and the low rail 475 (e.g., ground). The second current source 436 is configured to provide a bias current Ibf1 to the third transistor 432 and the fourth transistor 434. As discussed further below, the weight given to the previous bit decision in the DFE can be set by the bias current Ibf1.

[0044] In Figure 4 the example shown, a first capacitor 440 is coupled between the first node 412 and the low rail 475, and a second capacitor 445 is coupled between the second node 414 and the low rail 475. The first capacitor 440 and the second capacitor 445 can have approximately the same capacitance.

[0045] The regeneration stage 460 has a first input terminal 462, a second input terminal 464, a first output terminal 466, and a second output terminal 468. The first input terminal 462 is coupled to the first node 412 of the input stage 410, and the second input terminal 464 is coupled to the second node 414 of the input stage 410. The regeneration stage 460 is configured to receive a first voltage v1 and a second voltage v2 via the first input terminal 462 and the second input terminal 464, and make a bit decision based on the first voltage v1 and the second voltage v2, as discussed further below. The first output terminal 466 and the second output terminal 468 can be coupled to the latch (e.g., a set-reset (SR) latch or another type of latch) discussed above.

[0046] Now, exemplary operations of the comparator 405 will be discussed with reference to Figure 5 For ease of discussion, the exemplary operation of the comparator 405 without DFE will be discussed first, and then the exemplary operation of the comparator 405 with DFE will be discussed.

[0047] Figure 5 It is a timing diagram showing an example of a clock signal clk for timing a comparator 405, a first voltage v1, and a second voltage v2. In this example, the comparator 405 resolves bit values during each cycle (i.e., period) of the clock signal clk. For each clock cycle, the comparator 405 may operate in a reset phase when the clock signal clk is low and in a sense phase when the clock signal clk is high. The sense phase may also be referred to as an integration phase or another term. The clock signal may be a periodic signal that oscillates between a high clock frequency (i.e., logic one) and a low clock frequency (i.e., logic zero). The clock signal may be from a phase-locked loop or another type of clock circuit.

[0048] During the reset phase of each clock cycle, the first switch 450 and the second switch 452 are turned on. This causes the first capacitor 440 to be charged to the supply voltage Vdd through the first switch 450, and the first voltage v1 at the first node 412 rises to approximately the supply voltage Vdd. This also causes the second capacitor 445 to be charged to the supply voltage Vdd through the second switch 452, and the second voltage v2 at the second node 414 rises to approximately the supply voltage Vdd. Thus, the reset phase of each clock cycle resets the first voltage v1 and the second voltage v2 to approximately the supply voltage Vdd.

[0049] During the sense phase of each clock cycle, the first switch 450 and the second switch 452 are turned off. The first transistor 422 provides a first current to discharge the first capacitor 440 based on the first input signal inp, and the second transistor 424 provides a second current to discharge the second capacitor 445 based on the second input signal inn. The first capacitor 440 and the second capacitor 445 discharge at different rates according to the first current and the second current, which in turn depend on the first input signal inp and the second input signal inn. The different discharge rates cause the first voltage v1 and the second voltage v2 to decrease (i.e., ramp down) at different rates based on the first input signal inp and the second input signal inn during the sense phase of each clock cycle, as Figure 5 shown.

[0050] At Figure 5In the example shown, during the sensing phase of the first cycle of the clock signal clk, the first input signal inp is greater than the second input signal inn. In this case, the first current from the first transistor 422 is greater than the second current from the second transistor 424, which causes the first capacitor 440 to discharge faster than the second capacitor 445, and the first voltage v1 to decrease (i.e., slope down) faster than the second voltage v2. Thus, the first voltage v1 and the second voltage v1 separate (i.e., diverge), where the first voltage v1 is lower than the second voltage v2, as Figure 5 shown. In this example, the regeneration stage 460 can be configured to resolve the bit value one when the first voltage v1 slopes down at a faster rate than the second voltage v2, or vice versa. The regeneration stage 460 can output the resolved bit value at the first output terminal 466 and output the complement (i.e., inverse) of the resolved bit value at the second output terminal 468.

[0051] Additionally, in Figure 5 the example shown, during the sensing phase of the second cycle of the clock signal clk, the second input inn is greater than the first input signal inp. In this case, the second current from the second transistor 424 is greater than the first current from the first transistor 422, which causes the second capacitor 445 to discharge faster than the first capacitor 440, and the second voltage v2 to decrease (i.e., slope down) faster than the first voltage v1. Thus, the first voltage v1 and the second voltage v2 separate (i.e., diverge), where the first voltage v1 is greater than the second voltage v2, as Figure 5 shown. In this example, the regeneration stage 460 can be configured to resolve the bit value zero when the second voltage v2 slopes down at a faster rate than the first voltage v1, or vice versa. The regeneration stage 460 can output the resolved bit value at the first output terminal 466 and output the complement (i.e., inverse) of the resolved bit value at the second output terminal 468.

[0052] In Figure 4 the example shown, the DFE is provided by the feedback differential pair 430, which is coupled in parallel with the input differential pair 420. In this example, the third transistor 432 provides a third current based on the first decision feedback signal dfp1. The third current is added to the first current of the input differential pair 420 at the first node 412. Thus, the first capacitor 440 discharges through the sum of the first current and the third current. Thus, the third current adjusts the discharge rate of the first capacitor 440 (and thus the slope down rate of the first voltage v1) based on the first decision feedback signal dfp1.

[0053] The fourth transistor 434 provides a fourth current based on the second decision feedback signal dfn1. The fourth current is added to the second current of the input differential pair at the second node 414. Accordingly, the second capacitor 445 is discharged by the sum of the second current and the fourth current. Thus, the fourth current adjusts the discharge rate of the second capacitor 445 (and thus the slew rate of the second voltage v2) based on the second decision feedback signal dfn1.

[0054] Accordingly, the comparator 405 uses parallel differential pairs and current summing to provide DFE. The weight of the previous bit decision can be set by the bias current Ibf1 of the second current source 436. The higher the bias current Ibf1, the greater the weight.

[0055] Figure 4 An example of a 1-tap DFE showing the most recent previous bit decision (i.e., the bit decision corresponding to the clock cycle immediately preceding the current clock cycle) using the comparator 405 is shown. The DFE in the comparator 405 can be extended to include additional previous bit decisions (i.e., bit decisions corresponding to earlier clock cycles) by coupling additional feedback differential pairs in parallel with the input differential pair 420, where each of the additional feedback differential pairs provides feedback for a corresponding one of the additional previous bit decisions.

[0056] Figure 4 A challenge with the DFE method illustrated in is that coupling the differential pairs in parallel with the input differential pair 420 to define the DFE can significantly increase the parasitic capacitance on the first node 412 and the second node 414. The increased parasitic capacitance can significantly slow down the ramp rates of the first voltage v1 and the second voltage v2, which increases the time required for the voltages v1 and v2 to separate and for the regeneration stage 460 to make a bit decision (i.e., resolve the bit). The increased time required to make a bit decision reduces the frequency at which the comparator 405 can operate and thus reduces the rate at which data can be transmitted using the comparator 405.

[0057] To address this issue, aspects of the present disclosure use series transistors to reduce parasitic capacitance to provide DFE, where the series transistors are coupled in series with the transistors of the input differential pair and the gates of the series transistors are coupled to one or more feedback differential pairs. The series transistors help isolate the signal path of the input stage from the parasitic capacitance of the one or more feedback differential pairs, thereby reducing the capacitive load on the signal path. The reduced capacitive load allows for a higher data rate. The above and other features according to aspects of the present disclosure are discussed further below.

[0058] Figure 6An example of a comparator 605 in accordance with aspects of the present disclosure is shown. The comparator 605 is configured to receive a differential input signal including a first signal inp and a second signal inn, and make a bit decision (i.e., resolve a data bit) based on the differential input signal. The comparator 605 may also be used for pseudo-differential signals, as further discussed below.

[0059] The comparator 605 includes an input stage 610 and a regeneration stage 680. The input stage 610 is configured to receive the differential input signal and generate a first voltage v1 and a second voltage v2 based on the differential input signal. The regeneration stage 460 is configured to resolve the data bit based on the first voltage v1 and the second voltage v2, as further discussed below.

[0060] The input stage 610 includes an input differential pair 620, a feedback differential pair 640, a current source 626, a first resistor 650, a second resistor 655, a first switch circuit 660, and a second switch circuit 665.

[0061] In this example, the input differential pair 620 includes a first transistor 622 and a second transistor 624. The gate of the first transistor 622 is coupled to a first input terminal 612 of the input stage 610 configured to receive the first signal inp (e.g., a first input voltage). The gate of the second transistor 624 is coupled to a second input terminal 614 of the input stage 610 configured to receive the second input signal inn (e.g., a second input voltage). Thus, the first transistor 622 and the second transistor 624 are driven by the differential input signal. The first transistor 622 is configured to generate a first current based on the first input signal inp, and the second transistor 624 is configured to generate a second current based on the second input signal inn.

[0062] In Figure 6 the example shown, each of the first transistor 622 and the second transistor 624 is implemented with a corresponding p-type field effect transistor (PFET). However, it should be understood that the present disclosure is not limited to this example. For example, in other embodiments, each of the first transistor 622 and the second transistor 624 may be implemented with a corresponding n-type field effect transistor (NFET).

[0063] In Figure 6In the example shown, the first switch circuit 660 is coupled between the power supply rail 690 and the sources of the first transistor 622 and the second transistor 624. The power supply rail 690 has a supply voltage Vdd (e.g., provided by a power distribution network). The first switch circuit 660 is configured to receive a clock signal clk. As discussed further below, the first switch circuit 660 is configured to couple the sources of the first transistor 622 and the second transistor 624 to the power supply rail 690, or decouple the sources of the first transistor 622 and the second transistor 624 from the power supply rail 690, based on the clock signal clk (e.g., based on the logic state of the clock signal clk).

[0064] In this example, the comparator 605 further includes a third transistor 630 coupled in series with the first transistor 622, and a fourth transistor 635 coupled in series with the second transistor 624. As discussed further below, the third transistor 630 and the fourth transistor 635 are used to provide DFE. As used herein, two transistors are "coupled in series" when their channels are coupled in series. The channel of a transistor is located between the drain and the source of the transistor. The third transistor 630 may also be referred to as the first series transistor because the third transistor 630 is coupled in series with the first transistor 622, and the fourth transistor 635 may also be referred to as the second series transistor because the fourth transistor 635 is coupled in series with the second transistor 624.

[0065] In Figure 6 the example shown, the third transistor 630 is coupled between the drain of the first transistor 622 and the first node 632, and the fourth transistor 635 is coupled between the drain of the second transistor 624 and the second node 637. In this example, a first voltage v1 is provided at the first node 632, and a second voltage v2 is provided at the second node 637. Each of the third transistor 630 and the fourth transistor 635 may be implemented with a corresponding PFET, as Figure 6 shown in the example in. However, it should be understood that the present disclosure is not limited to this example. For example, in other embodiments, each of the third transistor 630 and the fourth transistor 635 may be implemented with a corresponding NFET.

[0066] In Figure 6In the example shown, the second switching circuit 665 is coupled between the first node 632 and the low rail 695, and is also coupled between the second node 637 and the low rail 695. The low rail 695 has a voltage Vss (i.e., potential) that is lower than the supply voltage Vdd of the supply rail 690. For example, the low rail 695 may be coupled to ground. The second switching circuit 665 is configured to receive the clock signal clk. As further discussed below, the second switching circuit 665 is configured to couple the first node 632 and the second node 637 to the low rail 695, or decouple the first node 632 and the second node 637 from the low rail 695, based on the clock signal clk (e.g., based on the logic state of the clock signal clk).

[0067] The feedback differential pair 640 includes a fifth transistor 642 and a sixth transistor 644. The first decision feedback signal dfp1 can be input to the gate of the fifth transistor 642, and the second decision feedback signal dfn1 can be input to the gate of the sixth transistor 644. The first decision feedback signal dfp1 can correspond to a previous bit decision of the comparator 605, and the second decision feedback signal dfn1 can correspond to the complement (i.e., inverse) of the previous bit decision of the comparator 605, or vice versa. The first decision feedback signal dfp1 and the second decision feedback signal dfn1 can come from a latch ( Figure 6 not shown in the figure) coupled to the comparator 605, where the latch is configured to latch the previous bit decision of the comparator 605 and the complement of the previous bit decision of the comparator 605. The latch can be a set-reset (SR) latch or another type of latch.

[0068] The fifth transistor 642 is configured to generate a third current based on the first decision feedback signal dfp1, and the sixth transistor 644 is configured to generate a fourth current based on the second decision feedback signal dfn1. In Figure 6 the example shown, each of the fifth transistor 642 and the sixth transistor 644 is implemented with a corresponding PFET. However, it should be understood that the present disclosure is not limited to this example. For example, in other embodiments, each of the fifth transistor 642 and the sixth transistor 644 can be implemented with a corresponding NFET.

[0069] The current source 626 is coupled between the supply rail 690 and the sources of the fifth transistor 642 and the sixth transistor 644. The current source 626 is configured to provide a bias current Ibf1 to the fifth transistor 642 and the sixth transistor 644. As further discussed below, the weight given to the previous bit decision can be set by the bias current Ibf1.

[0070] A first resistor 650 is coupled between the drain of a fifth transistor 642 and a low rail 695, and a second resistor 655 is coupled between the drain of a sixth transistor 644 and the low rail 695. Each of the resistors 650 and 655 can be implemented with a respective passive resistor, a respective active resistor (i.e., a resistor implemented with one or more active devices), or any combination thereof.

[0071] In this example, the gate of a third transistor 630 is coupled to a third node 646 between the fifth transistor 642 and the first resistor 650, and the gate of a fourth transistor 635 is coupled to a fourth node 648 between the sixth transistor 644 and the second resistor 655. A third current of the fifth transistor 642 flows through the first resistor 650 to generate a first gate voltage vg1 for the third transistor 630 at the third node 646. A fourth current of the sixth transistor 644 flows through the second resistor 655 to generate a second gate voltage vg2 for the fourth transistor 635 at the fourth node 648. Thus, the gate voltages vg1 and vg2 applied to the gates of the third transistor 630 and the fourth transistor 635 depend on the third current and the fourth current, which in turn depend on a first decision feedback signal dfp1 and a second decision feedback signal dfn1.

[0072] A regeneration stage 680 has a first input terminal 682, a second input terminal 684, a first output terminal 686, and a second output terminal 688. The first input terminal 682 is coupled to a first node 632 of an input stage 610, and the second input terminal 684 is coupled to a second node 637 of the input stage 610. The regeneration stage 680 is configured to receive a first voltage v1 and a second voltage v2 via the first input terminal 682 and the second input terminal 684, and make a bit decision based on the first voltage v1 and the second voltage v2, as further discussed below. The first output terminal 686 and the second output terminal 688 can be coupled to the latch (e.g., a set-reset (SR) latch or another type of latch) discussed above.

[0073] Exemplary operation of the comparator 605 will now be discussed in accordance with certain aspects. For ease of discussion, exemplary operation of the comparator 605 without DFE will be discussed first, and then exemplary operation of the comparator 605 with DFE will be discussed.

[0074] In certain aspects, the comparator 605 resolves a bit value during each cycle (i.e., period) of a clock signal clk. For each clock cycle, the comparator 605 can operate in a reset phase when the clock signal clk is high, and operate in a sense phase when the clock signal clk is low, or vice versa. The sense phase can also be referred to as an integration phase or another term.

[0075] During a reset phase of each clock cycle, the first switch circuit 660 is configured to decouple the sources of the first transistor 622 and the second transistor 624 from the supply rail 690, and the second switch circuit 665 is configured to couple the first node 632 and the second node 637 to the low rail 695. This causes the capacitances on the first node 632 to discharge to the low rail 695 through the second switch circuit 665, and the capacitances on the second node 637 to discharge to the low rail 695 through the second switch circuit 665. Thus, the second switch circuit 665 resets the first node 632 and the second node 637 to the voltage Vss of the low rail 695 during the reset phase. For an example where the low rail 695 is coupled to ground, the first node 632 and the second node 637 are reset to ground. The capacitances on the first node 632 and the second node 637 may include the capacitances from the first input terminal 682 and the second input terminal 684 of the regeneration stage 680.

[0076] During a sense phase of each clock cycle, the first switch circuit 660 is configured to couple the sources of the first transistor 622 and the second transistor 624 to the supply rail 690, and the second switch circuit 665 is configured to decouple the first node 632 and the second node 637 from the low rail 695. This allows the first transistor 622 to generate a first current based on the first input signal inp, and the second transistor 624 to generate a second current based on the second input signal inn. The first current charges the capacitance on the first node 632, thereby increasing (i.e., ramping up) the first voltage v1. The second current charges the capacitance on the second node 637, thereby increasing (i.e., ramping up) the second voltage v2. The first voltage v1 and the second voltage v2 increase (i.e., ramp up) at different rates according to the first current and the second current, which in turn depend on the first input signal inp and the second input signal inn. The regeneration stage 680 then makes a bit decision (i.e., determines the bit value) based on which of the first voltage v1 and the second voltage v2 ramps up faster, as discussed further below.

[0077] When the first input signal inp is greater than the second input signal inn during the sense phase of the clock cycle, the second current is greater than the first current. In this case, the second node 637 charges faster than the first node 632, causing the second voltage v2 at the second node 637 to increase (i.e., ramp up) faster than the first voltage v1 at the first node 632. Thus, the first voltage v1 and the second voltage v2 separate, where the second voltage v2 is greater than the first voltage v1. In this example, the regeneration stage 680 may be configured to resolve (i.e., determine) the bit value one when the second voltage v2 ramps up faster than the first voltage v1, or vice versa. The regeneration stage 680 may output the resolved bit value at the first output terminal 686, and the complement of the resolved bit value at the second output terminal 688.

[0078] When the second input signal inn is greater than the first input signal inp during the sensing phase of the clock cycle, the first current is greater than the second current. In this case, the first node 632 charges faster than the second node 637, causing the first voltage v1 at the first node 632 to increase (i.e., ramp) faster than the second voltage v2 at the second node 637. Thus, the first voltage v1 and the second voltage v2 separate, where the first voltage v1 is greater than the second voltage v2. In this example, the regeneration stage 680 can be configured to resolve (i.e., determine) a bit value of zero when the first voltage v1 ramps faster than the second voltage v2, or vice versa. The regeneration stage 680 can output the resolved bit value at the first output terminal 686 and the complement of the resolved bit value at the second output terminal 688.

[0079] Exemplary operation of the comparator 605 having DFE provided by the feedback differential pair 640 and the third transistor 630 and the fourth transistor 635 will now be discussed in accordance with some aspects. As discussed above, the fifth transistor 642 generates a third current based on the first decision feedback signal dfp1, and the sixth transistor 644 generates a fourth current based on the second decision feedback signal dfn1. The third current flows through the first resistor 650 to generate a first gate voltage vg1 that is input to the gate of the third transistor 630. The first gate voltage vg1 controls the conductance of the third transistor 630, which adjusts the ramp rate of the first voltage v1 at the first node 632. Since the first gate voltage vg1 depends on the third current (which in turn depends on the first decision feedback signal dfp1), the adjustment of the ramp rate of the first voltage v1 by the third transistor 630 depends on the first decision feedback signal dfp1.

[0080] The fourth current flows through the second resistor 655 to generate a second gate voltage vg2 that is input to the gate of the fourth transistor 635. The second gate voltage vg2 controls the conductance of the fourth transistor 635, which adjusts the ramp rate of the second voltage v2 at the second node 637. Since the second gate bias voltage vg2 depends on the fourth current (which in turn depends on the second decision feedback signal dfn1), the adjustment of the ramp rate of the second voltage v2 by the fourth transistor 635 depends on the second decision feedback signal dfn1.

[0081] Thus, in this example, the feedback differential pair 640 and the third transistor 630 and fourth transistor 635 provide DFE by adjusting the ramp rates of the first voltage v1 and the second voltage v2 based on the first decision feedback signal dfp1 and the second decision feedback signal dfn1. The weight of the DFE can be set by the bias current Ibf1 of the current source 626. In this regard, the current source 626 can be implemented with a programmable current source 626, where the bias current Ibf1 can be programmed based on the desired weight of the DFE. The desired weight can be determined, for example, based on the characteristics (e.g., frequency response) of a link (e.g., link 130) coupled to the input terminals 612 and 614 of the comparator 605.

[0082] compared to the parallel DFE method in which the first node 632 and the second node 637 are in the signal path Figure 4 The comparator 605 reduces the capacitive load on the signal path of the input stage 610. This is because the third transistor 630 and the fourth transistor 635 help isolate the signal path from the parasitic capacitance of the feedback differential pair 640, thereby reducing the capacitive load on the signal path. The reduced capacitive load allows the comparator 605 to operate at a higher frequency for higher data rates. In contrast, in the Figure 4 method illustrated in, the feedback differential pair 430 is coupled in parallel with the input differential pair 420, where the parasitic capacitance of the feedback differential pair 430 is directly coupled to the nodes 412 and 414, which can result in a significant increase in the capacitive load.

[0083] For an example where the first decision feedback signal dfp1 corresponds to the previous bit decision of the comparator 605, the first decision feedback signal dfp1 can have a voltage approximately equal to the supply voltage Vdd when the previous bit decision has a bit value of one, and can have a voltage approximately equal to the voltage Vss (e.g., ground) of the low rail 695 when the previous bit decision has a bit value of zero. For an example where the second decision feedback signal dfn1 corresponds to the complement of the previous bit decision of the comparator 605, the second decision feedback signal dfn1 can have a voltage approximately equal to the supply voltage Vdd when the complement of the previous bit decision has a bit value of one, and can have a voltage approximately equal to the voltage Vss (e.g., ground) of the low rail 695 when the complement of the previous bit decision has a bit value of zero. However, it should be understood that the present disclosure is not limited to this example.

[0084] For example, in some specific implementations, the first decision feedback signal dfp1 may have a voltage higher than a threshold when the previous bit decision has a bit value of one, and may have a voltage lower than the threshold when the previous bit decision has a bit value of zero. Additionally, in this example, the second decision feedback signal dfn1 may have a voltage higher than a threshold when the complement of the previous bit decision has a bit value of one, and may have a voltage lower than the threshold when the complement of the previous bit decision has a bit value of zero. Thus, the voltage of the first decision feedback signal dfp1 does not need to fully reach Vdd or Vss, and the voltage of the second decision feedback signal dfn1 does not need to fully reach Vdd or Vss. For example, the voltages of the first decision feedback signal dfp1 and the second decision feedback signal dfn1 may be sufficient to direct a majority of the bias current Ibf1 to one of the first resistor 650 and the second resistor 655 based on the previous bit decision and its complement without having to fully reach Vdd or Vss.

[0085] Figure 7 An exemplary implementation of a first switching circuit 660 and a second switching circuit 665 is shown in accordance with certain aspects. In this example, the first switching circuit 660 includes a first switch 710 coupled between the sources of a first transistor 622 and a second transistor 624 and a supply rail 690. In Figure 6 the example shown, the first switch 710 is implemented with a PFET, where the gate of the PFET is driven by a clock signal clk. However, it should be understood that the present disclosure is not limited to this example, and the first switch 710 may be implemented with an NFET, a transmission gate, or another type of switch. It should also be understood that the first switching circuit 660 is not limited to Figure 7 the first switch 710 shown. Generally speaking, according to various aspects, the first switching circuit 660 may be implemented with one or more switches arranged to perform the switching function of the first switching circuit 660 described herein.

[0086] In this example, the second switching circuit 665 includes a second switch 720 and a third switch 730, where the second switch 720 is coupled between a first node 632 and a low rail 695, and the third switch 730 is coupled between a second node 637 and the low rail 695. In Figure 7 the example shown, each of the second switch 720 and the third switch 730 is implemented with a corresponding NFET, where the gates of the corresponding NFETs are driven by a clock signal clk. However, it should be understood that the present disclosure is not limited to this example, and each of the second switch 720 and the third switch 730 may be implemented with a corresponding PFET, a transmission gate, or another type of switch. It should also be understood that the second switching circuit 665 is not limited to Figure 7The second switch 720 and the third switch 730 shown. Generally speaking, according to various aspects, the second switch circuit 665 can be implemented by one or more switches arranged to perform the switching function of the second switch circuit 665 described herein.

[0087] It should be understood that the input stage 610 may include Figure 6 and Figure 7 one or more additional components not shown in. For example, in some specific embodiments, the input stage 610 may include one or more additional reset switches (not shown) configured to reset the node between the first transistor 622 and the third transistor 630 to Vss (e.g., ground) during the reset phase, and to reset the node between the second transistor 624 and the fourth transistor 635 to Vss (e.g., ground) during the reset phase. In some specific implementations, the comparator 605 may include additional components (not shown) for offset cancellation. Therefore, it should be understood that the input stage 610 is not limited to Figure 6 and Figure 7 the components shown.

[0088] Figure 8 An exemplary specific implementation of the regeneration stage 680 according to certain aspects is shown. In this example, the regeneration stage 680 includes a first inverter 850, a second inverter 860, a first drive transistor 810, a second drive transistor 820, a first transistor 830, a second transistor 835, a third transistor 840, and a fourth transistor 845.

[0089] The first inverter 850 and the second inverter 860 are cross-coupled to form a latch, where the input terminal 852 of the first inverter 850 is coupled to the output terminal 864 of the second inverter 860, and the input terminal 862 of the second inverter 860 is coupled to the output terminal 854 of the first inverter 850. As further discussed below, the cross-coupling of the first inverter 850 and the second inverter 860 provides regeneration feedback to assist in resolving bits (i.e., making bit decisions). In Figure 8 the example, the first output terminal 686 is coupled to the output terminal 854 of the first inverter 850, and the second output terminal 688 is coupled to the output terminal 864 of the second inverter 860. However, it should be understood that the present disclosure is not limited to this example, and the first output terminal 686 and the second output terminal 688 may be coupled to other nodes in the regeneration stage 680.

[0090] The first inverter 850 also has a first voltage terminal 856 and a second voltage terminal 858. The first voltage terminal 856 is coupled to the supply rail 690 and the second voltage terminal 858 is coupled to the first node 870. The first inverter 850 is configured to pull the output terminal 854 to the voltage at the first voltage terminal 856 (e.g., the supply voltage Vdd) when the input terminal 852 is low and to pull the output terminal 854 to the voltage at the second voltage terminal 858 when the input terminal 852 is high.

[0091] The second inverter 860 also has a first voltage terminal 866 and a second voltage terminal 868. The first voltage terminal 866 is coupled to the supply rail 690 and the second voltage terminal 868 is coupled to the second node 875. The second inverter 860 is configured to pull the output terminal 864 to the voltage at the first voltage terminal 866 (e.g., the supply voltage Vdd) when the input terminal 862 is low and to pull the output terminal 864 to the voltage at the second voltage terminal 868 when the input terminal 862 is high.

[0092] The drain of the first drive transistor 810 is coupled to the first node 870, the gate of the first drive transistor 810 is coupled to the first input terminal 682, and the source of the first drive transistor 810 is coupled to the low rail 695 (e.g., ground). The drain of the second drive transistor 820 is coupled to the second node 875, the gate of the second drive transistor 820 is coupled to the second input terminal 684, and the source of the second drive transistor 820 is coupled to the low rail 695 (e.g., ground). In Figure 8 the example, each of the drive transistors 810 and 820 is implemented with a corresponding NFET.

[0093] The first transistor 830 is coupled between the supply rail 690 and the output terminal 854 of the first inverter 850, and the second transistor 835 is coupled between the supply rail 690 and the first node 870. The gate of each of the first transistor 830 and the second transistor 835 is coupled to the first input terminal 682. The third transistor 840 is coupled between the supply rail 690 and the output terminal 864 of the second inverter 860, and the fourth transistor 845 is coupled between the supply rail 690 and the second node 875. The gate of each of the third transistor 840 and the fourth transistor 845 is coupled to the second input terminal 684. In Figure 8 the example, each of the transistors 830, 835, 840, and 845 is implemented with a corresponding PFET.

[0094] Now, an exemplary operation of the regenerative stage 680 shown in the example of Figure 8 will be discussed according to certain aspects.

[0095] During the reset phase of the clock cycle, the first input terminal 682 and the second input terminal 684 are pulled down to the voltage Vss (e.g., ground) of the low rail 692. This is because the first node 632 and the second node 637 in the input stage 610 are reset to the voltage Vss of the low rail 692, as discussed above with reference to Figure 6 The pulling down of the first input terminal 682 and the second input terminal 684 causes the transistors 830, 835, 840, and 845 to turn on. The turning on of the transistors 830, 835, 840, and 845 causes the first transistor 830 to reset the output terminal 854 of the first inverter 850 to high (e.g., Vdd) and the input terminal 862 of the second inverter 860 to high (e.g., Vdd), the second transistor 835 to reset the first node 870 to high (e.g., Vdd), the third transistor 840 to reset the output terminal 864 of the second inverter 860 to high (e.g., Vdd) and the input terminal 852 of the first inverter 150 to high (e.g., Vdd), and the fourth transistor 845 to reset the second node 875 to high (e.g., Vdd). In addition, the first drive transistor 810 and the second drive transistor 820 are turned off.

[0096] During the sense phase of the clock cycle, the first drive transistor 810 is driven by a first voltage v1 from the input stage 610, and the second drive transistor 820 is driven by a second voltage v2 from the input stage 610. The first drive transistor 810 or the second drive transistor 820 turns on first during the sense phase, depending on which of the first voltage v1 and the second voltage v2 has a faster (i.e., higher) ramp rate.

[0097] When the first voltage v1 has a higher ramp rate than the second voltage v2, the first drive transistor 810 turns on before the second drive transistor 820. In this case, the first drive transistor 810 couples the second voltage terminal 858 of the first inverter 850 to Vss (e.g., ground), which enables the first inverter 850. This causes the first inverter 850 to turn on and pull down the output terminal 854 of the first inverter 850. The first inverter 850 pulls down the output terminal 854 because the input terminal 852 was reset to high (e.g., Vdd) during the reset phase. Since the output terminal 854 of the first inverter 850 is coupled to the input terminal 862 of the second inverter 860, the input terminal 862 of the second inverter 860 is also pulled down. When the second drive transistor 820 turns on, the second inverter 860 turns on and pulls up the output terminal 864 of the second inverter 860 because the input terminal 862 of the second inverter 860 was pulled down by the output terminal 854 of the first inverter 850. Thus, in this example, the first output terminal 686 is pulled down, indicating a bit decision of zero. Additionally, the second output terminal 688 is pulled up, indicating a bit decision of one (i.e., the complement of zero).

[0098] When the second voltage v2 has a ramp rate higher than that of the first voltage v1, the second drive transistor 820 turns on before the first drive transistor 810. In this case, the second drive transistor 820 couples the second voltage terminal 868 of the second inverter 860 to Vss (e.g., ground), which enables the second inverter 860. This causes the second inverter 860 to turn on and pull down the output terminal 864 of the second inverter 860. The second inverter 860 pulls down the output terminal 864 because the input terminal 862 is reset to high (e.g., Vdd) during the reset phase. Since the output terminal 864 of the second inverter 860 is coupled to the input terminal 852 of the first inverter 850, the input terminal 852 of the first inverter 850 is also pulled down. When the first drive transistor 810 turns on, the first inverter 850 turns on and pulls up the output terminal 854 of the first inverter 850 because the input terminal 852 of the first inverter 850 is pulled down by the output terminal 864 of the second inverter 860. Thus, in this example, the first output terminal 686 is pulled up, indicating a bit decision of one. Additionally, the second output terminal 688 is pulled down, indicating a bit decision of zero (i.e., the complement of one).

[0099] Figure 9 Exemplary embodiments of the first inverter 850 and the second inverter 860 are shown in accordance with certain aspects. In this example, each of the inverters 850 and 860 includes a complementary pair of transistors.

[0100] More specifically, the first inverter 850 includes a corresponding PFET 910 and a corresponding NFET 920. The source of the PFET 910 is coupled to the first voltage terminal 856, the drain of the PFET 910 is coupled to the output terminal 854, and the gate of the PFET 910 is coupled to the input terminal 852. The source of the NFET 920 is coupled to the second voltage terminal 858, the drain of the NFET 920 is coupled to the output terminal 854, and the gate of the NFET 920 is coupled to the input terminal 852.

[0101] The second inverter 860 includes a corresponding PFET 930 and a corresponding NFET 940. The source of the PFET 930 is coupled to the first voltage terminal 866, the drain of the PFET 930 is coupled to the output terminal 864, and the gate of the PFET 930 is coupled to the input terminal 862. The source of the NFET 940 is coupled to the second voltage terminal 868, the drain of the NFET 940 is coupled to the output terminal 864, and the gate of the NFET 940 is coupled to the input terminal 862.

[0102] Figure 6 and Figure 7An example of a 1-tap DFE is shown, where the first decision feedback signal dfp1 and the second decision feedback signal dfn1 correspond to the most recent previous bit decision and its complement. However, it should be understood that the comparator 605 can be extended to a multi-tap DFE to provide the DFE based on additional previous bit decisions (i.e., bit decisions corresponding to earlier clock cycles). This can be achieved by coupling additional feedback differential pairs to the third node 646 and the fourth node 648, where each of the additional feedback differential pairs provides feedback for a corresponding one of the additional previous bit decisions. The third transistor 630 and the fourth transistor 635 help isolate the signal path of the input stage 610 from the parasitic capacitances of the additional feedback differential pairs. Thus, the third transistor 630 and the fourth transistor 635 allow the addition of additional feedback differential pairs (i.e., additional taps for the DFE) with little impact on the capacitive load on the signal path.

[0103] Figure 10 An example is shown in which the comparator 605 includes a second current source 1025 and a second feedback differential pair 1010 to implement a multi-tap DFE. In this example, the second feedback differential pair 1010 is coupled to the third node 646 and the fourth node 648 to provide feedback for a second previous bit decision (i.e., a bit decision corresponding to two clock cycles before the current clock cycle).

[0104] In this example, the second feedback differential pair 1010 includes a seventh transistor 1015 and an eighth transistor 1020. The third decision feedback signal dfp2 can be input to the gate of the seventh transistor 1015, and the fourth decision feedback signal dfn2 can be input to the gate of the eighth transistor 1020. The third decision feedback signal dfp2 can correspond to the second previous bit decision, and the fourth decision feedback signal dfn2 can correspond to the complement (i.e., the inverse) of the second previous bit decision, or vice versa.

[0105] The drain of the seventh transistor 1015 is coupled to the third node 646, and the drain of the eighth transistor 1020 is coupled to the fourth node 648. The seventh transistor 1015 is configured to generate a fifth current based on the third decision feedback signal dfp2, and the eighth transistor 1020 is configured to generate a sixth current based on the fourth decision feedback signal dfn2. In Figure 10 the example shown, each of the seventh transistor 1015 and the eighth transistor 1020 is implemented with a corresponding PFET. However, it should be understood that the present disclosure is not limited to this example.

[0106] A second current source 1025 is coupled between a power supply rail 690 and the sources of a seventh transistor 1015 and an eighth transistor 1020. The second current source 1025 is configured to provide a second bias current Ibf2 to the seventh transistor 1015 and the eighth transistor 1020. In some aspects, the second current source 1025 may be implemented with a programmable current source, where the weight given to a second previous bit decision may be set to a desired weight by programming the second bias current Ibf2 accordingly.

[0107] In this example, a fifth current from the seventh transistor 1015 is added to a third current from the fifth transistor 642 at a third node 646. The sum of the fifth current and the third current flows through a first resistor 650 to generate a first gate voltage vg1 for a third transistor 630. Thus, the third transistor 630 adjusts a ramp rate of a first voltage v1 based on both a first feedback signal dfp1 and a third decision feedback signal dfp2.

[0108] A sixth current from the eighth transistor 1020 is added to a fourth current from the sixth transistor 644 at a fourth node 648. The sum of the sixth current and the fourth current flows through a second resistor 655 to generate a second gate voltage vg2 for a fourth transistor 635. Thus, the fourth transistor 635 adjusts a ramp rate of a second voltage v2 based on both a second decision feedback signal dfn1 and a fourth decision feedback signal dfn2. It should be understood that additional feedback differential pairs may be coupled to the third node 646 and the fourth node 648 to implement a 3 - tap DFE or a higher - tap DFE.

[0109] Figure 11 A system 1100 is shown that includes a comparator 605 and a latch 1120 coupled to the comparator 605. For ease of illustration, Figure 11 details of the comparator 605 are not explicitly shown.

[0110] The latch 1120 may include a set - reset (SR) latch or another type of latch. The latch 1120 has a first input terminal 1122, a second input terminal 1124, a first output terminal 1126, and a second output terminal 1128. In Figure 11 the example, the first input terminal 1122 is coupled to a first output terminal 686 of the comparator 605, and the second input terminal 1124 is coupled to a second output terminal 688 of the comparator 605. For an example where the latch 1120 includes an SR latch, the first input terminal 1122 may be a set input terminal and the second input terminal 1124 may be a reset input terminal, or vice versa. The first output terminal 1126 and the second output terminal 1128 may be coupled to a processor, a deserialiser, a memory, or another type of circuit.

[0111] In some aspects, the latch 1120 can be configured to latch a bit value (i.e., the resolved bit value) at the first output 686 and the complement of the bit value at the second output 688. The latch 1120 can also be configured to output the latched bit value at the first output 1126 and the complement of the latched bit value at the second output 1128, or vice versa. In one example, during the reset phase of a cycle of the clock signal clk, the latch 1120 (e.g., an SR latch) can be configured to output the latched bit value from the previous clock cycle and the complement of the latched bit value (i.e., the previous bit decision and the complement of the previous bit decision).

[0112] In Figure 11 the example shown, the first decision feedback signal dfp1 and the second decision feedback signal dfn1 for the DFE in the comparator 605 can be provided by the first output 1126 and the second output 1128 of the latch 1120. For example, the first output 1126 of the latch 1120 can be coupled to the gate of the fifth transistor 642 (shown in Figure 6 ), to provide the first decision feedback signal dfp1, and the second output 1128 of the latch 1120 can be coupled to the gate of the sixth transistor 644 (shown in Figure 6 ), to provide the second decision feedback signal dfn1, or vice versa. However, it should be understood that the present disclosure is not limited to Figure 11 the example shown. For example, in some embodiments, the first decision feedback signal dfp1 and the second decision feedback signal dfn1 can be provided by internal nodes in the latch 1120.

[0113] Figure 12 An example of a receiver 1200 having a half-rate architecture is shown in accordance with certain aspects. The receiver 1200 includes a first comparator 605A, a second comparator 605B, a first latch 1120A, and a second latch 1120B. Each of the first comparator 605A and the second comparator 605B can be a separate instance of the comparator 605 and can be implemented, for example, with any of the exemplary embodiments discussed herein. In Figure 12 the example, the reference numerals of the elements of the first comparator 605A are appended with "A", and the reference numerals of the elements of the second comparator 605B are appended with "B".

[0114] The first input terminal 612A of the first comparator 605A and the first input terminal 612B of the second comparator 605B are coupled to the first input terminal 1212 of the receiver 1200. The first input terminal 1212 is configured to receive the first input signal inp of the differential input signal. The second input terminal 614A of the first comparator 605A and the second input terminal 614B of the second comparator 605B are coupled to the second input terminal 1214 of the receiver 1200. The second input terminal 1214 is configured to receive the second input signal inn of the differential input signal.

[0115] In this example, the first comparator 605A receives the clock signal clk, and the second comparator 605B receives the complementary clock signal clkb (i.e., the complement of the clock signal clk). Thus, the clock signal clk times the switches 710A, 720A, and 730A in the first comparator 605A ( Figure 12 not shown), and the complementary clock signal clkb times the switches 710B, 720B, and 730B in the second comparator 605B ( Figure 12 not shown). This causes the first comparator 605A and the second comparator 605B to alternately resolve bit values based on the differential input signal. In other words, the first comparator 605A and the second comparator 605B resolve bit values in a time-interleaved manner. For example, the first comparator 605A may resolve even bit values, and the second comparator 605B may resolve odd bit values, or vice versa. Thus, the last bit value resolved by the second comparator 605B may correspond to the previous bit decision relative to the first comparator 605A, and the last bit value resolved by the first comparator 605A may correspond to the previous bit decision relative to the second comparator 605B.

[0116] In Figure 12 the example, the first latch 1120A (e.g., the first SR latch) has a first input terminal 1122A coupled to the first output terminal 686A of the first comparator 605A, a second input terminal 1124A coupled to the second output terminal 688A of the first comparator 605A, a first output terminal 1126A, and a second output terminal 1128A. The first output terminal 1126A and the second output terminal 1128A may be coupled to a processor, a deserialiser, a memory, or another type of circuit. The first latch 1120A may be configured to latch the bit value at the first output terminal 686A of the first comparator 605A and the complement of the bit value at the second output terminal 688A of the first comparator 605A. The first latch 1120A may also be configured to output the latched bit value at the first output terminal 1126A and the complement of the latched bit value at the second output terminal 1128A, or vice versa.

[0117] The second latch 1120B (e.g., a second SR latch) has a first input terminal 1122B coupled to the first output terminal 686B of the second comparator 605B, a second input terminal 1124B coupled to the second output terminal 688B of the second comparator 605B, a first output terminal 1126B, and a second output terminal 1128B. The first output terminal 1126B and the second output terminal 1128B can be coupled to a processor, a deserialiser, a memory, or another type of circuit. The second latch 1120B can be configured to latch the bit value at the first output terminal 686B of the first comparator 605B and the complement of the bit value at the second output terminal 688B of the first comparator 605B. The second latch 1120B can also be configured to output the latched bit value at the first output terminal 1126B and the complement of the latched bit value at the second output terminal 1128B, or vice versa.

[0118] In Figure 12 the example shown, the first decision feedback signal dfp1A and the second decision feedback signal dfn1A for decision feedback equalization in the first comparator 605A are provided by the first output terminal 686B and the second output terminal 688B of the second comparator 605B. It should be understood that in other specific implementations, the first decision feedback signal dfp1A and the second decision feedback signal dfn1A can be provided by the first internal node and the second internal node of the second comparator 605B or the second latch 1120B, respectively.

[0119] In Figure 12 the example shown, the first decision feedback signal dfp1B and the second decision feedback signal dfn1B for decision feedback equalization in the second comparator 605B are provided by the first output terminal 686A and the second output terminal 688A of the first comparator 605A. It should be understood that in other specific implementations, the first decision feedback signal dfp1B and the second decision feedback signal dfn1B can be provided by the first internal node and the second internal node of the first comparator 605A or the first latch 1120A, respectively.

[0120] For an example of a 2 - tap DFE, each of the first comparator 605A and the second comparator 605B may receive a respective third feedback signal dfp2 and a fourth feedback signal dfn1 from respective latches 1120A and 1120B. Thus, in this example, for the first comparator 605A, the first feedback signal dfp1 and the second feedback signal dfn1 may be based on the previous bit decision of the second comparator 605B, and the third feedback signal dfp2 and the fourth feedback signal defn2 may be based on the previous bit decision of the first comparator 605A. Similarly, for the second comparator 605B, the first feedback signal dfp1 and the second feedback signal dfn1 may be based on the previous bit decision of the first comparator 605A, and the third feedback signal dfp2 and the fourth feedback signal defn2 may be based on the previous bit decision of the second comparator 605B.

[0121] Figure 13A An example of a system 1305 including a comparator 605 and a latch 1120 in accordance with certain aspects of the present disclosure is shown. In this example, the system 1305 also includes a transmitter 112 and a link 130 (e.g., a differential serial link) discussed above with reference to Figure 1 As Figure 13A shown, a first input terminal 612 and a second input terminal 614 of the comparator 605 are coupled to a first output terminal 1322 and a second output terminal 1324 of the transmitter 112 via respective transmission lines 1312 and 1314 of the link 130. In certain aspects, the transmitter 112 may transmit a first signal inp from the first output terminal 1322 and a second signal inn from the second output terminal 1324.

[0122] The comparator 605 may receive a first decision feedback signal dfp1 and a second decision feedback signal dfn1 from a latch 1120 (shown in Figure 11 ). In another example, the comparator 605 may receive the first decision feedback signal dfp1 and the second decision feedback signal dfn1 from another comparator time - interleaved with the comparator 605. In this example, the comparator 605 may correspond to the first comparator 605A, and the other comparator may correspond to the Figure 12 second comparator 605B shown in

[0123] The system 1305 also includes a deserialiser 1310 (e.g., to support SerDes communication) coupled to the latch 1120. The deserialiser 1310 may be coupled to a first output terminal 1126 and / or a second output terminal 1128 of the latch 1120. In this example, the deserialiser 1310 may be configured to receive a serial bit stream from the latch 1120 and convert the serial bit stream into a plurality of parallel bit streams. The parallel bit streams may be transmitted to a processor (not shown) for further processing.

[0124] Figure 13B An example of a system 1330 including a comparator 605 and a latch 1120 in accordance with certain aspects of the present disclosure is shown. In this example, system 1305 also includes the transmitter 112 and the link 130 (e.g., a differential serial link) discussed above with reference to Figure 1 The transmitter 112 and the link 130 (e.g., a differential serial link) discussed above with reference to Figure 13B As shown, a first input terminal 612 and a second input terminal 614 of the comparator 605 are coupled to a first output terminal 1322 and a second output terminal 1234 of the transmitter 112 via respective transmission lines 1312 and 1314 of the link 130. The comparator 605 can receive a first decision feedback signal dfp1 and a second decision feedback signal dfn1 from the latch 1120 (shown in Figure 11 ), or from another comparator time-interleaved with the comparator 605, as discussed above with reference to Figure 13A The transmitter 112 and the link 130 (e.g., a differential serial link) discussed above with reference to

[0125] System 1330 also includes a memory 1335 (e.g., a double data rate (DDR) dynamic random access memory (DRAM), a low power DDR (LPDDR) DRAM, etc.) coupled to the latch 1120. The memory 1335 can be coupled to the first output terminal 1126 and / or the second output terminal 1128 of the latch 1120. In this example, the memory 1335 can receive data bits, address bits, and / or control bits from the latch 1120. For an example in which the memory 1335 receives data bits from the latch 1120, the memory 1335 can store the received data bits.

[0126] As discussed above, the comparator 605 can also be used for pseudo-differential signals. In this regard, Figure 14 An example in which the comparator 605 is used for pseudo-differential signals is shown. The pseudo-differential signal includes an input signal and a reference signal. The input signal can be from a transmitter (e.g., transmitter 112) via a link (e.g., link 130). In this example, the input signal (e.g., input voltage) is input to the first input terminal 612 of the comparator 605, and the reference signal (e.g., reference voltage) is input to the second input terminal 614 of the comparator 605.

[0127] In this example, the comparator 605 can include a digital-to-analog converter (DAC) 1410 configured to generate a reference signal (e.g., reference voltage) based on a digital code and output the reference signal at an output terminal 1415 coupled to the second input terminal 614 of the comparator 605. In this example, the reference signal can be set to a desired level (e.g., voltage level) by setting the digital code accordingly.

[0128] In this example, comparator 605 makes a bit decision based on whether the input signal is greater than or less than a reference signal. For example, comparator 605 may resolve a bit value of one when the input signal is greater than the reference signal and may resolve a bit value of zero when the input signal is less than the reference signal. However, it should be understood that the present disclosure is not limited to this example.

[0129] Figure 15 An example is shown in which each of a first transistor 622, a second transistor 624, a third transistor 630, a fourth transistor 635, a fifth transistor 642, and a sixth transistor 644 is implemented with a corresponding NFET. In this example, a first switch circuit 660 is coupled between the sources of the first transistor 622 and the second transistor 624 and the low rail 695, and a second switch circuit 665 is coupled between a first node 632 and a second node 637 and the supply rail 690. In Figure 15 the example shown, the first switch circuit 660 includes a first switch 710 implemented with an NFET, and the second switch circuit 665 includes a second switch 720 and a third switch 730 implemented with corresponding PFETs. However, it should be understood that the present disclosure is not limited to this example.

[0130] In this example, the input stage 610 operates in a reset phase when the clock signal clk is low and operates in a sense phase when the clock signal is high. During the reset phase, the first switch circuit 660 decouples the sources of the first transistor 622 and the second transistor 624 from the low rail 695, and the second switch circuit 665 couples the first node 632 and the second node 637 to the supply rail 690. Accordingly, the capacitance of the first node 632 is charged to the supply rail 690, causing the first voltage v1 to rise to approximately Vdd. Additionally, the capacitance of the second node 637 is charged to the supply rail 690, causing the second voltage v2 to rise to approximately Vdd. Thus, in this example, the first voltage v1 and the second voltage v2 are reset to approximately Vdd.

[0131] During the sensing phase, the first transistor 622 discharges the capacitance on the first node 632 based on the first input signal inp, causing the first voltage v1 to decrease (i.e., ramp down), and the second transistor 624 discharges the capacitance on the second node 637 based on the second input signal inn, causing the second voltage v2 to decrease (i.e., ramp down). Alternatively, for a pseudo-differential signal, the first transistor 622 discharges the capacitance on the first node 632 based on the input signal, and the second transistor 624 discharges the capacitance on the second node 637 based on the reference signal. The first voltage v1 and the second voltage v2 ramp down at different rates according to the input signals inp and inn. For example, when the first input signal inp is higher than the second input signal inn, the first current is higher than the second current. When the second input signal inn is higher than the first input signal inp, the second current is higher than the first current. In both cases, the first current and the second current are different according to the input signals inp and inn, causing the first voltage v1 and the second voltage v2 to ramp down at different rates and separate during the sensing phase. In this example, the regeneration stage 680 may be configured to make a bit decision one when the first voltage v1 ramps down faster than the second voltage v2, and make a bit decision zero when the second voltage v2 ramps down faster than the first voltage v1, or vice versa.

[0132] The third transistor 630, the fourth transistor 635, and the feedback differential pair 640 add DFE by adjusting the ramp rates of the first voltage v1 and the second voltage v2 based on the feedback signals dfp1 and dfn1, as discussed above. In this example, the current source 626 is coupled between the sources of the fifth transistor 642 and the sixth transistor 644 and the low rail 695, the first resistor 650 is coupled between the gate of the third transistor 630 and the supply rail 690, and the second resistor 655 is coupled between the gate of the fourth transistor 635 and the supply rail 690.

[0133] In some aspects, the reset phase of a cycle of the clock signal clk corresponds to the first part of a cycle of the clock signal clk, and the sensing phase of a cycle of the clock signal clk corresponds to the second part of a cycle of the clock signal clk. In Figure 7 the exemplary embodiment shown, the clock signal clk may be high during the first part of a cycle of the clock signal and low during the second part of a cycle of the clock signal. In Figure 15 the exemplary embodiment shown, the clock signal clk may be low during the first part of a cycle of the clock signal and high during the second part of a cycle of the clock signal. However, it should be understood that the present disclosure is not limited to these examples.

[0134] Figure 16Illustrates a method 1600 for operating a comparator. The comparator (e.g., comparator 605) includes a first transistor (e.g., first transistor 622), a second transistor (e.g., second transistor 624), a third transistor (e.g., third transistor 630), and a fourth transistor (e.g., fourth transistor 635), where the third transistor is coupled in series with the first transistor and coupled between the first transistor and a first node (e.g., first node 632), and the fourth transistor is coupled in series with the second transistor and coupled between the second transistor and a second node (e.g., second node 637).

[0135] At block 1610, the gate of the first transistor is driven with a first signal. For example, the first signal may correspond to the first signal inp of a differential input signal or the input signal of a pseudo-differential signal.

[0136] At block 1620, the gate of the second transistor is driven with a second signal. The second signal may correspond to a second input signal inn or a reference signal.

[0137] At block 1630, a first voltage at the gate of the third transistor is adjusted based on a first decision feedback signal. For example, the first voltage may correspond to a first gate voltage vg1. In some aspects, the first voltage at the gate of the third transistor may be adjusted by a fifth transistor 642 and a first resistor 650.

[0138] At block 1640, a second voltage at the gate of the fourth transistor is adjusted based on a second decision feedback signal. For example, the second voltage may correspond to a second gate voltage vg2. In some aspects, the second voltage at the gate of the fourth transistor may be adjusted by a sixth transistor 644 and a second resistor 655.

[0139] At block 1650, a bit decision is made based on a third voltage on the first node and a fourth voltage on the second node. For example, the third voltage may correspond to a first voltage v1, and the fourth voltage may correspond to a second voltage v2. In some aspects, the bit decision may be made by a regeneration stage 680.

[0140] In some aspects, the first decision feedback signal corresponds to a previous bit decision of the comparator, and the second decision feedback signal corresponds to the complement of the previous bit decision.

[0141] In some aspects, the first decision feedback signal corresponds to a previous bit decision of another comparator time-interleaved with the comparator, and the second decision feedback signal corresponds to the complement of the previous bit decision. For example, in Figure 12 the example shown, the comparator may correspond to comparator 605A, and the other comparator may correspond to comparator 605B.

[0142] In some aspects, the comparator includes a first resistor coupled between the gate of a third transistor and a rail. The rail can correspond to the supply rail 690 or the low rail 695. In these aspects, adjusting the first voltage at the gate of the third transistor based on the first decision feedback signal can include driving the gate of a fifth transistor with the first decision feedback signal to generate a first current, and routing the first current through the first resistor. The first current can correspond to the third current discussed above.

[0143] In some aspects, the comparator includes a second resistor coupled between the gate of a fourth transistor and a rail. The rail can correspond to the supply rail 690 or the low rail 695. In these aspects, adjusting the second voltage at the gate of the fourth transistor based on the second decision feedback signal can include driving the gate of a sixth transistor with the second decision feedback signal to generate a second current, and routing the second current through the second resistor. The second current can correspond to the fourth current discussed above.

[0144] In some aspects, making a bit decision based on a third voltage at a first node and a fourth voltage at a second node can include making the bit decision based on the ramp rate of the third voltage at the first node and the ramp rate of the fourth voltage at the second node. In one example, the third voltage and the fourth voltage ramp up at different rates (e.g., from approximately Vss). In another example, the third voltage and the fourth voltage ramp down at different rates (e.g., from approximately Vdd).

[0145] Specific implementation examples are described in the following numbered clauses:

[0146] 1. A comparator, the comparator comprising:

[0147] An input stage, the input stage comprising:

[0148] A first transistor, wherein the gate of the first transistor is coupled to a first input of the input stage;

[0149] A second transistor, wherein the gate of the second transistor is coupled to a second input of the input stage;

[0150] A third transistor coupled in series with the first transistor;

[0151] A fourth transistor coupled in series with the second transistor;

[0152] A fifth transistor, wherein the gate of the fifth transistor is configured to receive a first decision feedback signal, and the drain of the fifth transistor is coupled to the gate of the third transistor; and

[0153] A sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.

[0154] 2. The comparator according to clause 1, wherein:

[0155] The first decision feedback signal corresponds to a previous bit decision of the comparator; and

[0156] The second decision feedback signal corresponds to a complement of the previous bit decision.

[0157] 3. The comparator according to clause 1, wherein:

[0158] The first decision feedback signal corresponds to a previous bit decision of another comparator time-interleaved with the comparator; and

[0159] The second decision feedback signal corresponds to a complement of the previous bit decision.

[0160] 4. The comparator according to any one of clauses 1 to 3, wherein the input stage further comprises:

[0161] A first resistor coupled between the gate of the third transistor and a first rail; and

[0162] A second resistor coupled between the gate of the fourth transistor and the first rail.

[0163] 5. The comparator according to clause 4, wherein the input stage further comprises a current source, wherein the current source is coupled between a source of the fifth transistor and a second rail, and the current source is coupled between a source of the sixth transistor and the second rail.

[0164] 6. The comparator according to clause 5, wherein the second rail comprises a power supply rail, and the first rail has a potential lower than that of the power supply rail.

[0165] 7. The comparator according to clause 5, wherein the first rail comprises a power supply rail, and the second rail has a potential lower than that of the power supply rail.

[0166] 8. The comparator according to any one of clauses 1 to 7, wherein the input stage further comprises a first switch circuit, wherein the first switch circuit is configured to:

[0167] Receive a clock signal;

[0168] Decouple a source of the first transistor and a source of the second transistor from the first rail during a first part of a cycle of the clock signal; and

[0169] During a second part of the cycle of the clock signal, couple the source of the first transistor and the source of the second transistor to the first rail.

[0170] 9. The comparator according to clause 8, wherein the third transistor is coupled between the first transistor and a first node, the fourth transistor is coupled between the second transistor and a second node, and the input stage further includes a second switch circuit, wherein the second switch circuit is configured to:

[0171] Receive the clock signal;

[0172] During a first part of the cycle of the clock signal, couple the first node and the second node to a second rail; and

[0173] During a second part of the cycle of the clock signal, decouple the first node and the second node from the second rail.

[0174] 10. The comparator according to clause 9, wherein the first rail includes a supply rail, and the second rail has a potential lower than that of the supply rail.

[0175] 11. The comparator according to clause 9, wherein the second rail includes a supply rail, and the first rail has a potential lower than that of the supply rail.

[0176] 12. The comparator according to any one of clauses 9 to 11, wherein the second switch circuit includes:

[0177] A first switch coupled between the first node and the second rail; and

[0178] A second switch coupled between the second node and the second rail.

[0179] 13. The comparator according to any one of clauses 9 to 12, further including a regeneration stage, wherein the regeneration stage includes:

[0180] A first inverter;

[0181] A second inverter cross-coupled with the first inverter;

[0182] A first driving transistor coupled to the first inverter, wherein the gate of the first driving transistor is coupled to the first node; and

[0183] A second driving transistor coupled to the second inverter, wherein the gate of the second driving transistor is coupled to the second node.

[0184] 14. The comparator according to any one of clauses 1 to 13, wherein the comparator is configured to receive a differential input signal including a first input signal and a second input signal, the first input signal is input to the first input terminal of the input stage, and the second input signal is input to the second input terminal of the input stage.

[0185] 15. The comparator according to any one of clauses 1 to 13, wherein the first input terminal of the input stage is configured to receive an input signal, and the comparator further includes:

[0186] A digital-to-analog converter (DAC), wherein the DAC has an output terminal coupled to the second input terminal of the comparator, and the DAC is configured to generate a reference signal and output the reference signal at the output terminal of the DAC.

[0187] 16. The comparator according to any one of clauses 1 to 15, wherein the input stage further includes:

[0188] A seventh transistor, wherein the gate of the seventh transistor is configured to receive a third decision feedback signal, and the drain of the seventh transistor is coupled to the gate of the third transistor; and

[0189] An eighth transistor, wherein the gate of the eighth transistor is configured to receive a fourth decision feedback signal, and the drain of the eighth transistor is coupled to the gate of the fourth transistor.

[0190] 17. The comparator according to clause 16, wherein:

[0191] The first decision feedback signal corresponds to the first previous bit decision of the comparator;

[0192] The second decision feedback signal corresponds to the complement of the first previous bit decision;

[0193] The third decision feedback signal corresponds to the second previous bit decision of the comparator; and

[0194] The fourth decision feedback signal corresponds to the complement of the second previous bit decision.

[0195] 18. The comparator according to clause 16, wherein:

[0196] The first decision feedback signal corresponds to the previous bit decision of another comparator time-interleaved with the comparator;

[0197] The second decision feedback signal corresponds to the complement of the previous bit decision of the other comparator;

[0198] The third decision feedback signal corresponds to the previous bit decision of the comparator; and

[0199] The fourth decision feedback signal corresponds to the complement of the previous bit decision of the comparator.

[0200] 19. The comparator according to any one of clauses 1 to 18, wherein the third transistor is coupled between the first transistor and the first node, the fourth transistor is coupled between the second transistor and the second node, and the comparator further comprises:

[0201] A regenerative stage having a first input, a second input, a first output, and a second output, wherein the first input of the regenerative stage is coupled to the first node, and the second input of the regenerative stage is coupled to the second node.

[0202] 20. The comparator according to clause 19, wherein the regenerative stage is configured to:

[0203] Determine a bit value based on a first voltage on the first node and a second voltage on the second node;

[0204] Output the bit value at the first output of the regenerative stage; and

[0205] Output the complement of the bit value at the second output of the regenerative stage.

[0206] 21. The comparator according to clause 20, wherein the regenerative stage is configured to determine the bit value based on a ramp rate of the first voltage and a ramp rate of the second voltage.

[0207] 22. The comparator according to any one of clauses 19 to 21, wherein the input stage further comprises a switching circuit, wherein the switching circuit is configured to:

[0208] Receive a clock signal;

[0209] Couple the first node and the second node to the rails during a first part of the cycle of the clock signal; and

[0210] Decouple the first node and the second node from the rails during a second part of the cycle of the clock signal.

[0211] 23. A method of operating a comparator, the comparator including a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the third transistor is serially coupled with the first transistor and coupled between the first transistor and a first node, and the fourth transistor is serially coupled with the second transistor and coupled between the second transistor and a second node, the method including:

[0212] Driving a gate of the first transistor with a first signal;

[0213] Driving a gate of the second transistor with a second signal;

[0214] Adjusting a first voltage at the gate of the third transistor based on a first decision feedback signal;

[0215] Adjusting a second voltage at the gate of the fourth transistor based on a second decision feedback signal; and

[0216] Making a bit decision based on a third voltage on the first node and a fourth voltage on the second node.

[0217] 24. The method according to clause 23, wherein:

[0218] The first decision feedback signal corresponds to a previous bit decision of the comparator; and

[0219] The second decision feedback signal corresponds to a complement of the previous bit decision.

[0220] 25. The method according to clause 23, wherein:

[0221] The first decision feedback signal corresponds to a previous bit decision of another comparator time-interleaved with the comparator; and

[0222] The second decision feedback signal corresponds to a complement of the previous bit decision.

[0223] 26. The method according to any one of clauses 23 to 25, wherein the comparator includes a first resistor coupled between the gate of the third transistor and a rail, and wherein adjusting the first voltage at the gate of the third transistor based on the first decision feedback signal includes:

[0224] Driving a gate of a fifth transistor with the first decision feedback signal to generate a first current; and

[0225] Routing the first current through the first resistor.

[0226] 27. The method according to clause 26, wherein the comparator includes a second resistor coupled between the gate of the fourth transistor and the rail, and wherein adjusting the second voltage at the gate of the fourth transistor based on the second decision feedback signal includes:

[0227] driving the gate of a sixth transistor with the second decision feedback signal to generate a second current; and

[0228] routing the second current through the second resistor.

[0229] 28. The method according to any one of clauses 23 to 27, wherein the first signal includes a first input signal of a differential input signal, and the second signal includes a second input signal of the differential input signal.

[0230] 29. The method according to any one of clauses 23 to 27, wherein the first signal includes an input signal, and the second signal includes a reference signal.

[0231] 30. The method according to any one of clauses 23 to 29, wherein making the bit decision based on the third voltage at the first node and the fourth voltage at the second node includes:

[0232] making the bit decision based on the ramp rate of the third voltage at the first node and the ramp rate of the fourth voltage at the second node.

[0233] Any reference to elements using designations such as "first", "second", etc. herein generally does not limit the number or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, the reference to a first element and a second element does not mean that only two elements can be employed, or that the first element must be located before the second element.

[0234] As used herein, a first inverter and a second inverter are "cross-coupled" when the input terminal of the first inverter is coupled to the output terminal of the second inverter and the output terminal of the second inverter is coupled to the input terminal of the first inverter. As used herein, when two comparators alternate between making bit decisions, the two comparators are "time-interleaved". As used herein, a "previous bit decision" is a bit decision previously made by a comparator.

[0235] It should be understood that an n-type field effect transistor may also be referred to as an n-channel field effect transistor, and a p-type field effect transistor may also be referred to as a p-channel field effect transistor.

[0236] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration". Any particular implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of the disclosure. Similarly, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. As used herein, the term "about" with respect to a specified value or property is intended to indicate within 10% of the specified value or property.

[0237] The foregoing description of the disclosure has been provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A comparator, the comparator comprising: An input stage, the input stage comprising: A first transistor, wherein a gate of the first transistor is coupled to a first input terminal of the input stage; A second transistor, wherein a gate of the second transistor is coupled to a second input terminal of the input stage; A third transistor coupled in series with the first transistor; A fourth transistor coupled in series with the second transistor; A fifth transistor, wherein a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor; and A sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.

2. The comparator according to claim 1, wherein: The first decision feedback signal corresponds to a previous bit decision of the comparator; and The second decision feedback signal corresponds to a complement of the previous bit decision.

3. The comparator according to claim 1, wherein: The first decision feedback signal corresponds to a previous bit decision of another comparator time-interleaved with the comparator; and The second decision feedback signal corresponds to a complement of the previous bit decision.

4. The comparator according to claim 1, wherein the input stage further comprises: A first resistor coupled between the gate of the third transistor and a first rail; And A second resistor coupled between the gate of the fourth transistor and the first rail.

5. The comparator according to claim 4, wherein the input stage further comprises a current source, wherein the current source is coupled between a source of the fifth transistor and a second rail, and the current source is coupled between a source of the sixth transistor and the second rail.

6. The comparator according to claim 5, wherein the second rail comprises a power supply rail, and the first rail has a potential lower than the power supply rail.

7. The comparator according to claim 5, wherein the first rail comprises a power supply rail, and the second rail has a potential lower than the power supply rail.

8. The comparator according to claim 1, wherein the input stage further comprises a first switch circuit, wherein the first switch circuit is configured to: Receive a clock signal; Decouple a source of the first transistor and a source of the second transistor from the first rail during a first portion of a cycle of the clock signal; and Couple the source of the first transistor and the source of the second transistor to the first rail during a second portion of the cycle of the clock signal.

9. The comparator according to claim 8, wherein the third transistor is coupled between the first transistor and a first node, the fourth transistor is coupled between the second transistor and a second node, and the input stage further comprises a second switch circuit, wherein the second switch circuit is configured to: Receive the clock signal; Couple the first node and the second node to a second rail during the first portion of the cycle of the clock signal; And During the second part of the cycle of the clock signal, decouple the first node and the second node from the second rail.

10. The comparator according to claim 9, wherein the first rail includes a power supply rail, and the second rail has a potential lower than that of the power supply rail.

11. The comparator according to claim 9, wherein the second rail includes a power supply rail, and the first rail has a potential lower than that of the power supply rail.

12. The comparator according to claim 9, wherein the second switching circuit includes: A first switch coupled between the first node and the second rail; and A second switch coupled between the second node and the second rail.

13. The comparator according to claim 9, further comprising a regenerative stage, wherein the regenerative stage includes: A first inverter; A second inverter cross-coupled with the first inverter; A first driving transistor coupled to the first inverter, wherein the gate of the first driving transistor is coupled to the first node; and A second driving transistor coupled to the second inverter, wherein the gate of the second driving transistor is coupled to the second node.

14. The comparator according to claim 1, wherein the comparator is configured to receive a differential input signal including a first input signal and a second input signal, the first input signal is input to the first input terminal of the input stage, and the second input signal is input to the second input terminal of the input stage.

15. The comparator according to claim 1, wherein the first input terminal of the input stage is configured to receive an input signal, and the comparator further includes: A digital-to-analog converter (DAC), wherein the DAC has an output terminal coupled to the second input terminal of the comparator, and the DAC is configured to generate a reference signal and output the reference signal at the output terminal of the DAC.

16. The input stage according to claim 1, further comprising: A seventh transistor, wherein the gate of the seventh transistor is configured to receive a third decision feedback signal, and the drain of the seventh transistor is coupled to the gate of the third transistor; and An eighth transistor, wherein the gate of the eighth transistor is configured to receive a fourth decision feedback signal, and the drain of the eighth transistor is coupled to the gate of the fourth transistor.

17. The comparator according to claim 16, wherein: The first decision feedback signal corresponds to the first previous bit decision of the comparator; The second decision feedback signal corresponds to the complement of the first previous bit decision; The third decision feedback signal corresponds to the second previous bit decision of the comparator; and The fourth decision feedback signal corresponds to the complement of the second previous bit decision.

18. The comparator according to claim 16, wherein: The first decision feedback signal corresponds to the previous bit decision of another comparator time-interleaved with the comparator; The second decision feedback signal corresponds to the complement of the previous bit decision of the other comparator; The third decision feedback signal corresponds to the previous bit decision of the comparator; and The fourth decision feedback signal corresponds to the complement of the previous bit decision of the comparator.

19. The comparator according to claim 1, wherein the third transistor is coupled between the first transistor and the first node, the fourth transistor is coupled between the second transistor and the second node, and the comparator further comprises: A regeneration stage having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal of the regeneration stage is coupled to the first node, and the second input terminal of the regeneration stage is coupled to the second node.

20. The comparator according to claim 19, wherein the regeneration stage is configured to: Determine a bit value based on a first voltage on the first node and a second voltage on the second node; Output the bit value at the first output terminal of the regeneration stage; And Output the complement of the bit value at the second output terminal of the regeneration stage.

21. The comparator according to claim 20, wherein the regeneration stage is configured to determine the bit value based on the ramp rate of the first voltage and the ramp rate of the second voltage.

22. The comparator according to claim 19, wherein the input stage further comprises a switching circuit, wherein the switching circuit is configured to: Receive a clock signal; Couple the first node and the second node to the rails during a first portion of the cycle of the clock signal; and Decouple the first node and the second node from the rails during a second portion of the cycle of the clock signal.

23. A method of operating a comparator, the comparator comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the third transistor is coupled in series with the first transistor and coupled between the first transistor and a first node, and the fourth transistor is coupled in series with the second transistor and coupled between the second transistor and a second node, the method comprising: Driving the gate of the first transistor with a first signal; Driving the gate of the second transistor with a second signal; Adjusting a first voltage at the gate of the third transistor based on a first decision feedback signal; Adjusting a second voltage at the gate of the fourth transistor based on a second decision feedback signal; And Making a bit decision based on a third voltage on the first node and a fourth voltage on the second node.

24. The method according to claim 23, wherein: The first decision feedback signal corresponds to the previous bit decision of the comparator; and The second decision feedback signal corresponds to the complement of the previous bit decision.

25. The method according to claim 23, wherein: The first decision feedback signal corresponds to the previous bit decision of another comparator time-interleaved with the comparator; and The second decision feedback signal corresponds to the complement of the previous bit decision.

26. The method according to claim 23, wherein the comparator includes a first resistor coupled between the gate of the third transistor and the rail, and wherein adjusting the first voltage at the gate of the third transistor based on the first decision feedback signal includes: driving the gate of a fifth transistor with the first decision feedback signal to generate a first current; and routing the first current through the first resistor.

27. The method according to claim 26, wherein the comparator includes a second resistor coupled between the gate of the fourth transistor and the rail, and wherein adjusting the second voltage at the gate of the fourth transistor based on the second decision feedback signal includes: driving the gate of a sixth transistor with the second decision feedback signal to generate a second current; and routing the second current through the second resistor.

28. The method according to claim 23, wherein the first signal includes a first input signal of a differential input signal, and the second signal includes a second input signal of the differential input signal.

29. The method according to claim 23, wherein the first signal includes an input signal, and the second signal includes a reference signal.

30. The method according to claim 23, wherein making the bit decision based on the third voltage at the first node and the fourth voltage at the second node includes: making the bit decision based on a ramp rate of the third voltage at the first node and a ramp rate of the fourth voltage at the second node.

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