A navigation array anti-interference adaptive RLS calculation method and system

Abstract

The present invention belongs to the field of Beidou navigation anti-interference technology, and particularly relates to a navigation array anti-interference adaptive RLS operation method and system. The method is implemented based on an operation system and includes the steps of signal reception and down-conversion processing, analog-to-digital conversion and data matrix construction, data stream structured processing, data control and RLS operation, direction vector assignment and update, and navigation signal generation. The present invention generates a valve control signal by determining an idle flag s and a system temperature t. Different operations are performed on the covariance matrix and direction vector based on whether the value of g is 1 (valid). When the RLS operation unit is not in an idle state or the system operating temperature is higher than a set value, g is used to control the covariance matrix and direction vector to perform simplified operations. This can reduce the system's computational load and power consumption, reduce system heating caused by high computation, and thus return the system to a desired temperature.

Description

Technical Field

[0001] The present invention belongs to the field of Beidou navigation anti-interference technology, and in particular relates to a navigation array anti-interference adaptive RLS operation method and system. Background Art

[0002] In satellite navigation array anti-interference receivers, adaptive filtering techniques (such as the recursive least squares algorithm (RLS)) are widely used to suppress multipath and narrowband interference due to their high convergence speed and anti-interference performance. However, as navigation systems demand greater real-time performance and accuracy, the sampling rate of the receiver's front-end analog-to-digital converter (ADC) typically needs to exceed 125Msps to capture wideband signals, resulting in an exponential increase in the amount of data input to the RLS algorithm.

[0003] The computational complexity of the traditional RLS algorithm is O(m 2 )(m is the number of array elements, O(m 2 ) indicates that the algorithm's computational complexity is proportional to the square of the input parameter m. That is, as m increases, the amount of computation increases quadratically. In high-speed sampling scenarios, the processor needs to frequently perform matrix inversion and iterative update operations, consuming significant computing resources. This not only degrades real-time performance but also leads to increased chip power consumption and uncontrolled system temperature rise, severely restricting device reliability.

[0004] To reduce the amount of RLS computation, existing technologies generally adopt two solutions: one is to reduce the dimension of the input data, such as through fixed-interval sampling or random discarding of some data, but such methods will lose signal integrity and lead to reduced navigation accuracy; the other is to optimize the RLS algorithm structure, such as block processing or approximate matrix updates, but it still relies on fixed-length data cache, which is difficult to adapt to the streaming data processing requirements under high sampling rates. In addition, the existing technology lacks a coordinated control mechanism for computing load and system temperature rise, and cannot dynamically adjust data throughput in high-temperature environments, which can easily cause hardware performance degradation or even failure. Summary of the Invention

[0005] (1) Technical issues to be resolved

[0006] To address the problems of high computational complexity, processor power consumption surge, uncontrolled system temperature rise, and difficulty balancing real-time streaming data processing and signal integrity caused by high sampling rates (>125Msps) in the RLS algorithm of satellite navigation array receivers, the present invention provides an anti-interference adaptive RLS operation method and system for navigation arrays that can adapt to high sampling rate data streams and maintain anti-interference performance, while significantly reducing RLS operation complexity and achieving temperature rise control.

[0007] (2) Technical solution

[0008] The present invention is implemented through the following technical solution: The present invention proposes a navigation array anti-interference adaptive RLS operation system, the operation system comprising:

[0009] An array antenna with several elements;

[0010] A radio frequency front-end module connected to the array antenna;

[0011] An analog-to-digital conversion module connected to the RF front-end module;

[0012] a data stream generator connected to the analog-to-digital conversion module;

[0013] A clock synchronization module connected to the data stream generator;

[0014] A data control valve connected to a clock synchronization module;

[0015] RLS calculation unit connected to the control valve;

[0016] A control valve determiner connected to the RLS operation unit and the control valve;

[0017] A temperature sensor connected to the control valve determiner;

[0018] A navigation signal calculator connected to the clock synchronization module and the RLS operation unit;

[0019] a digital-to-analog conversion module connected to a navigation signal calculator;

[0020] The navigation array anti-interference adaptive RLS operation method implemented based on the above-mentioned operation system includes the following steps:

[0021] a. Signal reception and down-conversion processing:

[0022] Receive satellite signals through an array antenna configured with m array elements;

[0023] The RF front-end module down-converts the satellite signals output by each channel of the array antenna to generate m intermediate frequency signals;

[0024] b. Analog-to-digital conversion and data matrix construction:

[0025] The analog-to-digital conversion module synchronously samples the intermediate frequency signal in each channel with a sampling length of n to obtain data x(i, j) and construct a spatiotemporal sampling matrix X with m rows and n columns. The sampling length n can be arbitrarily long or infinite. If the sampling length is infinite, n→∞.

[0026] Among them, the row index i=1, 2, ..., m corresponds to the array channel number;

[0027] Column index j = 1, 2, ..., n corresponds to the time sampling number;

[0028] c. Data stream structured processing;

[0029] The data stream generator expands the m-row and n-column space-time matrix X into n m-row vectors Y(n)=[y(1), y(2), …, y(n)] in column-major order;

[0030] Here, each column vector is defined as: , j = 1, 2, …, n;

[0031] The clock frequency f in the clock synchronization module is s Output the column vector y(j) to the data control valve and the navigation calculation signal calculator in sequence. The clock synchronization module has n clock cycles.

[0032] d. Data control and RLS operation:

[0033] The data control valve selects the column vector y(j) corresponding to the current n-th clock cycle according to the valve signal g and outputs it to the RLS operation unit;

[0034] The RLS operation unit performs the following process:

[0035] First, the idle flag s is set to 0 and output to the control valve determiner to enter the calculation process, and then determine whether it is the first clock cycle. If yes, execute step I), otherwise execute step II);

[0036] Ⅰ) Initialization phase;

[0037] Direction vector ;

[0038] Covariance matrix ;

[0039] The forgetting factor λ satisfies 0.95≤λ≤0.99;

[0040] is a zero vector with m rows and 1 column, and I is an identity matrix with m-1 rows and m-1 columns;

[0041] II) Iterative update phase;

[0042] The RLS operation unit splits y(j) into b(j) and d(j);

[0043] b(j) is an m-1 row, 1 column vector consisting of the first m-1 rows of the input m-row, 1-column vector y(j). The input data is b(1), b(2), ..., b(j);

[0044] d(j) is the vector of the mth row and 1st column of the input m-row and 1-column vector y(j);

[0045] According to the formula, the process vector k(j) and the residual vector are calculated And update the direction vector w(j) and covariance matrix P(j), the formulas are:

[0046] ;

[0047] ;

[0048] ;

[0049] ;

[0050] The control valve determiner outputs a valve control signal g according to the current temperature t and the idle flag s;

[0051] is the conjugate transpose of the b(j) vector, is the conjugate transpose of y(j);

[0052] w(j) is an m-1 row and 1 column vector, specifically the m-1 row direction vector calculated by the RLS operation unit at the nth time period;

[0053] P(j) is an m-1 row and m-1 column matrix, specifically the covariance matrix of the input data b(1), b(2), ..., b(j) calculated by the RLS operation unit at the nth time period;

[0054] e. Update the direction vector assignment:

[0055] After the RLS operation unit completes the jth iteration, it sets the idle flag s to 1 and outputs the current direction vector w(j) to the navigation signal calculator;

[0056] When the navigation signal calculator detects s=1, it performs the assignment operation ;

[0057] When s=0, the navigation signal calculator maintains It is the most recently received valid value;

[0058] f. Navigation signal generation:

[0059] The navigation signal calculator splits y(j) into and ;

[0060] A vector with m-1 rows and 1 column consisting of the first m-1 rows of the input m-row and 1-column vector y(j);

[0061] is the mth row and 1st column vector of the input mth row and 1st column vector y(j);

[0062] The navigation signal calculator generates the navigation signal according to w(j) : ; is the conjugate transpose of w(j); the digital-to-analog conversion module converts z(j) into an analog navigation signal, which serves as the final output navigation signal of the RLS operation system.

[0063] Preferably, the logic of the idle flag s is: when the RLS operation unit completes the current iteration, s=1 is set, and when the next cycle is started, s=0 is set.

[0064] Preferably, m in step a is ≥ 2 and is a natural number.

[0065] Preferably, the control valve determiner has a determination rule as follows: when the current system operating temperature is less than the set upper temperature limit and the RLS operation unit is in an idle state, the valve control signal g is 1, otherwise it is 0. The rule is:

[0066] ; The upper temperature limit set for the computing system, t is the operating temperature of the computing system; It is dynamically adjusted (set directly according to actual needs).

[0067] Preferably, the spatiotemporal sampling matrix X with m rows and n columns in step b is as follows:

[0068] .

[0069] Preferably, in step b, the specific operation of the clock synchronization module is: outputting the column vector y(j) in sequence to the data control valve and the navigation calculation signal calculator, and corresponding the clock cycle to the transmission of a column vector y(j) within n clock cycles, that is, outputting y(1) in the first clock cycle, outputting y(2) in the second clock cycle, and so on to outputting y(n) in the nth clock cycle; for example, if the clock of the clock synchronization module is 125MHz, then every 8ns is a system clock cycle, and the y(n)th group of data is output in each clock cycle.

[0070] Preferably, the computing system is implemented based on an FPGA chip. The upper temperature limit set for the FPGA chip, t is the operating temperature of the FPGA chip; It is dynamically adjusted (set directly according to actual needs).

[0071] (3) Beneficial effects

[0072] The present invention generates a valve control signal by determining the idle flag s and the system temperature t, and selects the covariance matrix and direction vector to perform different operations based on whether the value of g is 1 (valid). When the RLS operation unit is not in an idle state or the system operating temperature is higher than the set value, the covariance matrix and direction vector are controlled by g to perform simplified operations, which can reduce the system's computational load and power consumption, reduce system heating caused by high computation, and thus return the system to the expected temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0074] Figure 1 This is a system block diagram of the present invention. DETAILED DESCRIPTION

[0075] Reference Figure 1 As shown, the present invention proposes a navigation array anti-interference adaptive RLS operation system, the operation system includes:

[0076] An array antenna with several elements;

[0077] A radio frequency front-end module connected to the array antenna;

[0078] An analog-to-digital conversion module connected to the RF front-end module;

[0079] a data stream generator connected to the analog-to-digital conversion module;

[0080] A clock synchronization module connected to the data stream generator;

[0081] A data control valve connected to a clock synchronization module;

[0082] RLS calculation unit connected to the control valve;

[0083] A control valve determiner connected to the RLS operation unit and the control valve;

[0084] A temperature sensor connected to the control valve determiner;

[0085] A navigation signal calculator connected to the clock synchronization module and the RLS operation unit;

[0086] a digital-to-analog conversion module connected to a navigation signal calculator;

[0087] The navigation array anti-interference adaptive RLS operation method implemented based on the above-mentioned operation system includes the following steps:

[0088] a. Signal reception and down-conversion processing:

[0089] Receive satellite signals through an array antenna configured with m array elements;

[0090] The RF front-end module down-converts the satellite signals output by each channel of the array antenna to generate m intermediate frequency signals;

[0091] b. Analog-to-digital conversion and data matrix construction:

[0092] The analog-to-digital conversion module synchronously samples the intermediate frequency signal in each channel with a sampling length of n to obtain data x(i, j) and construct a spatiotemporal sampling matrix X with m rows and n columns. The sampling length n can be arbitrarily long or infinite. If the sampling length is infinite, n→∞.

[0093] Among them, the row index i=1, 2, ..., m corresponds to the array channel number;

[0094] Column index j = 1, 2, ..., n corresponds to the time sampling number;

[0095] c. Data stream structured processing;

[0096] The data stream generator expands the m-row and n-column space-time matrix X into n m-row vectors Y(n)=[y(1), y(2), …, y(n)] in column-major order;

[0097] Here, each column vector is defined as: , j = 1, 2, …, n;

[0098] The clock frequency f in the clock synchronization module is s Output the column vector y(j) to the data control valve and the navigation calculation signal calculator in sequence. The clock synchronization module has n clock cycles.

[0099] d. Data control and RLS operation:

[0100] The data control valve selects the column vector y(j) corresponding to the current n-th clock cycle according to the valve signal g and outputs it to the RLS operation unit;

[0101] The RLS operation unit performs the following process:

[0102] First, the idle flag s is set to 0 and output to the control valve determiner to enter the calculation process, and then determine whether it is the first clock cycle. If yes, execute step I), otherwise execute step II);

[0103] Ⅰ) Initialization phase;

[0104] Direction vector ;

[0105] Covariance matrix ;

[0106] The forgetting factor λ satisfies 0.95≤λ≤0.99;

[0107] is a zero vector with m rows and 1 column, and I is an identity matrix with m-1 rows and m-1 columns;

[0108] II) Iterative update phase;

[0109] The RLS operation unit splits y(j) into b(j) and d(j);

[0110] b(j) is an m-1 row and 1 column vector consisting of the first m-1 rows of the input m-row and 1 column vector y(j);

[0111] d(j) is the vector of the mth row and 1st column of the input m-row and 1-column vector y(j);

[0112] According to the formula, the process vector k(j) and the residual vector are calculated And update the direction vector w(j) and covariance matrix P(j), the formulas are:

[0113] ;

[0114] ;

[0115] ;

[0116] ;

[0117] The control valve determiner outputs a valve control signal g according to the current temperature t and the idle flag s;

[0118] is the conjugate transpose of the b(j) vector, is the conjugate transpose of y(j);

[0119] w(j) is an m-1 row and 1 column vector, specifically the m-1 row direction vector calculated by the RLS operation unit at the nth time period;

[0120] P(j) is an m-1 row and m-1 column matrix, specifically the covariance matrix of the input data b(1), b(2), ..., b(j) calculated by the RLS operation unit at the nth time period;

[0121] e. Update the direction vector assignment:

[0122] After the RLS operation unit completes the jth iteration, it sets the idle flag s to 1 and outputs the current direction vector w(j) to the navigation signal calculator;

[0123] When the navigation signal calculator detects s=1, it performs the assignment operation ;

[0124] When s=0, the navigation signal calculator maintains It is the most recently received valid value;

[0125] f. Navigation signal generation:

[0126] The navigation signal calculator splits y(j) into and ;

[0127] A vector with m-1 rows and 1 column consisting of the first m-1 rows of the input m-row and 1-column vector y(j);

[0128] is the mth row and 1st column vector of the input mth row and 1st column vector y(j);

[0129] The navigation signal calculator generates the navigation signal according to w(j) : ; is the conjugate transpose of w(j); the digital-to-analog conversion module converts z(j) into an analog navigation signal, which serves as the final output navigation signal of the RLS operation system;

[0130] The logic of the idle flag s is: when the RLS operation unit completes the current iteration, s is set to 1, and when the next cycle is started, s is set to 0;

[0131] Wherein, m in step a is ≥ 2 and is a natural number;

[0132] The control valve determiner has a determination rule as follows: when the current system operating temperature is less than the set upper temperature limit and the RLS operation unit is in an idle state, the valve control signal g is 1, otherwise it is 0. The rule is:

[0133] ; The upper temperature limit set for the computing system, t is the operating temperature of the computing system; Dynamic adjustment (directly set according to actual needs);

[0134] The spatiotemporal sampling matrix X with m rows and n columns in step b is as follows:

[0135] ;

[0136] Wherein, in the step b, the specific operation of the clock synchronization module is: outputting the column vector y(j) to the data control valve and the navigation calculation signal calculator in sequence, and corresponding the clock cycle to the transmission of one column vector y(j) within n clock cycles, that is, outputting y(1) in the first clock cycle, outputting y(2) in the second clock cycle, and so on to outputting y(n) in the nth clock cycle; for example, if the clock of the clock synchronization module is 125MHz, then every 8ns is one system clock cycle, and the y(n)th group of data is output in each clock cycle;

[0137] Wherein, the computing system is implemented based on FPGA chip. The upper temperature limit set for the FPGA chip, t is the operating temperature of the FPGA chip; It is dynamically adjusted (set directly according to actual needs).

[0138] In its specific implementation, the present invention achieves the following core advantages through algorithm optimization and system-level collaborative control mechanism:

[0139] In traditional RLS operation systems, the maximum amount of computation and the maximum power consumption, i.e., heat generation, lie in the covariance matrix P(j) and In fact, in the actual working process of navigation equipment, P(j) and The present invention generates a valve control signal g by judging the idle flag s and the system temperature t, and selects P(j) and Perform different operations. When the RLS operation unit is not in idle state or the system operating temperature is higher than the set value, g is used to control P(j) and Simplified operations can reduce the system's computational load and power consumption, lowering system heat generation caused by high computational effort, thereby returning the system to its expected temperature. This overcomes the computational bottleneck and temperature rise contradiction of traditional RLS algorithms in high-sampling-rate scenarios. This approach is particularly suitable for high-precision military / civilian navigation terminals such as BeiDou-3 and GPS III, as well as for scenarios such as dynamic anti-interference for drones and multipath suppression for autonomous driving. Specifically:

[0140] (1) Optimization of vector segmentation (two-segmentation). That is, the segmentation operation of the navigation signal calculator is consistent with that of the RLS operation unit, but the functional objectives are different:

[0141] The specific operations are:

[0142] The RLS operation unit splits the input vector y(j) into b(j) and d(j);

[0143] The definition of the vector split operation is that the input vector is split, and it can be seen that b(j) is a vector with m-1 rows and 1 column composed of the first m-1 rows of the input m-row and 1-column vector y(j);

[0144] d(j) is the vector of the mth row and 1st column of the input mth row and 1st column vector y(j), that is,

[0145] ;

[0146] This operation reduces the dimension of subsequent matrix operations by intercepting part of the data;

[0147] The mathematical significance of the above dimensionality reduction is that the covariance matrix p(j) of the traditional RLS algorithm has dimensions of m×m and a complexity of O(m 2 ), and after segmentation, only p(j) of (m-1)×(m-1) dimensions needs to be processed, and the complexity is reduced to O((m−1) 2 );

[0148] In addition, computing resource optimization is also achieved. In terms of hardware implementation, in FPGA chips, matrix multiplication and inversion operations occupy a large amount of logic resources. After partitioning, the matrix dimension is reduced to (m-1), and the number of multiplication and addition operations is significantly reduced, which is suitable for pipeline parallel processing.

[0149] For example, when m = 8, the size of the covariance matrix is ​​reduced from 8 × 8 to 7 × 7, and the theoretical number of multiplications and additions is reduced by about 15%;

[0150] It also realizes the coordinated cooperation of dynamic valve control, that is, the combination of the determination mechanism of the control valve determiner and the segmentation mechanism further reduces the instantaneous power consumption;

[0151] The navigation signal calculator splits y(j) into and , so that the segmentation of navigation signal generation is realized, specifically:

[0152] A vector with m-1 rows and 1 column consisting of the first m-1 rows of the input m-row and 1-column vector y(j);

[0153] is the mth row and 1st column vector of the input mth row and 1st column vector y(j);

[0154] And the navigation signal calculator generates the navigation signal according to w(j) : , thereby ensuring input data alignment and maintaining signal integrity. Unlike the traditional RLS method that reduces dimensionality by discarding data, this segmentation mechanism retains the complete signal dimension and only reduces the dimensionality through mathematical operations, avoiding navigation deviation caused by signal loss;

[0155] (2) Real-time processing capability of streaming data:

[0156] Structured data streaming: The data stream generator expands the spatiotemporal matrix X into n m-dimensional column vectors in a column-first manner. Combined with a clock synchronization module (e.g., a 125MHz clock cycle), this enables streaming processing at high sampling rates (>125Msps), eliminating the large cache required for traditional block processing.

[0157] Zero data dropout: Unlike traditional methods that randomly drop data or sample at fixed intervals, the valve control mechanism of the data control valve in this invention only skips some operations rather than the data itself. That is, when g = 0, only the iterative update of p(j) is skipped, retaining the original data y(j) for transmission to the navigation signal calculator. This ensures signal integrity (such as phase continuity and chip alignment) and avoids spectral leakage introduced by traditional fixed-interval sampling.

[0158] Real-time verification: Test data shows that at a sampling rate of 125Msps, the single-cycle latency of streaming processing is 8ns (matching the clock cycle), while traditional block processing requires an additional wait of n cycles due to matrix filling (for example, the latency increases 1000 times when n=1024).

[0159] (3) Temperature rise control and power consumption optimization:

[0160] Temperature feedback mechanism: The temperature sensor monitors the FPGA chip temperature in real time and controls the valve determiner to dynamically adjust the data throughput. When the temperature approaches the threshold, the valve signal g = 0, pausing data input to the RLS operation unit. The rules are as follows:

[0161] ; The upper temperature limit set for the computing system, t is the operating temperature of the computing system; Dynamic adjustment (directly set according to actual needs) reduces instantaneous power consumption and temperature rise rate. This mechanism can avoid the overall performance loss caused by traditional global cooling solutions (such as frequency reduction);

[0162] Efficient use of hardware resources: When implemented based on FPGA chips, the coordination of the status flag s and the valve signal g reduces the occupancy of logic units and multipliers, avoiding timing conflicts caused by resource competition.

[0163] (IV) Maintaining anti-interference performance

[0164] Dynamic update of the direction vector: The navigation signal calculator updates w(j) only when s=1, ensuring that the direction vector matches the current interference environment and suppressing narrowband interference and multipath effects;

[0165] Forgetting factor optimization: The forgetting factor λ is set to satisfy 0.95≤λ≤0.99, balancing the algorithm convergence speed and steady-state error to adapt to the non-stationary characteristics of satellite navigation signals.

[0166] The comparative advantages of the present invention over the traditional technology are shown in Table 1:

[0167] Table 1:

[0168]

[0169] The present invention solves the key problem of the contradiction between high complexity and high real-time performance in navigation array anti-interference through the triple strategy of vector segmentation (reducing matrix dimension), dynamic valve control (balancing load and temperature rise) and recursive update optimization (avoiding matrix inversion), providing a feasible technical path for high-precision navigation scenarios such as Beidou.

Claims

1. A navigation array anti-interference adaptive RLS operation method, the method is implemented based on an RLS operation system; Its characteristics are: The steps include: a. Signal reception and down-conversion processing: Receive satellite signals through an array antenna configured with m array elements; The RF front-end module down-converts the satellite signals output by each channel of the array antenna to generate m intermediate frequency signals; b. Analog-to-digital conversion and data matrix construction: The analog-to-digital conversion module synchronously samples the intermediate frequency signal in each channel with a sampling length of n, obtains the data x(i, j), and constructs a spatiotemporal sampling matrix X with m rows and n columns; Among them, the row index i=1, 2, ..., m corresponds to the array channel number; Column index j = 1, 2, ..., n corresponds to the time sampling number; c. Data stream structured processing; The data stream generator expands the m-row and n-column space-time matrix X into n m-row vectors Y(n)=[y(1), y(2), …, y(n)] in column-major order; Here, each column vector is defined as: , j = 1, 2, …, n; The clock frequency f in the clock synchronization module is s Output the column vector y(j) to the data control valve and the navigation calculation signal calculator in sequence. The clock synchronization module has n clock cycles. d. Data control and RLS operation: The data control valve selects the column vector y(j) corresponding to the current n-th clock cycle according to the valve signal g and outputs it to the RLS operation unit; The RLS operation unit performs the following process: First, the idle flag s is set to 0 and output to the control valve determiner to enter the calculation process, and then determine whether it is the first clock cycle. If yes, execute step I), otherwise execute step II); Ⅰ) Initialization phase; Direction vector ; Covariance matrix ; The forgetting factor λ satisfies 0.95≤λ≤0.99; is a zero vector with m rows and 1 column, and I is an identity matrix with m-1 rows and m-1 columns; II) Iterative update phase; The RLS operation unit splits y(j) into b(j) and d(j); b(j) is an m-1 row, 1 column vector consisting of the first m-1 rows of the input m-row, 1 column vector y(j). The input data is b(1), b(2), ..., b(j); d(j) is the vector in the mth row and 1st column of the input m-row and 1-column vector y(j); According to the formula, the process vector k(j) and the residual vector are calculated And update the direction vector w(j) and covariance matrix P(j), the formulas are: ； ； ； ； The control valve determiner outputs a valve control signal g according to the current temperature t and the idle flag s; is the conjugate transpose of the b(j) vector, is the conjugate transpose of y(j); w(j) is an m-1 row and 1 column vector, specifically the m-1 row direction vector calculated by the RLS operation unit at the nth time period; P(j) is an m-1 row and m-1 column matrix, specifically the covariance matrix of the input data b(1), b(2), ..., b(j) calculated by the RLS operation unit at the nth time period; e. Update the direction vector: After the RLS operation unit completes the jth iteration, it sets the idle flag s to 1 and outputs the current direction vector w(j) to the navigation signal calculator; When the navigation signal calculator detects s=1, it performs the assignment operation ; When s=0, the navigation signal calculator maintains It is the most recently received valid value; f. Navigation signal generation: The navigation signal calculator splits y(j) into and ; A vector with m-1 rows and 1 column consisting of the first m-1 rows of the input m-row and 1-column vector y(j); is the mth row and 1st column vector of the input mth row and 1st column vector y(j); The navigation signal calculator generates the navigation signal according to w(j) : ; is the conjugate transpose of w(j); the digital-to-analog conversion module converts z(j) into an analog navigation signal, which serves as the final output navigation signal of the RLS operation system.

2. The navigation array anti-interference adaptive RLS calculation method according to claim 1, characterized in that: The logic of the idle flag s is: when the RLS operation unit completes the current iteration, s is set to 1, and when the next cycle is started, s is set to 0.

3. The navigation array anti-interference adaptive RLS calculation method according to claim 1, characterized in that: In step a, m≥2 and is a natural number.

4. The navigation array anti-interference adaptive RLS calculation method according to claim 1, characterized in that: The control valve determiner determines the following rules: when the current system operating temperature is less than the set upper temperature limit and the RLS operation unit is in an idle state, the valve control signal g is 1, otherwise it is 0. The rules are: ; The upper temperature limit set for the computing system, t is the operating temperature of the computing system; For dynamic adjustment.

5. The navigation array anti-interference adaptive RLS calculation method according to claim 1, characterized in that: The spatiotemporal sampling matrix X with m rows and n columns in step b is as follows: 。 6. The navigation array anti-interference adaptive RLS calculation method according to claim 1, characterized in that: In step b, the specific operation of the clock synchronization module is: outputting the column vector y(j) to the data control valve and the navigation calculation signal calculator in sequence, and corresponding the clock cycle to the transmission of one column vector y(j) within n clock cycles, that is, outputting y(1) in the first clock cycle, outputting y(2) in the second clock cycle, and so on until outputting y(n) in the nth clock cycle.

7. A navigation array anti-interference adaptive RLS operation system for implementing the method according to any one of claims 1 to 6, characterized in that: The operating system includes: An array antenna with several elements; A radio frequency front-end module connected to the array antenna; An analog-to-digital conversion module connected to the RF front-end module; a data stream generator connected to the analog-to-digital conversion module; A clock synchronization module connected to the data stream generator; A data control valve connected to a clock synchronization module; RLS calculation unit connected to the control valve; A control valve determiner connected to the RLS operation unit and the control valve; A temperature sensor connected to the control valve determiner; A navigation signal calculator connected to the clock synchronization module and the RLS operation unit; A digital-to-analog conversion module connected to the navigation signal calculator.

8. The navigation array anti-interference adaptive RLS operation system according to claim 7, characterized in that: The computing system is implemented based on an FPGA chip.

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