A MCU chip adaptation evaluation method

Abstract

The present invention discloses a method for evaluating the adaptation of an MCU chip. The method comprises: determining the corresponding MCU computing power requirements based on each application scenario of a vehicle controller; abstracting the computing power requirements of each MCU based on computing elements to construct MCU operation assessment test cases corresponding to each application scenario; determining the assessment ratio or weight of each MCU operation assessment test case based on the proportion of the demand for MCU computing power of each application scenario, combining each test case based on the assessment ratio or weight to form a combined test case; performing MCU operation assessment tests on each MCU chip based on the combined test case to obtain the minimum execution time of the typical algorithm corresponding to the combined test case for each MCU chip to complete; and determining the most suitable MCU chip based on the minimum execution time. The present invention implements the evaluation of the computing power adaptability of the MCU chip based on the computing requirements of the vehicle controller application scenario, which can reduce the time and cost of MCU selection and adaptation.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip evaluation, and more specifically, relates to an MCU chip adaptation evaluation method. Background Art

[0002] Amid the rapid development of intelligent and connected vehicles, automotive chips have become a core driving force behind this progress. Automotive-grade microcontroller units (MCUs), with their superior performance and high degree of integration, are widely used in a range of key components, including vehicle control units (ECUs) and battery management systems (BMSs). These critical components are like the vehicle's "nerve center" and "energy steward," with the MCU chip carrying the heavy responsibility of executing core control algorithms. These algorithms are directly related to the precise implementation of various vehicle functions and the reliable protection of the safety of drivers and passengers.

[0003] However, the current state of MCU chip testing primarily relies solely on chip manuals, reliability testing standards such as AEC-Q100, and the ISO26262 functional safety standard. While these traditional testing methods can assess the basic performance and safety of chips to a certain extent, they have significant limitations. They severely lack customized testing methods and specialized equipment tailored to the core control algorithm requirements of MCU chips. This results in a lack of comprehensive, in-depth, and accurate assessment of MCU chips' suitability for specific vehicle controller applications. This lack of effective evaluation makes it difficult for automakers and R&D personnel to obtain targeted and guiding guidance when selecting MCU chips. This can impact the optimization of overall vehicle performance, expansion of functionality, and improvement of safety, hindering the efficient development of intelligent and connected vehicles.

[0004] The information disclosed in the background technology section of the present invention is only intended to deepen the understanding of the general background technology of the present invention, and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to propose an MCU chip adaptation evaluation method to solve the problem that traditional evaluation methods cannot comprehensively, deeply and accurately evaluate whether the MCU chip is truly suitable for the application scenario of the corresponding vehicle controller and are difficult to match actual needs. It can accurately evaluate and screen MCU chips that are adapted to the vehicle controller application scenario.

[0006] To achieve the above objectives, the present invention proposes an MCU chip adaptation evaluation method, comprising:

[0007] Determine the corresponding MCU computing power requirements based on each application scenario of the vehicle controller;

[0008] Abstract the computing power requirements of each MCU based on computing elements to construct MCU computing assessment test cases corresponding to each application scenario;

[0009] Determine the assessment ratio or weight of each MCU operation assessment test case based on the proportion of MCU computing power requirements of each application scenario;

[0010] Based on the assessment ratio or weight, the MCU operation assessment test cases are combined to form a combination test case; based on the combination test case, the MCU operation assessment test is performed on each MCU chip separately to obtain the minimum execution time of each MCU chip to complete the typical algorithm corresponding to the combination test case; based on the minimum execution time of each MCU chip to complete the typical algorithm of the combination test case, the most suitable MCU chip is determined.

[0011] Optionally, it also includes:

[0012] Based on each of the MCU operation assessment test cases, an MCU operation assessment test is performed on each MCU chip to obtain the minimum execution time of each MCU chip to complete the typical algorithm corresponding to each of the MCU operation assessment test cases;

[0013] Based on the sum of the minimum execution time of each MCU chip to complete the typical algorithm of each MCU operation assessment test case and the product of the assessment ratio or weight, the one with the smallest sum is selected as the most suitable MCU chip.

[0014] Optionally, the calculation elements include:

[0015] Computing paradigm, computational effort, and storage capacity.

[0016] Optionally, determining the most suitable MCU chip based on the minimum execution time of each MCU chip to complete the typical algorithm of each test case further includes:

[0017] Compare the minimum execution time of each MCU chip to complete the typical algorithm of the combination test case, and select the one with the shortest total minimum execution time as the most suitable MCU chip.

[0018] Optionally, performing the MCU operation assessment test based on the combined test case or each MCU operation assessment test case includes:

[0019] The combination test case or each MCU operation assessment test case is loaded into the MCU chip through the hardware-in-the-loop system, and the MCU chip is controlled to execute the relevant operations of the combination test case or each MCU operation assessment test case.

[0020] Optionally, the MCU chip is designed as an MCU chip test board, and the hardware-in-the-loop system is communicatively connected to the MCU chip test board.

[0021] Optionally, the hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit and a result processing unit;

[0022] The signal sending unit is used to send control signals and test case data to the MCU chip test board;

[0023] The signal acquisition unit is used to collect the start time and end time of the MCU chip test board executing the combined test case or each MCU operation assessment test case;

[0024] The result processing unit is used to calculate the minimum execution time of the MCU chip test board to execute the combined test case or each MCU operation assessment test case, and to calculate the total minimum execution time of the MCU chip test board to execute each MCU operation assessment test case based on the minimum execution time of each MCU operation assessment test case.

[0025] Optionally, the control signal includes a wake-up signal, an ignition signal and a test instruction;

[0026] The wake-up signal is used to activate the communication between the MCU chip test board and the hardware-in-the-loop system;

[0027] The ignition signal is used to control the MCU chip test board to power on and initialize;

[0028] The test instruction is used to control the MCU chip to call each MCU operation assessment test case or combined test case.

[0029] Optionally, the result processing unit calculates the total minimum execution time of each MCU operation assessment test case as follows:

[0030]

[0031] in, , is the minimum execution time of the i-th test case, is the assessment ratio or weight of the i-th test case, , is the end time of the i-th test case, The starting time of the i-th test case, m is the total number of MCU operation assessment test cases.

[0032] Optionally, the formula used by the result processing unit to calculate the minimum execution time of the combined test case is:

[0033]

[0034] in, T 2 is the start time of the combined test case, T 1 is the end time of the combined test case.

[0035] The beneficial effects of the present invention are: starting from the various application scenarios of the vehicle controller, the present invention converts the computing power requirements into quantifiable test indicators, avoiding the problem of traditional testing being out of touch with actual working conditions, and ensuring that the screened MCU chips meet actual control requirements; allocating test weights according to the proportion of application scenario requirements to form combined test cases, with the minimum execution time as the core quantitative indicator, providing a unified and objective horizontal comparison benchmark for MCU chips of different manufacturers and models, reducing the cost of selection decision-making; ensuring that the selected MCU chip can still efficiently run typical algorithms under mixed loads in multiple scenarios, optimizing the real-time response capability and stability of the vehicle controller, indirectly improving the functional safety and intelligent networking level of the entire vehicle, establishing a closed-loop methodology from demand analysis to test verification, and providing reusable industry standards for the selection of automotive-grade MCU chips, helping to solve the technical pain points of traditional testing that lack specificity, and accelerating the localization process of automotive chips. The present invention can realize the evaluation of the computing power adaptability of the MCU chip based on the computing requirements of the vehicle controller application scenario, thereby avoiding the MCU chip being unsuitable for the corresponding vehicle controller computing power requirements or extreme requirements. It can reduce the selection and adaptation time and cost of vehicle manufacturers and controller manufacturers, and can also be used by chip design companies to better discover chip definition deviations and problems in the early stages, and guide vehicle design.

[0036] The system of the present invention has other features and advantages that will be apparent from or will be described in detail in the accompanying drawings and subsequent detailed description incorporated herein, which together serve to explain the specific principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which like reference numerals generally represent like components.

[0038] Figure 1 A flowchart showing the steps of an MCU chip adaptation evaluation method according to embodiment 1 of the present invention is shown.

[0039] Figure 2 A schematic diagram of a hardware-in-the-loop system according to embodiment 1 of the present invention is shown. DETAILED DESCRIPTION

[0040] The present invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention may be implemented in various forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present invention more thorough and complete and to fully convey the scope of the present invention to those skilled in the art.

[0041] Example 1

[0042] A method for evaluating MCU chip adaptation according to the present invention includes:

[0043] S1. Determine the corresponding MCU computing power requirements based on each application scenario of the vehicle controller;

[0044] Specifically, the computing power requirements of a vehicle controller's MCU (microcontroller unit) are directly related to the complexity of its application scenario, real-time requirements, and data processing volume. Different controllers (such as powertrain, chassis systems, and body electronics) have significantly different requirements for MCU performance, including clock speed, number of cores, memory capacity, and bus bandwidth, due to their diverse functions. For example, the application scenarios of motor controllers include motor vector control, torque closed-loop control, weak magnetic control, overheating protection, energy recovery, etc. of electric / hybrid vehicles. The motor controller is responsible for motor speed, torque, and position control, and executes vector control (FOC), PID adjustment and other algorithms. Its computing power requirements are characterized by high-speed fixed-point operations (such as coordinate transformation), serial real-time response (microsecond control cycle), and fixed storage control parameter table; the application scenarios of battery controllers include charging, discharging, battery safety protection and other scenarios. The battery controller needs to process real-time data such as battery voltage, current, and temperature, and execute state estimation (such as SOC / SOH), balancing control and other algorithms. Its computing power requirements are characterized by high-frequency floating-point operations (such as Kalman filtering), parallel processing of multi-cell data, and dynamic storage of battery status tables; the application scenarios of transmission controllers include automatic shifting, hybrid coupling, transmission protection and fault diagnosis, etc. The shift controller is responsible for coordinating signals from multiple components such as the clutch, transmission, and engine, and executing shift logic and torque coordination algorithms; its computing power requirements are characterized by heterogeneous computing (logic control + Real-time scheduling), high storage throughput (caching multi-component state data), and mixed-precision operations (fixed-point + floating-point).

[0045] S2. Abstract the computing power requirements of each MCU based on computing elements to construct MCU computing assessment test cases corresponding to each application scenario;

[0046] Among them, computing elements include: computing paradigm, computing capacity and storage capacity;

[0047] Specifically, this embodiment abstracts the computing power requirements of each MCU from three dimensions: computing paradigm, computing amount, and storage capacity, converts vague computing requirements into standardized and executable test items, and constructs MCU computing assessment test cases corresponding to each application scenario; the computing paradigm refers to the algorithm type and processing logic when the MCU executes a task, which directly affects its computing complexity and architectural adaptability, and considers the different requirements of serial computing and parallel computing, among which parallel computing can be divided according to rules such as homogeneous computing and heterogeneous computing; the computing amount is used to quantify the computing task intensity of the MCU per unit time, and is usually measured by the number of instruction executions or the number of floating-point operations, considering different computing models such as floating-point operations and fixed-point operations, among which floating-point operations can be divided according to single floating-point operations, double floating-point operations, etc.; the storage capacity considers the constraints on storage space distribution after different computing models are deployed on the MCU chip, such as whether it can be dynamically expanded and the upper limit of storage space allocation. For example, in the computing paradigm dimension, the serial computing test item involves a single-threaded loop executing a sensor data verification algorithm to verify sequential execution efficiency; the parallel computing homogeneous computing test item involves multi-threaded synchronous processing of three-phase motor current sampling data to test multi-core load balancing capabilities; the heterogeneous computing test item involves a CPU+DSP combination executing a battery balancing algorithm (the CPU is responsible for logic scheduling, and the DSP handles floating-point operations) to verify the efficiency of heterogeneous core collaboration. In the computational capacity dimension, the floating-point arithmetic test item involves a single-precision test: performing 100,000 single-precision floating-point additions (simulating motor speed integration) to calculate the computation time; a double-precision test: performing double-precision floating-point iterative calculations of a battery model (such as the ampere-hour integration method) to verify high-precision computing capabilities; and the fixed-point arithmetic test item involves performing 100,000 fixed-point multiplications (simulating PWM duty cycle calculation) to test integer arithmetic throughput. In terms of storage capacity, the test items are static storage test: loading 1MB of control program code into Flash to verify the storage read and write speed and space utilization; dynamic storage test: running real-time data caching tasks (such as storing 1,000 sets of motor status data into RAM) to test the dynamic memory allocation efficiency and overflow protection mechanism.

[0048] S3. Determine the assessment ratio or weight of each MCU computing assessment test case based on the proportion of MCU computing power requirements in each application scenario;

[0049] Specifically, the demand ratio is determined based on the importance and frequency of MCU computing power requirements in actual operation of each application scenario of the vehicle controller; for example, in the battery controller, the assessment ratio or weight of the MCU operation assessment test case corresponding to the charging scenario is 35%, the assessment ratio or weight of the MCU operation assessment test case corresponding to the discharging scenario is 30%, and the assessment ratio or weight of the MCU operation assessment test case corresponding to the battery safety protection scenario is 35%.

[0050] S4. Combine the MCU operation assessment test cases based on the assessment ratio or weight to form a combined test case; perform MCU operation assessment tests on each MCU chip based on the combined test case to obtain the minimum execution time of each MCU chip to complete the typical algorithm corresponding to the combined test case; determine the most suitable MCU chip based on the minimum execution time of each MCU chip to complete the typical algorithm of the combined test case.

[0051] Specifically, the test cases for each scenario with assessment ratios or weights are integrated to form a set of combined test cases that simulate the mixed computing loads during the actual operation of the vehicle controller. For example, for the battery controller, the combined test cases include 35% charging scenario test cases, 30% discharging scenario test cases, and 35% battery protection scenario test cases. Through the combined test cases, the MCU operation assessment test is performed on each MCU chip separately to obtain the minimum execution time of each MCU chip to complete the typical algorithm corresponding to the combined test case. The typical algorithm refers to the algorithm model that can represent the core computing requirements of a specific application scenario. These algorithms are usually representative computing tasks abstracted from actual applications, which are used to simulate and verify the computing performance of the MCU in real scenarios. Finally, the most suitable MCU chip is determined based on the minimum execution time of each MCU chip to complete the typical algorithm of the combined test case.

[0052] This step also includes: performing MCU operation assessment tests on each MCU chip based on each MCU operation assessment test case, and obtaining the minimum execution time of each MCU chip to complete the typical algorithm corresponding to each MCU operation assessment test case;

[0053] Based on the sum of the minimum execution time of each MCU chip to complete the typical algorithm of each MCU operation assessment test case and the assessment ratio or weight product, the one with the smallest sum is selected as the most suitable MCU chip.

[0054] Specifically, in this step, it is also possible not to use a combined test case for testing, but to directly use each MCU operation assessment test case to perform MCU operation assessment test on each MCU chip separately, and then obtain the minimum execution time of each MCU chip to complete the typical algorithm corresponding to each MCU operation assessment test case, and then according to the sum of the minimum execution time of each MCU chip to complete the typical algorithm of each MCU operation assessment test case and the assessment ratio or weight product, select the one with the smallest sum of the minimum execution time and the assessment ratio or weight product as the most suitable MCU chip. For example, the assessment ratio or weight of the MCU operation assessment test case corresponding to the charging scenario is 35%, the assessment ratio or weight of the MCU operation assessment test case corresponding to the discharging scenario is 30%, and the assessment ratio or weight of the MCU operation assessment test case corresponding to the battery safety protection scenario is 35%. The minimum execution time of the charging scenario of MCU-A is 20.3, the minimum execution time of the discharging scenario is 20.5, and the minimum execution time of the safety protection scenario is 7.9. The minimum execution time of the charging scenario of MCU-B is 12.7, the minimum execution time of the discharging scenario is 13.4, and the minimum execution time of the safety protection scenario is 5.4. The minimum execution time of the charging scenario of MCU-C is 8.8, the minimum execution time of the discharging scenario is 10.1, and the minimum execution time of the safety protection scenario is 3.9. The total score of MCU-A is: 20.3 35%+20.5 30%+7.9 %35=15.95, the total score of MCU-B is 10.355, and the total score of MCU-C is 7.475, so MCU-C is the most suitable MCU chip.

[0055] In this step, the MCU operation assessment test based on the combined test case or each MCU operation assessment test case includes:

[0056] The combination test case or each MCU operation assessment test case is loaded into the MCU chip through the hardware-in-the-loop system, and the MCU chip is controlled to execute the relevant operations of the combination test case or each MCU operation assessment test case.

[0057] like Figure 2 As shown, the MCU chip is designed as an MCU chip test board, and the hardware-in-the-loop system is communicatively connected with the MCU chip test board.

[0058] The hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit, and a result processing unit;

[0059] The signal sending unit is used to send control signals and test case data to the MCU chip test board;

[0060] The signal acquisition unit is used to collect the start time and end time of the MCU chip test board executing the combined test case or each MCU operation assessment test case;

[0061] The result processing unit is used to calculate the minimum execution time of the MCU chip test board to execute the combined test case or each MCU operation assessment test case, and to calculate the total minimum execution time of the MCU chip test board to execute each MCU operation assessment test case based on the minimum execution time of each MCU operation assessment test case.

[0062] The control signals include wake-up signals, ignition signals and test instructions;

[0063] The wake-up signal is used to activate the communication between the MCU chip test board and the hardware-in-the-loop system;

[0064] The ignition signal is used to control the MCU chip test board for power supply and initialization;

[0065] The test instructions are used to control the MCU chip test board to call each MCU operation assessment test case or combined test case.

[0066] The formula for calculating the minimum execution time of the combined test case by the result processing unit is:

[0067]

[0068] in, T 2 is the start time of the combined test case, T 1 is the end time of the combined test case.

[0069] The formula for calculating the total minimum execution time of each MCU operation assessment test case by the result processing unit is:

[0070]

[0071] in, , is the minimum execution time of the i-th test case, is the assessment ratio or weight of the i-th test case, , is the end time of the i-th test case, The starting time of the i-th test case, m is the total number of MCU operation assessment test cases.

[0072] Specifically, this embodiment loads the test case into the MCU chip through the hardware-in-the-loop system, and controls the MCU chip to execute related operations of the test case combination. The MCU chip is designed as an MCU chip test board. The hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit and a result processing unit. The signal sending unit sends the wake-up signal to the MCU chip test board through the GPIO interface, activates the communication link between the MCU chip test board and the hardware-in-the-loop system, and prepares the MCU chip test board to receive and process subsequent instructions and data; sends the ignition signal to the MCU chip test board through the CANFD1 interface to simulate the vehicle ignition action, so that the MCU chip test board is powered and initialized to prepare for formal testing; sends test instructions to the MCU chip test board through the AD interface to instruct the MCU chip test board to call the corresponding test case and start a specific test process. Test data (Data 1, Data 2, ..., Data N) is sent to the MCU chip test board via the SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit Interface), and AD interfaces. This data simulates actual data collected by various sensors during vehicle operation and provides input for the MCU chip's computational testing. The MCU chip test board then calls each test case (Case 1, Case 2, ..., Case X) based on the test data to perform computational testing. The signal acquisition unit collects the test start time T1 and test end time T2 from the MCU chip test board via the CANFD2 interface and sends them to the result processing unit. Based on the collected test start time T1 and test end time T2, the result processing unit calculates the minimum execution time for the MCU chip test board to execute each MCU computational assessment test case or combination of test cases. It also calculates the total minimum execution time for the MCU chip test board to execute each MCU computational assessment test case based on the minimum execution time of each MCU computational assessment test case. Finally, the calculated results and other relevant test information are compiled to generate a test report output, facilitating test personnel's performance evaluation and analysis of each MCU chip. By simulating the whole vehicle signal interaction through the HIL system, the test process can be standardized and the results can be reproduced, reducing the cost of manual debugging.

[0073] The test process is as follows: The HIL system's signal transmission unit first sends a wake-up signal to activate communication between the MCU chip and the external environment, followed by an ignition signal to power and initialize the MCU chip. Next, a test instruction is sent, instructing the MCU chip to invoke a test case. Simultaneously, the HIL system's test data module sends various test data to the MCU chip test board. After invoking the test case and receiving the data, the MCU chip test board begins executing the computational test. During the test, the HIL system's signal acquisition unit records the test start time T1 and test end time T2. Finally, the HIL system's result processing unit uses the collected time information to calculate the minimum execution time ΔT for the MCU chip to complete the combined test case or the total minimum execution time for each MCU computational assessment test case, and then outputs a test report.

[0074] While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A MCU chip adaptation evaluation method, characterized in that: include: Determine the corresponding MCU computing power requirements based on each application scenario of the vehicle controller; Abstract the computing power requirements of each MCU based on computing paradigm, computing amount and storage capacity to construct MCU computing assessment test cases corresponding to each application scenario; determine the assessment ratio or weight of each MCU computing assessment test case based on the proportion of MCU computing power requirements of each application scenario; Combining the MCU operation assessment test cases based on the assessment ratio or weight to form a combined test case; performing an MCU operation assessment test on each MCU chip based on the combined test case to obtain the minimum execution time of the typical algorithm corresponding to the combined test case for each MCU chip; Determine the most suitable MCU chip based on the minimum execution time of each MCU chip to complete the typical algorithm of the combined test case; The combined test case is loaded into the MCU chip through the hardware-in-the-loop system, and the MCU chip is controlled to execute relevant operations of the combined test case.

2. The MCU chip adaptation evaluation method according to claim 1, characterized in that: Also includes: Based on each of the MCU operation assessment test cases, an MCU operation assessment test is performed on each MCU chip to obtain the minimum execution time of each MCU chip to complete the typical algorithm corresponding to each of the MCU operation assessment test cases; Based on the sum of the minimum execution time of each MCU chip to complete the typical algorithm of each MCU operation assessment test case and the product of the assessment ratio or weight, the one with the smallest sum is selected as the most suitable MCU chip.

3. The MCU chip adaptation evaluation method according to claim 1, characterized in that: The determination of the most suitable MCU chip based on the minimum execution time of each MCU chip to complete the typical algorithm of the combined test case also includes: Compare the minimum execution time of each MCU chip to complete the typical algorithm of the combination test case, and select the one with the shortest total minimum execution time as the most suitable MCU chip.

4. The MCU chip adaptation evaluation method according to claim 2, characterized in that: The MCU operation assessment test based on each MCU operation assessment test case includes: Each MCU operation assessment test case is loaded into the MCU chip through the hardware-in-the-loop system, and the MCU chip is controlled to execute the relevant operations of each MCU operation assessment test case.

5. The MCU chip adaptation evaluation method according to claim 4, characterized in that: The MCU chip is designed as an MCU chip test board, and the hardware-in-the-loop system is communicatively connected to the MCU chip test board.

6. The MCU chip adaptation evaluation method according to claim 5, characterized in that: The hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit and a result processing unit; The signal sending unit is used to send control signals and test case data to the MCU chip test board; The signal acquisition unit is used to collect the start time and end time of the MCU chip test board executing the combined test case or each MCU operation assessment test case; The result processing unit is used to calculate the minimum execution time of the MCU chip test board to execute the combined test case or each MCU operation assessment test case, and to calculate the total minimum execution time of the MCU chip test board to execute each MCU operation assessment test case based on the minimum execution time of each MCU operation assessment test case.

7. The MCU chip adaptation evaluation method according to claim 6, characterized in that: The control signal includes a wake-up signal, an ignition signal and a test instruction; The wake-up signal is used to activate the communication between the MCU chip test board and the hardware-in-the-loop system; The ignition signal is used to control the MCU chip test board to power on and initialize; The test instructions are used to control the MCU chip test board to call each MCU operation assessment test case or combined test case.

8. The MCU chip adaptation evaluation method according to claim 6, characterized in that: The formula for calculating the total minimum execution time of each MCU operation assessment test case by the result processing unit is: ； in, , is the minimum execution time of the i-th test case, is the assessment ratio or weight of the i-th test case, , is the end time of the i-th test case, The starting time of the i-th test case, m is the total number of MCU operation assessment test cases.

9. The MCU chip adaptation evaluation method according to claim 6, characterized in that: The formula used by the result processing unit to calculate the minimum execution time of the combined test case is: in, T 2 is the start time of the combined test case, T 1 is the end time of the combined test case.

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