Hardware-in-the-loop test system and method based on modular layered architecture

Abstract

The invention discloses a hardware-in-the-loop testing system and method based on a modular layered architecture, and belongs to the technical field of hardware-in-the-loop testing. The hardware-in-the-loop testing system comprises five layers of physical layered architectures; the driving layer is provided with a temperature sensor array, a variable rotating speed turbofan air cooling system and a gradient heat pipe array; a double-layer composite shielding structure is adopted between the master control and communication layer and the driving layer, a magnetic isolation driving and multi-stage LC filtering network is integrated, and the master control and communication layer is interconnected with the calculation layer, the signal layer and the interface adaptation layer through a bus; a two-way communication link is established between the driving layer and the calculation layer, and data transmission between the calculation layer and the signal layer is realized through a time-sensitive network; a signal layer deploys a dynamic compensation filtering architecture. Through a physical layered architecture (five layers of physical areas), a gradient heat dissipation strategy, a modular mechanical design and a full-link state feedback four-dimensional collaborative design, high reliability, strong expansibility and full-life-cycle intelligent operation and maintenance are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware-in-the-loop testing, and particularly to a hardware-in-the-loop testing system and method based on a modular hierarchical architecture. Background Art

[0002] With the evolution of automotive electronic and electrical architectures towards centralized architectures in the power domain, body domain, and autonomous driving domain, the requirements for functional safety and reliability verification of electronic control units (ECUs) have increased sharply. Traditional on-road vehicle testing methods are limited by long testing cycles, difficulty in replicating extreme working conditions, and safety hazards, and can no longer meet the agile development requirements of new ECUs.

[0003] In this context, hardware-in-the-loop (HIL) testing technology, with its advantages of full-life-cycle testing coverage, high-risk working condition safety simulation, and repeatable verification of accurately replicating fault scenarios at the millisecond level, has become an essential core verification method in fields such as automotive and aerospace. The software code volume of ECUs in modern vehicles has increased exponentially. Such systems involve the collaborative work of multi-core processors, high-speed bus communication, and heterogeneous computing units. If traditional on-road vehicle testing is relied upon to complete full-functional verification, it would take tens of thousands of hours of testing time and it would be difficult to cover all boundary conditions. HIL testing, through high-fidelity real-time simulation models and physical signal closed-loop injection technology, can simulate sensor signals, actuator loads, and vehicle dynamic characteristics in the laboratory, achieving extreme testing under all-weather and full-load working conditions, significantly shortening the development cycle and reducing the recall risk caused by ECU defects.

[0004] The hardware-in-the-loop testing platform is the basis for implementing HIL testing and the fundamental guarantee for the execution and verification of test cases. In the field of HIL testing systems, although mainstream solutions such as dSPACE and NI have partially solved basic problems such as EMC interference and fault location through closed architectures or modular designs, in the face of the evolution trend of automotive electronics towards high power density, multi-protocol integration, and rapid iteration, the inherent limitations of their underlying architectures are gradually emerging. Especially in the aspects of constructing high-fidelity signal chains, dynamic thermal management, and system reconfigurability, the existing technologies still face some technical problems: 1. In the existing HIL system architecture, the all-metal shielding and physical isolation strategy adopted by dSPACE and the module-level filtering design based on the PXIe bus by NI can locally improve the electromagnetic compatibility performance, but it is difficult to solve the problem of cross-level noise coupling between high-power and low-power modules. Currently, the technology generally co-locates high-power drive modules and precision signal modules, resulting in the coupling of switching power supply ripple noise and relay contact arc noise to the signal link through the common ground wire. The deep reason lies in the fragmentation of the existing electromagnetic compatibility suppression strategy: on the one hand, although the PXIe bus improves the transmission rate, it does not physically isolate the power layer, signal layer, and communication layer, resulting in high-frequency noise penetrating the shielding structure; on the other hand, the mainstream solutions often adopt a single grounding strategy and fail to design differentiated filtering paths according to the frequency-domain characteristics of conducted noise and radiated noise, resulting in low wide-band noise suppression efficiency.

[0005] 2. The current HIL system thermal management architecture faces the core contradictions of dynamic thermal load matching failure and cross-domain thermal interference diffusion. Although traditional fixed air-cooling and homogenized liquid-cooling solutions can meet the steady-state heat dissipation requirements, they are difficult to adapt to the high heat flux density impact under transient conditions. The existing technical paths show significant limitations: passive heat dissipation design cannot suppress the heat accumulation of sudden loads due to its response lag, resulting in local thermal imbalance and device life attenuation; active load reduction or redundant heat dissipation solutions can alleviate the temperature rise, but at the cost of sacrificing the test dynamic range or causing system volume expansion. The deeper bottleneck lies in the isolation failure of the system-level thermal topology. The cross-thermal coupling between high-power modules and signal chain units will cause ADC gain drift, resulting in the attenuation of test confidence with thermal stress correlation. This problem reflects the root defects of thermal management design in dimensions such as gradient heat dissipation distribution, non-linear thermal anti-coupling, and dynamic energy efficiency optimization. Summary of the Invention

[0006] Aiming at the deficiencies of the existing technology, the present invention provides a hardware-in-the-loop test system and method based on a modular hierarchical architecture. Through the four-dimensional collaborative design of a physical hierarchical architecture (five physical regions), a gradient heat dissipation strategy, a modular mechanical design, and a full-link state feedback, the present invention realizes high reliability, strong scalability, and intelligent operation and maintenance throughout the life cycle.

[0007] To achieve the above object, the present invention adopts the following technical solutions: In the first aspect, the present invention provides a hardware-in-the-loop test system based on a modular hierarchical architecture, including: a physical hierarchical architecture; the physical hierarchical architecture sequentially includes a main control and communication layer, a drive layer, a computing layer, a signal layer, and an interface adaptation layer; The main control and communication layer is used to drive the drive layer, and the drive layer is provided with a temperature sensor array, a variable-speed vortex fan air-cooling system, and a gradient heat pipe array; A double-layer composite shielding structure is adopted between the main control layer and the communication layer and the drive layer, and a magnetic isolation drive and a multi-stage LC filter network are integrated. The main control layer and the communication layer are interconnected with the computing layer, the signal layer, and the interface adaptation layer through a bus; a bidirectional communication link is established between the drive layer and the computing layer, and the computing layer also realizes data transmission with the signal layer through a time-sensitive network, and an orthogonal star-shaped grounding system is deployed between the computing layer and the signal layer; a dynamic compensation filtering architecture is deployed in the signal layer, and the signal layer is electrically connected to the interface adaptation layer.

[0008] As a further technical solution, the main control layer and the communication layer drive the drive layer based on the CAN protocol. The main control layer and the communication layer include a chassis, in which an upper industrial control computer, a controller, and a vehicle-mounted multi-protocol interface module are installed; wherein the upper industrial control computer communicates with the controller through the TCP / IP protocol.

[0009] As a further technical solution, the drive layer includes a power distribution unit, a programmable power supply, and a relay matrix module; wherein the power distribution unit is used for power distribution and management, and the relay matrix module responds to the trigger signal of the main control layer and the communication layer through the CAN protocol and controls the on / off of the power supply channel from the programmable power supply.

[0010] As a further technical solution, the computing layer includes an FPGA module, and simulation and acquisition processing programs for engine synchronization, fuel injection, ignition timing, PWM modulation, SENT signal parsing, and knock vibration characteristic analysis are embedded in the FPGA module.

[0011] As a further technical solution, the signal layer includes a fault injection module, an analog output and acquisition module, a digital output and acquisition module, a resistance simulation module, a to-be-tested ECU, an ECU calibration computer, and a load drawer; wherein the to-be-tested ECU interacts with the ECU calibration computer in real time through the Ethernet protocol, and the signal layer realizes its internal data throughput through a high-speed backplane.

[0012] As a further technical solution, the interface adaptation layer includes a wire harness connector, a digital signal conditioning module, an analog signal conditioning module, and a current-voltage conversion module; wherein, the digital signal conditioning module and the analog signal conditioning module respectively realize signal scaling through a dynamic gain control and a high-linearity amplification link.

[0013] As a further technical solution, the temperature sensor array is used to collect junction temperature data. According to the junction temperature data, a heat flow distribution model is established based on the three-dimensional unsteady heat conduction equation, specifically: ; wherein, is the temperature field distribution, is the time variable, = , denoted as the thermal diffusivity, is the heat generation rate per unit volume, is the thermal conductivity of the material.

[0014] As a further technical solution, the variable-speed vortex fan air-cooling system is configured with a centrifugal vortex fan driven by a brushless DC motor, and wide-range speed regulation is achieved according to the temperature rise gradient. Specifically: when the temperature exceeds the set threshold, the proportional-integral speed regulation algorithm is started, and the wind speed satisfies: ; where is the fan speed, is the time variable, is the temperature difference between the set temperature and the actual temperature.

[0015] As a further technical solution, the gradient heat pipe array is composed of three groups of heterogeneous heat pipes, which are divided into a high-temperature section, a medium-temperature section and a low-temperature section. The high-temperature section uses copper-water heat pipes, and the medium-temperature section and the low-temperature section are deployed with a composite capillary structure of aluminum-acetone heat pipes and sintered copper powder. The radial heat dissipation efficiency is enhanced through the gas-liquid phase change of the phase change material, and its maximum heat transfer power is determined by the capillary limit equation: ; where is the maximum heat transfer power of the heat pipe, is the pore diameter of the capillary structure, is the density of the working fluid liquid, is the latent heat of vaporization of the working fluid, is the surface tension coefficient, is the viscosity of the liquid working fluid, is the equivalent length of the heat pipe.

[0016] In a second aspect, the present invention provides a hardware-in-the-loop test method based on a modular hierarchical architecture. Based on the hardware-in-the-loop test system based on the modular hierarchical architecture according to any one of the first aspect, it includes: after the computing layer receives the instructions from the main control and communication layer through the bus, and based on the program embedded in the FPGA module, simulation is performed to obtain calibration parameters, operating condition data and fault codes, and they are transmitted to the signal layer through the time-sensitive network; the signal layer injects test signals into the ECU under test based on the received calibration parameters, operating condition data and fault codes to simulate the actual operating conditions; the ECU under test interacts with the ECU calibration computer in real time through the Ethernet protocol.

[0017] One or more technical solutions of the present invention have the following beneficial effects: (1) By constructing a collaborative suppression system of a physical hierarchical architecture (five-layer physical isolation architecture) and multi-modal filtering technology, the present invention effectively solves the problem of cross-layer noise coupling between high- and low-power modules. The composite shielding structure between layers and the orthogonal star-shaped grounding system increase the attenuation amplitude of conducted noise by 40 dB@1 MHz - 1 GHz, and reduce the radiated noise field strength to 3 V / m (EN55022 Class B standard), providing an "electromagnetically clean" environment for high-precision signal links; the dynamic compensation filtering technology further optimizes signal integrity, supports the reliable acquisition of weak signals (such as μV-level sensor data), meets the stringent electromagnetic compatibility standard requirements of automotive electronics such as ISO 11452-2, and provides an electromagnetically pure environment for high-precision testing.

[0018] (2) Based on the collaborative design of an intelligent temperature control strategy and a gradient heat pipe array, the system achieves rapid thermal equilibrium and precise temperature control under extreme conditions. The thermal response speed is several times faster than the traditional solution (≤15 s), and the device stability is significantly enhanced. Through the intelligent matching of heat dissipation efficiency and energy consumption, the overall power consumption of the system is effectively reduced, while suppressing the performance impact of thermal stress on precision circuits (such as ADC modules), ensuring the long-term reliability of data acquisition in high-current and high-density scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings forming a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0020] Figure 1 It is a hierarchical architecture diagram of the hardware-in-the-loop test system in Embodiment 1 of the present invention; Figure 2 It is a dynamic heat dissipation flow chart in Embodiment 1 of the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used in the present invention have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0021] Explanation of related terms: HIL: Hardware-in-the-Loop, a testing method that connects actual hardware (such as controllers, sensors, actuators, etc.) to a virtual simulation environment (simulated controlled object or external system) through real-time simulation technology.

[0022] ECU: Electronic Control Unit, an embedded hardware device used to monitor, process, and respond to input signals from sensors or other systems in real time, and drive actuators or external devices to complete specific functions through preset control algorithms or software logic.

[0023] EMC: Electromagnetic Compatibility, which is used to describe the ability of an electronic device or system to work properly in an electromagnetic environment and not interfere with other devices.

[0024] NFC: Near Field Communication, a popular short-range wireless communication method evolved from the integration of RFID and interconnection technologies.

[0025] LSTM: Long Short Term Memory, a special type of Recurrent Neural Network (RNN) designed to address the vanishing or exploding gradient problems faced by traditional RNNs when processing long sequences, thus effectively capturing long-term dependencies.

[0026] FPGA: Field-Programmable Gate Array, a semiconductor device with reprogrammable characteristics, widely used in digital circuit design, hardware acceleration, real-time control and other fields.

[0027] Example 1 The present invention provides a hardware-in-the-loop test system based on a modular hierarchical architecture, as Figure 1 shown. In this embodiment, the hardware-in-the-loop test system adopts a five-layer physical hierarchical architecture (L0-L4), specifically including the main control and communication layer L0, the drive layer L1, the computing layer L2, the signal layer L3, and the interface adaptation layer L4 in sequence. Among them, the drive layer L1 is a high-power drive layer, the computing layer L2 is a real-time computing layer, and the signal layer L3 is a precision signal layer. Through hierarchical functional isolation and dedicated interconnection design, high reliability, signal integrity, and system scalability are achieved. Core functional modules are independently deployed at each level, and cooperation between levels is realized through standardized interfaces and protocols. The specific hierarchical definitions are as follows: First is the main control and communication layer L0. As the core control and communication center of the system, the main control and communication layer is used to drive the drive layer. The main control and communication layer includes a PXIe chassis 1 and an upper industrial control computer 2. The upper industrial control computer 2 is connected to the PXIe chassis 1 via a network cable through the TCP / IP protocol. An embedded controller 3 and a vehicle multi-protocol interface module 4 are installed inside the PXIe chassis, working together to build a complete real-time control and communication architecture. In this embodiment, the upper industrial control computer 2 runs based on the Windows system, is equipped with an Intel(R) Core(TM) i7-8700 processor with 12 cores and a main frequency of 3.2 GHz, communicates with the embedded controller through the TCP / IP protocol, and integrates software such as Simulink and VeriStand to achieve visual monitoring of test tasks and algorithm deployment; the embedded controller 3 runs a real-time Linux system, relying on the PXIe hardware platform to achieve a task scheduling delay of less than 10 microseconds, and simultaneously executes the HIL simulation model and multi-protocol communication scheduling. The vehicle multi-protocol interface module 4, as the core communication node, supports hardware-level real-time communication of protocols such as CANFD and LIN, meeting the parallel processing requirements of hundreds of PLC channels.

[0028] In this embodiment, the main control and communication layer L0 realizes multi-level collaboration through vertical protocol control and horizontal bus expansion, directly drives the high-power drive layer based on the CAN protocol, completes instruction issuance and real-time status feedback, and at the same time is highly interconnected with the computing layer L2 and other signal processing layers (signal layer L3 and interface adaptation layer L4) through the PCIeGen4×16 bus with a transmission delay of less than 100 nanoseconds, supporting a two-way data throughput rate of up to 32 GB / s, meeting the high real-time control and complex signal interaction requirements in the intelligent network connection scenario.

[0029] Next is the drive layer L1. The drive layer is for direct drive of high-power devices and overall power management. The drive layer includes a PDU power distribution unit 5, a TDK-Lambda power supply 6, and a relay matrix module 7, building an energy control architecture with a millisecond-level response. Among them, the TDK-Lambda power supply 6 is directly controlled by the main control and communication layer L0, realizes dynamic voltage and current regulation through the Modbus-TCP protocol, is used to provide low-ripple power supply, with a voltage fluctuation suppression ratio better than 0.1% and a transient response time ≤ 5 ms; the PDU power distribution unit 5 integrates multi-channel isolation circuits and intelligent fuse protection, supports remote power path reconstruction, and is used for power distribution and management; the relay matrix module 7 responds to the trigger signal from the main control and communication layer through the CAN protocol, accurately controls the on / off of 6 power supply channels from the TDK-Lambda power supply 6, and supports independent or grouped free regulation.

[0030] Then there is the computing layer L2. As the core computing center of the system, the computing layer includes a high-performance FPGA module composed of dual PXIe-7856R boards, which constructs a high-precision real-time signal processing architecture. The simulation and acquisition processing programs for engine synchronization, fuel injection, ignition timing, PWM modulation, SENT signal parsing, and knock vibration feature analysis are embedded in the FPGA module. Each FPGA board supports a main frequency of 2.5 GHz and 1080k logic unit resources, and realizes nanosecond-level (≤10ns) synchronous processing of 48 parallel signal channels through GTY high-speed transceivers. The computing layer L3 establishes a 16GB / s bidirectional communication link with the drive layer through the PCIe Gen4×8 bus, with a synchronous trigger error of less than ±50ns, and transmits calibration parameters, operating condition data, and fault codes to the signal layer L3 through the time-sensitive network (TSN) to ensure a hard real-time closed-loop link from signal generation, logical decision-making to execution control.

[0031] Then there is the signal layer L3. The signal layer L3 is for the full-link closed-loop control of high-precision signals. It realizes the acquisition, conditioning, and output of dense signals through a hybrid architecture to ensure the accuracy and stability of the test signals and provide a precise test environment for the ECU13 under test in extreme operating conditions. The signal layer includes a fault injection module 9, a PXIe analog output and acquisition module 10, a PXIe digital output and acquisition module 11, a resistance simulation module 12, the ECU13 under test, an ECU calibration computer 14, and a load drawer 15. The signal layer L3 can inject faults independently for each channel, has a programmable resistance network of 20Ω - 2MΩ, and high-precision digital and analog signal simulation and acquisition. The ECU13 under test interacts with the ECU calibration computer 14 in real time through the Ethernet protocol to achieve dynamic refreshing of calibration parameters and high-speed transmission of test data, ensuring seamless connection between the test process and engineering iteration. And the signal layer L3 realizes an internal data throughput of 128GB / s through a high-speed backplane, and dynamically reconstructs the sensor model and load characteristics based on the hardware-in-the-loop test framework, and finally realizes high-precision calibration and stable operation of the full signal link. And the signal layer is electrically connected to the interface adaptation layer.

[0032] Finally, there is the interface adaptation layer L4. The interface adaptation layer L4 focuses on multi-protocol interface adaptation, heterogeneous signal conversion, and electrical characteristic standardization conditioning to ensure the integrity and compatibility of cross-module signal transmission. The interface adaptation layer and the signal layer L3 are connected by physical hardwiring. The L4 interface adaptation layer includes a TIF harness connector 16, a digital signal conditioning module 17, an analog signal conditioning module 18, and a current-voltage conversion module 19; the TIF harness connector 16 supports physical layer multi-topology adaptive matching and signal pin dynamic redefinition; the digital signal conditioning module 17 and the analog signal conditioning module 18 respectively achieve intelligent signal scaling through dynamic gain control and high-linearity amplification links, complete accurate digital level matching and analog range adaptive expansion, and ensure intensity adaptation of various signals within the system compatibility range; among them, the signals that need to be conditioned are sent from the signal layer L3, first pass through the digital signal conditioning module or the analog signal conditioning module, and then are output through the TIF harness connector 16, and the signals that do not need to be conditioned are directly sent from the signal layer L3 to the TIF harness connector 16.

[0033] The current-voltage conversion module 19 can achieve high-precision, wide-range, and strong anti-interference current-voltage distortion-free conversion. Each module collaborates to build a multi-modal signal intelligent adaptation system to achieve precise regulation of signal intensity within the global dynamic range and system-level distortion-free compatibility.

[0034] In this embodiment, a multi-modal filtering technology is also proposed. Combining the above five-layer physical hierarchical architecture, a global electromagnetic interference collaborative governance system is constructed, significantly improving the electromagnetic compatibility performance in the mixed scenario of high and low power modules. At the physical architecture level, differential shielding isolation is implemented according to the functional characteristics of different levels: a double-layer composite shielding structure is adopted between the main control layer, the communication layer, and the drive layer. Among them, the inner layer is a high-permeability metal shielding cavity, and the outer layer combines conductive gaskets and absorbing materials to form a wide-band radiation noise attenuation mechanism; an orthogonal star-shaped grounding system is deployed between the computing layer and the signal layer, and the inter-layer common-mode noise conduction is suppressed through a single-point grounding topology. The traditional star-shaped grounding system is a known technology, and its core idea is to converge the grounding paths of multiple modules to a central grounding point through single-point grounding, thereby reducing ground loop interference and common-mode noise. However, it has limitations in high-frequency and high-power mixed scenarios.

[0035] The orthogonal star-shaped grounding system combines orthogonal wiring with a star-shaped grounding topology. By arranging the grounding paths of different layers orthogonally, the inter-layer electric / magnetic field coupling is reduced. Connecting to the central grounding point through orthogonal isolation paths between functional layers can effectively suppress inter-layer common-mode noise conduction and avoid cross-layer ground loop interference.

[0036] In this embodiment, the signal transmission path adopts adaptive filtering technology. Between the main control and the communication layer and the drive layer, the bus integrates magnetic isolation drive and a multi-stage LC filter network to enhance the common-mode noise suppression ability. The multi-stage LC filter network is a filtering technology achieved through the cascaded combination of multi-stage LC circuits, aiming to suppress high-frequency noise in the bus signal in multiple frequency bands and at multiple levels. Its core is to significantly improve electromagnetic compatibility through the collaborative design of inductors and capacitors, combined with magnetic isolation drive technology. The multi-stage LC filter network includes two levels of LC filter units: the first level consists of a low-inductance inductor (L1) and a high-capacitance capacitor (C) to form a wide-band pre-filter to suppress high-frequency noise; the second level consists of a high-inductance inductor (L2) and a low-capacitance capacitor (C2) to form a narrow-band filter for specific resonant frequencies (such as the harmonics of the switching devices in the drive layer). The topological structure is: Signal input → L1 → C1 → L2 → C2 → Signal output.

[0037] The signal layer deploys a dynamic compensation filter architecture, combining pre-stage low-pass filtering, common-mode suppression amplification, and programmable frequency notch technology. It should be noted that low-pass filtering, common-mode suppression amplification, and programmable frequency notch all use existing modules. Specifically: the model of the low-pass filter module is LTC1562, the model of the common-mode suppression amplification module is AD8421, and the model of the programmable notch module is ADAU1701. In this embodiment, integration is carried out to achieve full-link interference cancellation.

[0038] The interface adaptation layer enhances compatibility through heterogeneous signal isolation. For digital signals, multi-layer shielded cables and impedance-matching terminals are used to reduce return loss. For analog signal channels, a high-impedance isolation amplifier and a protection drive module are integrated. Both the high-impedance isolation amplifier and the protection drive module are existing modules. Specifically: the model of the high-impedance isolation amplifier is ADAU3190, and the model of the protection drive module is CN0503. The power supply line adopts a combination of a composite filter network and transient suppression devices to effectively control conducted noise.

[0039] In this embodiment, the dynamic thermal management problem of the high-power hardware-in-the-loop test system is effectively solved. In this embodiment, a temperature sensor array, a variable-speed vortex fan air-cooling system, and a gradient heat pipe array are set in the drive layer. Specifically: on the surfaces of the IGBT and MOSFET devices in the drive layer L1, a PT1000 thin-film temperature sensor array is integrated to collect junction temperature data in real time with a resolution of 0.1 °C. Based on the junction temperature data, a heat flow distribution model from the device layer to the heat dissipation substrate is established based on the three-dimensional unsteady heat conduction equation: ; where is the temperature field distribution (°C), is the time variable (s), = , expressed as the thermal diffusivity (m² / s), is calibrated through experiments. is the heat generation rate per unit volume (W / m³), which is dynamically calculated based on the switching losses of the power device. is the thermal conductivity of the material (W / m·K), which is assigned according to the material characteristics of the heat dissipation substrate.

[0040] Such as Figure 2 As shown, the variable speed centrifugal fan air-cooling system is configured with a centrifugal fan driven by a brushless DC motor, and achieves wide-range speed regulation from 500 to 4500 rpm according to the temperature rise gradient ΔT. Specifically: when the temperature exceeds the set threshold (40°C), the proportional-integral speed regulation algorithm is started, and the wind speed satisfies: ; where is the fan speed, is the time variable, is the temperature difference between the set temperature and the actual temperature, 、 is dynamically optimized according to the thermal resistance characteristics of the radiator. In the proportional-integral speed regulation algorithm, (proportional gain) and (integral gain) are the core parameters of the control system, which directly affect the dynamic response and steady-state performance of speed regulation. is the immediate response to the current error, which determines the response intensity of the controller to the current error (the difference between the set value and the actual value). The greater the error, the greater the control quantity (such as voltage, force, flow rate, etc.) output by the proportional term.

[0041] is the cumulative compensation for historical errors, which determines the compensation intensity of the controller for the cumulative amount of errors over time. The integral term gradually eliminates the static error that cannot be solved by proportional control by continuously accumulating historical errors.

[0042] The gradient heat pipe array is composed of three groups of heterogeneous heat pipes, divided into a high-temperature section, a medium-temperature section, and a low-temperature section. The high-temperature section uses copper-water heat pipes to achieve axial heat conduction of 400 W / m·K. The medium-temperature section and the low-temperature section are deployed with a composite capillary structure of aluminum-acetone heat pipes and sintered copper powder, and the radial heat dissipation efficiency is enhanced through the gas-liquid phase change of the phase change material. Its maximum heat transfer power is determined by the capillary limit equation: ; where is the maximum heat transfer power of the heat pipe, is the pore diameter of the capillary structure, is the density of the working fluid liquid, is the latent heat of vaporization of the working fluid, is the surface tension coefficient, is the viscosity of the liquid working fluid, is the equivalent length of the heat pipe.

[0043] The intelligent temperature control strategy adopts the fuzzy PID algorithm, taking the junction temperature deviation ΔT and the change rate dT / dt as input parameters, and dynamically adjusts the fan speed and the heat pipe operating mode: when ΔT > 10°C, the secondary phase change of the heat pipe is activated to enhance heat transfer, and the radial fin heat dissipation power is increased; when dT / dt ( )> 2°C / s, the fan overclocking mode is triggered, and the speed is instantly increased to 120% of the rated value. The system implements three-level temperature protection: an audible and visual warning is triggered at 70°C and the heat dissipation power is enhanced, power device derating control is started at 85°C, and global shutdown is executed at 95°C. The thermal management strategy realizes data interconnection with the host computer through the PCIe bus, uses a long short-term memory neural network to perform a time series modeling on the historical temperature rise curve and the operating condition characteristics, generates a dynamic thermal load prediction function and feeds it back to the heat dissipation controller. The heat dissipation controller is a program running in the upper industrial control computer 2, and the overall thermal management control of the device is executed by this program, realizing adaptive thermal optimization based on feedforward-feedback composite control.

[0044] In this embodiment, a modular mechanical design is adopted to balance the rigidity and agility of the test system, as follows: The system is equipped with a slide rail type quick-release structure. The module units (relay matrix module 7, resistor simulation module 12, digital signal conditioning module 17, analog signal conditioning module 18, current-voltage conversion module 19) are quickly disassembled and assembled through pre-guided slide rails and self-locking mechanisms. The insertion operation force is less than 5N and supports module replacement in the powered state; standardized electrical interfaces and PT quick connection terminals are adopted between modules, integrated with anti-misinsertion guide grooves and self-cleaning contacts, realizing tool-free plugging and unplugging operations and highly reliable electrical connections; the PXIe board card wiring station and the external shapes of each conditioning module adopt a unified packaging size, and the internal components are optimized in space according to the thermodynamic distribution, and the stack density and maintenance convenience are improved with the help of an expandable slot frame; the safety protection system sets multiple interlock mechanisms, including an automatic power-off protection circuit and a physical isolation barrier in the powered state, and the high-voltage circuit is cut off in real time during the module plugging and unplugging process. The overall design significantly improves the system maintenance convenience, connection reliability and environmental adaptability.

[0045] In this embodiment, the slide rail type quick-release architecture and the standardized interface design reconstruct the maintainability logic of the HIL test system. The module replacement efficiency is increased to "second-level operation" (90 seconds / time), and the operation safety is ensured through anti-misinsertion and self-locking designs. The high-density stacking layout breaks through the space limitation of the traditional architecture, supports the flexible expansion of vehicle-mounted electronic system testing, and significantly reduces the deployment cost and time cost in complex scenarios.

[0046] This embodiment adopts NFC electronic tag technology that complies with the ISO14443-A standard. By solidifying the full life cycle data such as module serial number, calibration parameters, maintenance records and fault history in the tag storage area, the physical entity and digital information are permanently bound. The NFC tag configured for each module (except the ECU 13 under test and the calibration computer 14, all other modules that constitute the physical layered architecture can be configured with NFC tags to record their information) adopts a 13.56MHz radio frequency communication protocol, supports smart phones or dedicated readers and writers to interact with data within a 5cm near field range, and the tag has a built-in encryption engine to ensure the security of sensitive information storage. During the operation and maintenance process, the operator obtains key parameters such as the cumulative operating time and performance decay curve of the module in real time through near-field scanning, and after synchronization to the background database, the LSTM time series prediction engine performs degradation modeling to generate a remaining service life prediction and maintenance priority assessment report. When the prediction result triggers the preset maintenance threshold, the system automatically generates a work order instruction and pushes it to the maintenance terminal, and updates the health status identification in the electronic tag at the same time, completing the closed-loop control link from data collection, status diagnosis, life prediction to maintenance response, and effectively eliminating the decision-making delay caused by information islands in the traditional maintenance process.

[0047] In this embodiment, the maintenance system based on NFC electronic tags and LSTM prediction models realizes accurate tracking and predictive maintenance of the module health status. The system can predict potential failures in advance (prediction accuracy ≥ 80%), greatly reduce unplanned downtime, and realize accurate scheduling of maintenance resources through intelligent diagnosis. The maintenance decision response speed is improved to seconds, and the operation and maintenance cost is reduced by more than half compared with the traditional model, providing technical guarantee for the sustainable operation of large-scale test platforms.

[0048] Embodiment 2 This embodiment provides a hardware-in-the-loop testing method based on a modular layered architecture, and a hardware-in-the-loop testing system based on a modular layered architecture provided in Embodiment 1, including: The main control and communication layers synchronously control the modules of the drive layer, signal layer, and interface adapter layer through the bus. The computing layer performs simulation operations based on the embedded program of the FPGA module, generates a set of dynamic working condition parameters, and transmits them to the signal layer with the help of time-sensitive network (TSN). After receiving the parameters, the signal layer generates the excitation signal required for the closed-loop test, and at the same time ensures the timing accuracy of signal injection through the signal integrity verification algorithm, thereby simulating the real working condition environment to the ECU under test. The ECU under test realizes real-time data interaction with the ECU calibration computer through the Ethernet protocol.

[0049] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A hardware-in-the-loop test system based on a modular hierarchical architecture, characterized in that Including: Physical hierarchical architecture; The physical hierarchical architecture successively includes a main control and communication layer, a drive layer, a computing layer, a signal layer, and an interface adaptation layer; The main control and communication layer is used to drive the drive layer, and the drive layer is provided with a temperature sensor array, a variable-speed vortex fan air-cooling system, and a gradient heat pipe array; A double-layer composite shielding structure is adopted between the main control and communication layer and the drive layer, and a magnetic isolation drive and a multi-stage LC filter network are integrated. The main control and communication layer is interconnected with the computing layer, the signal layer, and the interface adaptation layer through a bus; A bidirectional communication link is established between the drive layer and the computing layer, and the computing layer also realizes data transmission with the signal layer through a time-sensitive network, and an orthogonal star-shaped grounding system is deployed between the computing layer and the signal layer; The signal layer deploys a dynamic compensation filtering architecture, and the signal layer is electrically connected to the interface adaptation layer.

2. The hardware-in-the-loop test system based on a modular hierarchical architecture according to claim 1, characterized in that, The main control and communication layer drives the drive layer based on the CAN protocol. The main control and communication layer includes a chassis and an upper industrial control computer. A controller and a vehicle-mounted multi-protocol interface module are installed inside the chassis; Wherein the upper industrial control computer communicates with the controller through the TCP / IP protocol.

3. A hardware-in-the-loop test system based on a modular hierarchical architecture according to claim 1, characterized in that The drive layer includes a power distribution unit, a power supply, and a relay matrix module; wherein the power distribution unit is used for power distribution and management, and the relay matrix module responds to the trigger signal of the main control and communication layer through the CAN protocol and controls the on / off of the power supply channel from the power supply.

4. A hardware-in-the-loop test system based on a modular hierarchical architecture according to claim 1, characterized in that The computing layer includes an FPGA module, and simulation and acquisition processing programs for engine synchronization, fuel injection, ignition timing, PWM modulation, SENT signal parsing, and knock vibration characteristic analysis are embedded in the FPGA module.

5. A hardware-in-the-loop test system based on a modular hierarchical architecture according to claim 1, characterized in that, The signal layer includes a fault injection module, an analog output and acquisition module, a digital output and acquisition module, a resistance simulation module, a to-be-tested ECU, an ECU calibration computer, and a load drawer; Wherein the to-be-tested ECU interacts with the ECU calibration computer in real time through the Ethernet protocol, and the signal layer realizes its internal data throughput through a high-speed backplane.

6. The hardware-in-the-loop test system based on a modular hierarchical architecture according to claim 1, characterized in that The interface adaptation layer includes a wire harness connector, a digital signal conditioning module, an analog signal conditioning module, and a current-voltage conversion module; wherein, the digital signal conditioning module and the analog signal conditioning module respectively realize signal scaling through a dynamic gain control and a high-linearity amplification link.

7. A hardware-in-the-loop test system based on a modular hierarchical architecture according to claim 1, characterized in that, The temperature sensor array is used to collect junction temperature data. According to the junction temperature data, a heat flow distribution model is established based on the three-dimensional unsteady heat conduction equation, specifically: ; wherein, is the temperature field distribution, is the time variable, = , expressed as the thermal diffusivity, is the heat generation rate per unit volume, is the thermal conductivity of the material.

8. A hardware-in-the-loop test system based on a modular hierarchical architecture as claimed in claim 1, characterized in that The variable-speed vortex fan air-cooling system is configured with a centrifugal vortex fan driven by a brushless DC motor, and wide-range speed regulation is realized according to the temperature rise gradient. Specifically: when the temperature exceeds the set threshold, a proportional-integral speed regulation algorithm is started, and the wind speed satisfies: ; wherein, is the fan speed, is the time variable, is the temperature difference between the set temperature and the actual temperature.

9. A hardware-in-the-loop test system based on a modular hierarchical architecture according to claim 1, characterized in that, The gradient heat pipe array is composed of three groups of heterogeneous heat pipes, which are divided into a high-temperature section, a medium-temperature section, and a low-temperature section. The high-temperature section adopts a copper-water heat pipe, and the medium-temperature section and the low-temperature section deploy an aluminum-acetone heat pipe and a sintered copper powder composite capillary structure. The radial heat dissipation efficiency is enhanced through the gas-liquid phase change of the phase change material, and its maximum heat transfer power is determined by the capillary limit equation: ; wherein, is the maximum heat transfer power of the heat pipe, is the pore diameter of the capillary structure, is the density of the working fluid liquid, is the latent heat of vaporization of the working fluid, is the surface tension coefficient, is the viscosity of the liquid working fluid, is the equivalent length of the heat pipe.

10. A hardware-in-the-loop test method based on a modular hierarchical architecture, based on the hardware-in-the-loop test system according to any one of claims 1-9, characterized in that, Including: After receiving the instructions from the main control and communication layer through the bus, the computing layer performs simulations based on the programs embedded in the FPGA module to obtain calibration parameters, operating condition data, and fault codes, and transmits them to the signal layer through the time-sensitive network; based on the received calibration parameters, operating condition data, and fault codes, the signal layer injects test signals into the ECU under test to simulate the actual operating conditions. The ECU under test interacts with the ECU calibration computer in real time through the Ethernet protocol.

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