Data writing method and device, electronic equipment and storage medium
The storage fragmentation problem is solved by splitting and allocating continuous physical block addresses when the processor detects a write command, and data reading efficiency and user experience are improved.
Patent Information
- Application Number
- CN202410023961.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-05
- Publication Date
- 2025-07-08
Smart Images
Figure CN120276660A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of communications, and in particular, to a data writing method, apparatus, electronic device, and storage medium. Background Art
[0002] Storage fragmentation, also known as file fragmentation, is formed because files are scattered and saved in different places of the entire memory instead of being saved in consecutive physical block addresses of the memory.
[0003] A common scenario for the generation of storage fragmentation is that when a user initiates multiple write operations and multiple processes are running simultaneously, since the system may alternately schedule the write commands of multiple write operations to the memory, and the memory processes them in sequence, resulting in storage fragmentation. Storage fragmentation will lead to a reduction in the sequential read performance of files, making the user waiting time longer, thus affecting the user experience. Summary of the Invention
[0004] The present disclosure provides a data writing method, apparatus, electronic device, and storage medium to overcome the problem of generating storage fragmentation during memory writing.
[0005] According to a first aspect of an embodiment of the present disclosure, a data writing method is provided, including:
[0006] When the processor detects at least one write command for a storage interface, determining the storage space indicated by the write command; wherein the write command has a command identifier;
[0007] Splitting the write command into a preset number of sub-commands and sending them to the memory; wherein each of the sub-commands has the command identifier;
[0008] The memory determines the first received sub-command among the multiple sub-commands corresponding to the same write command as the target sub-command;
[0009] Based on the command identifier of the target sub-command, allocating a consecutive physical block address corresponding to the storage space for the write command in the memory, and writing the data to be written indicated by the target sub-command in the consecutive physical block address.
[0010] In some embodiments, the data writing method further includes:
[0011] When the received sub-command is a non-target sub-command, the memory determines the write command to which the non-target sub-command belongs and the consecutive physical block address corresponding to the write command based on the command identifier of the non-target sub-command;
[0012] Writing the data to be written of the non-target sub-command to the consecutive physical block address corresponding to the write command.
[0013] In some embodiments, the data writing method further includes:
[0014] When it is determined that the write command has been successfully executed, the processor obtains the consecutive physical block addresses corresponding to the successfully executed write command;
[0015] The processor establishes a mapping relationship between the consecutive physical block addresses and the corresponding consecutive logical block addresses, and updates the address mapping table based on the mapping relationship;
[0016] Wherein, the address mapping table is used to store the consecutive physical block addresses corresponding to the data to be written indicated by the write command and the corresponding consecutive logical block addresses.
[0017] In some embodiments, the data writing method further includes:
[0018] Based on the storage space indicated by the write command, the processor allocates corresponding consecutive logical block addresses for the write command;
[0019] The processor establishes an address mapping table based on the data to be written indicated by the write command and the consecutive logical block addresses.
[0020] In some embodiments, the data writing method further includes:
[0021] When the processor receives at least one read command for the storage interface, based on the data to be read indicated by the read command, the consecutive logical block addresses of the data to be read are determined from the address mapping table;
[0022] Based on the consecutive logical block addresses, the corresponding consecutive physical block addresses are determined from the address mapping table;
[0023] Based on the consecutive physical block addresses, the memory reads the data to be read indicated by the read command.
[0024] In some embodiments, splitting the write command into a preset number of sub-commands and sending them to the memory includes:
[0025] Based on the storage space indicated by the write command and the minimum storage space that the memory can be operated on, the write command is split into a preset number of sub-commands; wherein, the sub-storage spaces indicated by each sub-command are less than or equal to the minimum storage space that the memory can be operated on;
[0026] Sending the sub-commands to the memory.
[0027] In some embodiments, the types of the write command include at least one of the following:
[0028] SCSI write command;
[0029] SATA write command;
[0030] SAS write command
[0031] PCIE write command.
[0032] According to a second aspect of embodiments of the present disclosure, a data writing device is provided, including:
[0033] A processor configured to determine the storage space indicated by the write command when detecting at least one write command for a storage interface; wherein, the write command has a command identifier; split the write command into a preset number of sub-commands and send them to the memory; wherein each of the sub-commands has the command identifier;
[0034] A memory configured to determine, among multiple sub-commands corresponding to the same write command, the first received sub-command as the target sub-command; based on the command identifier of the target sub-command, allocate a continuous physical block address corresponding to the storage space for the write command, and write the data to be written indicated by the target sub-command in the continuous physical block address.
[0035] In some embodiments, the memory is further configured to:
[0036] When the received sub-command is a non-target sub-command, determine the write command to which the non-target sub-command belongs and the continuous physical block address corresponding to the write command based on the command identifier of the non-target sub-command;
[0037] Write the data to be written of the non-target sub-command in the continuous physical block address corresponding to the write command.
[0038] In some embodiments, the processor is further configured to:
[0039] When it is determined that the write command is successfully executed, obtain the continuous physical block address corresponding to the successfully executed write command;
[0040] Establish a mapping relationship between the continuous physical block address and the corresponding continuous logical block address, and update the address mapping table based on the mapping relationship;
[0041] Wherein, the address mapping table is used to store the continuous physical block address corresponding to the data to be written indicated by the write command and the corresponding continuous logical block address.
[0042] In some embodiments, the processor is further configured to:
[0043] Allocate a corresponding consecutive logical block address for the write command based on the storage space indicated by the write command;
[0044] Establish an address mapping table based on the data to be written indicated by the write command and the consecutive logical block address.
[0045] In some embodiments, the processor is further configured to:
[0046] When receiving at least one read command for the storage interface, determine the consecutive logical block address of the data to be read from the address mapping table based on the data to be read indicated by the read command;
[0047] Determine the corresponding consecutive physical block address from the address mapping table based on the consecutive logical block address;
[0048] The memory is further configured to:
[0049] Read the data to be read indicated by the read command based on the consecutive physical block address.
[0050] In some embodiments, the processor is further configured to:
[0051] Split the write command into a preset number of sub-commands based on the storage space indicated by the write command and the minimum storage space that the memory can be operated on; wherein, the sub-storage space indicated by each sub-command is less than or equal to the minimum storage space that the memory can be operated on;
[0052] Send the sub-commands to the memory.
[0053] In some embodiments, the types of write commands include at least one of the following:
[0054] SCSI write command;
[0055] SATA write command;
[0056] SAS write command
[0057] PCIE write command.
[0058] According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device, including:
[0059] A processor;
[0060] A memory configured to store executable instructions of the processor;
[0061] Wherein, the processor is configured to be able to execute the data writing method described in the first aspect above when calling the executable instructions in the memory.
[0062] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the data writing method described in the first aspect above.
[0063] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:
[0064] In the data writing method of the present disclosure, when the processor detects at least one write command for the storage interface, it determines the storage space indicated by the write command. The processor splits the write command into a preset number of sub-commands and sends them to the memory. Each sub-command has a command identifier corresponding to the write command. During the process of processing the received multiple sub-commands, the memory determines the first received sub-command among the multiple sub-commands corresponding to the same write command as the target sub-command. Based on the command identifier of the target sub-command, it allocates a continuous physical block address corresponding to the storage space for the write command to which the target sub-command belongs, and writes the data to be written indicated by the target sub-command in the allocated continuous physical block address. In this way, for multiple sub-commands of the same write command, by allocating a continuous physical block address corresponding to the storage space of the write command when the target sub-command is received and reserving continuous physical block addresses for non-target sub-commands, it avoids write fragmentation caused by the alternating writing of multiple sub-commands belonging to different write commands.
[0065] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0066] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.
[0067] Figure 1 is a flowchart illustration of a data writing method shown according to an exemplary embodiment Figure 1 .
[0068] Figure 2 is a flowchart illustration of a data writing method shown according to an exemplary embodiment Figure 2 .
[0069] Figure 3 is a flowchart illustration of a data writing method shown according to an exemplary embodiment Figure 3 .
[0070] Figure 4 is a schematic diagram of the process of the processor and the memory interacting to complete data writing shown according to an exemplary embodiment.
[0071] Figure 5It is a schematic structural diagram of a data writing device shown according to an exemplary embodiment.
[0072] Figure 6 It is a schematic structural diagram of an electronic device shown according to an exemplary embodiment. Detailed implementation manners
[0073] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0074] In the specification, unless otherwise clearly stated, the terms "first" and "second" are only used for description to distinguish constituent elements and should not be construed as indicating an order. Unless otherwise clearly stated, terms such as "connected" and "fixed" should be understood in a broad sense, including but not limited to "connected" and "fixed" directly, indirectly, detachably, etc.
[0075] Common scenarios for the generation of storage fragmentation are that the user initiates multiple write operations and multiple processes are running simultaneously. For example, during the process of the user downloading a movie (Process 1), other events such as creating a new Excel file (Process 2) and downloading a game APP (Process 3) may also occur. The files generated by these processes may be split into multiple small files, especially large files such as movie downloads and APP downloads. And multiple small files corresponding to the same process may be written to different places in the memory during the multi-process scheduling process, resulting in the generation of storage fragmentation. For example, the file data generated by Process 1 is split into 5 sub-file data, and the file data generated by Process 2 is split into 3 sub-file data. When writing the 5 sub-file data of Process 1 to the memory, the sub-file data of Process 2 may be mixed and written. Due to the interleaved writing of various data of different processes, the sub-file data of the same process is not continuously written to the storage space, that is, storage fragmentation.
[0076] When the memory needs to read data, it is necessary to obtain the physical block address corresponding to the logical block address of the data, and then read the data based on the physical block address. If the data is scattered and stored in different places in the memory, that is, physically discontinuous, it is necessary to read multiple times to obtain the complete data, resulting in the "lag" problem of the electronic device, and further making the waiting time of the user in multiple usage scenarios such as application cold start and file loading longer, affecting the usage fluency.
[0077] Based on this, when the present disclosure receives a target sub-command, it allocates a continuous physical block address corresponding to the storage space of the write command for it, which is equivalent to reserving a continuous physical block address for non-target sub-commands, thereby avoiding write fragmentation caused by multiple sub-commands belonging to different write commands during the alternating writing process.
[0078] Figure 1 is a flowchart of a data writing method shown according to an exemplary embodiment Figure 1 , such as Figure 1 shown, the method mainly includes the following steps:
[0079] In step 101, when the processor detects at least one write command for the storage interface, determine the storage space indicated by the write command; wherein the write command has a command identifier.
[0080] In this embodiment, the storage interface can be any one of an ATA (AT Attachment) interface, a SATA interface, a SCSI (Small Computer System Interface) interface, a SAS (Serial Attached SCSI) interface, a PCIE interface, etc. Among them, ATA is a specific interface standard for IDE (Integrated Drive Electronics) hard disks, and SCSI (Small Computer System Interface) is a storage unit interface mode specially designed for small computer systems. SAS is Serial Attached SCSI, which improves the performance of the storage system and is suitable for high-end server storage systems.
[0081] Corresponding to different storage interfaces, the type of the write command can be any one of a SCSI write command, an ATA write command, a SATA write command, a SAS write command, a PCIE write command. Once the processor detects at least one write command for the storage interface triggered by various user write operations (such as: downloading movies, batch storing pictures, etc.), it determines the storage space required for each write command. In addition, each write command includes a command identifier and data to be written.
[0082] In step 102, split the write command into a preset number of sub-commands and send them to the memory; wherein each sub-command has a command identifier.
[0083] In this embodiment, at least one write command detected by the processor for the storage interface does not directly operate on the memory, but rather requires a relatively long IO stack to complete the data write. During this process, the processor needs to split the write command into sub-commands that can directly operate on the memory. The preset number of splits can be determined based on the storage space occupied by the write command and the minimum storage space that the memory can be operated on.
[0084] Send the multiple sub-commands obtained by splitting to the memory. Since each write command has its own corresponding command identifier, the multiple sub-commands after splitting also have the command identifier of the write command to which they belong. Additionally, the sub-commands can also include the storage space information of the write command to which they belong, so as to allocate physical block addresses by the memory subsequently. Of course, when splitting the write command, in essence, the data to be written in the write command is also split, and the result of the split is that the data to be written indicated by each sub-command is a part of the data to be written indicated by the write command.
[0085] It should be noted that when the user initiates a read / write operation, it does not directly operate on the memory (device side), but rather the read / write operation passes through the file system, block layer, and device driver layer in sequence in the processor (host side), and finally reaches the memory (device side). After the memory finishes processing, it sends an interrupt to notify the processor (host side). Among them, the memory (device side) includes a storage controller (Controller) and a storage space (NAND).
[0086] In step 103, the memory determines the first received sub-command among the multiple sub-commands corresponding to the same write command as the target sub-command.
[0087] In this embodiment, the processor schedules the multiple sub-commands to the memory in sequence according to a preset IO scheduling algorithm. For the received sub-commands, the memory determines whether they are the first received sub-commands among the multiple sub-commands of the write command to which they belong, and determines the first received sub-command among the multiple sub-commands of the write command to which they belong as the target sub-command.
[0088] Among them, the determination of the target sub-command can be based on the command identifier of the sub-command, that is, it is judged whether a sub-command corresponding to the same command identifier has been received before the currently received sub-command. If it has been received, the currently received sub-command is a non-target sub-command. If it has not been received, the currently received sub-command is a target sub-command. That is to say, the multiple sub-commands included in a write command are logically divided into target sub-commands and non-target sub-commands. A write command includes only one target sub-command, but includes multiple non-target sub-commands.
[0089] In step 104, based on the command identifier of the target sub-command, the memory allocates a continuous physical block address corresponding to the storage space for the write command, and writes the data to be written of the target sub-command in the continuous physical block address.
[0090] In this embodiment, since one command identifier corresponds to one write command and the storage space indicated by one write command is unique, the write command to which the target sub-command belongs and the storage space required by the write command to which the target sub-command belongs can be determined through the command identifier. Therefore, when the memory determines that the received sub-command is a target sub-command, based on the command identifier, a continuous physical block address corresponding to the storage space of the write command to which the target sub-command belongs is allocated for the write command to which the target sub-command belongs. At this time, it can be understood that the command identifier also corresponds to the allocated continuous physical block address.
[0091] After the continuous physical block address is allocated, the memory writes the data to be written indicated by the target sub-command in the continuous physical block address. It can be understood that at this time, the continuous physical block address is not fully used, and the unused address is equivalent to reserving storage space in advance for non-target sub-commands (other sub-commands belonging to the same write command as the target sub-command). In this way, it can be ensured that the data to be written corresponding to all sub-commands of the same write command is continuously stored.
[0092] In some embodiments, as Figure 2 shown, the data writing method further includes:
[0093] In step 205, when the received sub-command is a non-target sub-command, the memory determines the write command to which the non-target sub-command belongs and the continuous physical block address corresponding to the write command based on the command identifier of the non-target sub-command;
[0094] In step 206, the data to be written of the non-target sub-command is written to the continuous physical block address corresponding to the write command.
[0095] In this embodiment, for the received sub-command, it can be determined whether the sub-command is a non-target sub-command based on the command identifier of the sub-command. A non-target sub-command is a sub-command that is not the first received among multiple sub-commands of the belonging write command. For a non-target sub-command, the continuous physical block address corresponding to the belonging write command can be determined based on the command identifier, and at this time, the data to be written of the non-target sub-command can be directly written in this continuous physical block address.
[0096] That is to say, the allocation of the physical block address is only for the target sub-command, and the non-target sub-command can directly store data in the continuous physical block address corresponding to the command identifier.
[0097] In one embodiment, as Figure 3 shown, the data writing method further includes:
[0098] In step 305, when it is determined that the write command has been successfully executed, the processor obtains the consecutive physical block addresses corresponding to the successfully executed write command;
[0099] In step 306, the processor establishes a mapping relationship between the consecutive physical block addresses and the corresponding consecutive logical block addresses, and updates the address mapping table based on the mapping relationship; wherein, the address mapping table is used to store the consecutive physical block addresses and the corresponding consecutive logical block addresses corresponding to the data to be written indicated by the write command.
[0100] In this embodiment, after the memory successfully executes the write command, it sends an interrupt to notify the processor. When the processor determines that the write command has been successfully executed, it obtains the consecutive physical block addresses of the write command, establishes a mapping relationship between the consecutive physical block addresses and the consecutive logical block addresses corresponding to the write command, and updates the address mapping table based on the established mapping relationship. The updated address mapping table stores the data to be written corresponding to the write command, the corresponding consecutive logical block addresses, and the corresponding consecutive physical block addresses, which correspond to each other one by one, facilitating subsequent data reading.
[0101] In one embodiment, the data writing method further includes: based on the storage space indicated by the write command, the processor allocates corresponding consecutive logical block addresses for the write command; the processor establishes an address mapping table based on the data to be written indicated by the write command and the consecutive logical block addresses.
[0102] In this embodiment, based on the storage space required by the write command, the file system in the processor core allocates corresponding consecutive logical block addresses for the write command, so as to ensure that while the physical block addresses are consecutive, the logical block addresses are also consecutive, improving the performance of sequential data reading.
[0103] It can be understood that if the logical block addresses are consecutive, the processor only needs to send one read command when reading data. If the logical block addresses are not consecutive, that is, there are logical fragments, the processor needs to send multiple read commands based on the number of logical fragments when reading data, greatly increasing the processing burden on the processor and the memory, and affecting the user experience.
[0104] After the file system in the processor core allocates consecutive logical block addresses for the write command, the processor establishes an address mapping table based on the data to be written of the write command and the corresponding consecutive logical block addresses, facilitating the management of the data in the memory and also facilitating subsequent fast data reading based on the address mapping table.
[0105] In some embodiments, the data writing method further includes: when the processor receives at least one read command for the storage interface, determining, based on the data to be read indicated by the read command, the consecutive logical block addresses of the data to be read from the address mapping table; determining, based on the consecutive logical block addresses, the corresponding consecutive physical block addresses from the address mapping table; and the memory reading the data to be read indicated by the read command based on the consecutive physical block addresses.
[0106] In this embodiment, similar to the write command, when the processor (host side) receives at least one read command for the storage interface, the read command passes through the file system, the block layer, and the device driver layer in the processor (host side) in sequence, and finally reaches the memory (device side). The processor will determine the consecutive logical block addresses corresponding to the data to be read indicated by the read command from the pre-established and continuously updated address mapping table, and determine the corresponding consecutive physical block addresses based on the consecutive logical block addresses. The memory reads the data to be read indicated by the read command at the consecutive physical block addresses. Additionally, if the data to be read by the read command is relatively large and occupies a large storage space in the memory, the block layer in the processor will split the read command into multiple sub-commands, and the device driver layer will schedule the multiple sub-commands to the memory in sequence according to a preset scheduling algorithm, and the memory reads them in sequence according to the consecutive physical block addresses corresponding to the sub-commands.
[0107] In some embodiments, splitting the write command into a preset number of sub-commands and sending them to the memory in step 102 includes: splitting the write command into a preset number of sub-commands based on the storage space indicated by the write command and the minimum storage space that the memory can be operated on; where the sub-storage space indicated by each sub-command is less than or equal to the minimum storage space that the memory can be operated on; and sending the sub-commands to the memory.
[0108] In this embodiment, if the storage space indicated by the write command is greater than the minimum storage space that the memory can be operated on, the write command cannot act on the memory and needs to be split. The splitting process is executed by the block layer in the processor core. The block layer determines the preset number of splits of the write command based on the storage space indicated by the write command and the minimum storage space that the memory can be operated on, and completes the splitting. For example: if the minimum storage space that the memory can be operated on is 512K, the storage space occupied by the split sub-commands should be less than 512K.
[0109] Figure 4 FIG. is a schematic diagram of the process of the processor and the memory interacting to complete data writing according to an exemplary embodiment. The processor (host side) includes a file system, a block layer, and a device driver layer, and the memory (device) includes a storage controller and a storage space.
[0110] Figure 5 A data writing device shown according to an exemplary embodiment, such as Figure 5 shown, the device includes:
[0111] A processor 501, configured to determine the storage space indicated by the write command when detecting at least one write command for a storage interface; wherein, the write command has a command identifier; split the write command into a preset number of sub-commands and send them to the memory; wherein, each of the sub-commands has the command identifier;
[0112] A memory 502, configured to determine the first received sub-command among multiple sub-commands corresponding to the same write command as the target sub-command; based on the command identifier of the target sub-command, allocate a continuous physical block address corresponding to the storage space for the write command, and write the data to be written indicated by the target sub-command in the continuous physical block address.
[0113] In some embodiments, the memory 502 is further configured to:
[0114] When the received sub-command is a non-target sub-command, determine the write command to which the non-target sub-command belongs and the continuous physical block address corresponding to the write command based on the command identifier of the non-target sub-command;
[0115] Write the data to be written of the non-target sub-command to the continuous physical block address corresponding to the write command.
[0116] In some embodiments, the processor 501 is further configured to:
[0117] When it is determined that the write command is successfully executed, obtain the continuous physical block address corresponding to the successfully executed write command;
[0118] Establish a mapping relationship between the continuous physical block address and the corresponding continuous logical block address, and update the address mapping table based on the mapping relationship;
[0119] Wherein, the address mapping table is used to store the continuous physical block address corresponding to the data to be written indicated by the write command and the corresponding continuous logical block address.
[0120] In some embodiments, the processor 501 is further configured to:
[0121] Allocate a corresponding continuous logical block address for the write command based on the storage space indicated by the write command;
[0122] Establish an address mapping table based on the data to be written indicated by the write command and the continuous logical block address.
[0123] In some embodiments, the processor 501 is further configured to:
[0124] When receiving at least one read command for the storage interface, based on the data to be read indicated by the read command, determine the consecutive logical block addresses of the data to be read from the address mapping table;
[0125] Based on the consecutive logical block addresses, determine the corresponding consecutive physical block addresses from the address mapping table;
[0126] The memory 502 is further configured to:
[0127] Based on the consecutive physical block addresses, read the data to be read indicated by the read command.
[0128] In some embodiments, the processor 501 is further configured to:
[0129] Based on the storage space indicated by the write command and the minimum storage space that the memory can be operated on, split the write command into a preset number of sub-commands; wherein, the sub-storage space indicated by each sub-command is less than or equal to the minimum storage space that the memory can be operated on;
[0130] Send the sub-commands to the memory 502.
[0131] In some embodiments, the types of write commands include at least one of the following:
[0132] SCSI write command;
[0133] SATA write command;
[0134] SAS write command
[0135] PCIE write command.
[0136] Regarding the data writing device in the above embodiments, the specific ways in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.
[0137] As Figure 6 shown, embodiments of the present disclosure further provide an electronic device 600, including:
[0138] A memory 604 for storing processor-executable instructions;
[0139] A processor 620, connected to the memory 604;
[0140] Wherein, the processor 620 is configured to execute the data writing method provided by any of the foregoing technical solutions.
[0141] Block diagram of an electronic device 600 shown according to an exemplary embodiment. For example, the electronic device 600 may be a smart phone, a tablet computer, a laptop computer, a portable learning machine, etc.
[0142] Referring Figure 6 , the electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 618.
[0143] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.
[0144] The memory 604 is configured to store various types of data to support the operation of the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, videos, etc. The memory 604 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.
[0145] The power component 606 provides power to various components of the electronic device 600. The power component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.
[0146] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of a touch or swipe action but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.
[0147] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 600 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 604 or transmitted via the communication component 618. In some embodiments, the audio component 610 further includes a speaker for outputting audio signals.
[0148] The I / O interface 612 provides an interface between the processing component 602 and a peripheral interface module, which can be a keyboard, a click wheel, buttons, etc. These buttons can include but are not limited to: a home button, a volume button, a power button, and a lock button.
[0149] The sensor component 614 includes one or more sensors for providing an assessment of the status of various aspects of the electronic device 600. For example, the sensor component 614 can detect the on / off state of the electronic device 600, the relative positioning of components, such as the display and the keypad of the electronic device 600. The sensor component 614 can also detect a change in the position of the electronic device 600 or a component of the electronic device 600, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and a change in the temperature of the electronic device 600. The sensor component 614 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 614 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 614 can further include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
[0150] The communication component 618 is configured to facilitate communication between the electronic device 600 and other devices in a wired or wireless manner. The electronic device 600 may access a communication standard-based wireless network, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 618 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 618 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
[0151] In an exemplary embodiment, the electronic device 600 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described method.
[0152] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the above instructions can be executed by a processor 620 of the electronic device 600 to complete the above method. For example, the non-transitory computer-readable storage medium may be a ROM, Random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data writing device, etc.
[0153] An embodiment of the present application provides a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a processor of a computer, the computer is enabled to execute the data writing method described in one or more of the foregoing technical solutions.
[0154] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.
[0155] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.
Claims
1. A data writing method, characterized in that, Including: When the processor detects at least one write command for the storage interface, determining the storage space indicated by the write command; wherein, the write command has a command identifier; Splitting the write command into a preset number of sub-commands and sending them to the memory; wherein, each of the sub-commands has the command identifier; The memory determines the first received sub-command among the multiple sub-commands corresponding to the same write command as the target sub-command; Based on the command identifier of the target sub-command, allocating a continuous physical block address corresponding to the storage space for the write command in the memory, and writing the data to be written indicated by the target sub-command in the continuous physical block address.
2. The data writing method according to claim 1, wherein The method further includes: When the received sub-command is a non-target sub-command, the memory determines the write command to which the non-target sub-command belongs and the continuous physical block address corresponding to the write command based on the command identifier of the non-target sub-command; Writing the data to be written of the non-target sub-command to the continuous physical block address corresponding to the write command.
3. The data writing method according to claim 1, wherein The method further includes: When it is determined that the write command is successfully executed, the processor obtains the continuous physical block address corresponding to the successfully executed write command; The processor establishes a mapping relationship between the continuous physical block address and the corresponding continuous logical block address, and updates the address mapping table based on the mapping relationship; Wherein, the address mapping table is used to store the continuous physical block address corresponding to the data to be written indicated by the write command and the corresponding continuous logical block address.
4. The data writing method according to claim 3, wherein The method further includes: Based on the storage space indicated by the write command, the processor allocates a corresponding continuous logical block address for the write command; The processor establishes an address mapping table based on the data to be written indicated by the write command and the continuous logical block address.
5. The data writing method according to claim 3, wherein The method further includes: When the processor receives at least one read command for the storage interface, based on the data to be read indicated by the read command, determining the continuous logical block address of the data to be read from the address mapping table; Based on the continuous logical block address, determining the corresponding continuous physical block address from the address mapping table; Based on the continuous physical block address, the memory reads the data to be read indicated by the read command.
6. The data writing method according to claim 1, wherein The splitting the write command into a preset number of sub-commands and sending them to the memory includes: Based on the storage space indicated by the write command and the minimum storage space that the memory can be operated on, splitting the write command into a preset number of sub-commands; wherein, the sub-storage space indicated by each sub-command is less than or equal to the minimum storage space that the memory can be operated on; Sending the sub-commands to the memory.
7. The data writing method according to claim 1, wherein The type of the write command includes at least one of the following: SCSI write command; SATA write command; SAS write command PCIE write command.
8. A data writing device, characterized in that, Including: A processor, configured to determine a storage space indicated by the write command when detecting at least one write command for a storage interface; wherein the write command has a command identifier; split the write command into a preset number of sub-commands and send them to a memory; wherein each of the sub-commands has the command identifier; A memory, configured to determine the first received sub-command among a plurality of sub-commands corresponding to the same write command as a target sub-command; based on the command identifier of the target sub-command, allocate a continuous physical block address corresponding to the storage space for the write command, and write the data to be written indicated by the target sub-command in the continuous physical block address.
9. An electronic device, characterized in that, Comprising: A processor; A memory configured to store processor-executable instructions; Wherein, the processor is configured to be able to execute the data writing method according to any one of claims 1 to 7 when calling the executable instructions in the memory.
10. A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, enabling the electronic device to execute the data writing method according to any one of claims 1 to 7 above.