ECC (Error Correction Code)-supporting memory access method and system applied to DSP (Digital Signal Processor)
By combining the AXI interface and ECC module in the DSP system, flexibly dealing with access requests for different types of memory, the problem of lack of flexibility in the ECC fixed and memory access protocols in the prior art is solved, and efficient and reliable data transmission and system performance improvement are achieved.
Patent Information
- Application Number
- CN202510349667.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2025-07-08
AI Technical Summary
In the high-performance application scenarios, the existing DSP memory access system has a fixed implementation and lacks flexible configuration, and the memory access protocol and interface design lack flexibility, resulting in low memory bandwidth utilization and low data transmission efficiency.
Connect to the internal host of DSP through the AXI interface, receive access requests in real time, and select appropriate processing modules based on the access target and type, combine the ECC module to perform data checksum correction, and use access command cache queue management and priority scheduling mechanism to ensure efficient and reliable data transmission.
It improves memory bandwidth utilization and data transmission efficiency, enhances system adaptability and resource utilization efficiency, and ensures the reliability and integrity of data transmission.
Smart Images
Figure CN120276672A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of memory access, and particularly relates to a memory access method and system supporting ECC for DSP. Background Art
[0002] Digital Signal Processors (DSPs) are widely used in various scenarios requiring high-speed signal processing, such as image processing, speech recognition, communication systems, etc.; in order to meet the high-speed, high-efficiency, and high-precision requirements of these applications, DSPs usually need to handle a large amount of data storage and access operations. Therefore, memory access plays a crucial role in system performance; especially when dealing with large-scale data, memory bandwidth and latency become key factors affecting system performance.
[0003] In the prior art, DSP systems usually adopt multiple memory access protocols to improve memory bandwidth utilization and data access speed; as the amount of data continues to grow, the error incidence rate during data transmission also increases accordingly, especially in high-speed data transmission, the occurrence frequency of errors will increase significantly; therefore, in order to ensure the accuracy and reliability of data, Error Detection and Correction (ECC) has become an important technical means; ECC can effectively detect and correct bit errors in stored data, thereby improving the reliability of the system. Especially in applications requiring high fault tolerance and data accuracy, the role of ECC cannot be ignored.
[0004] Existing DSP memory access systems focus on optimizing memory access bandwidth and timing during design, but rarely combine ECC with the configurability of memory access. Especially in high-performance application scenarios, the integrated design of ECC and the flexibility of memory access are insufficient, restricting the improvement of system performance; existing ECC implementations are usually hardware-fixed and do not have the ability to be flexibly configured, and cannot be optimized according to actual application requirements; at the same time, the protocol and interface design of memory access often lack flexibility. Especially when dealing with different memory types and configurations, the prior art often cannot efficiently support various configuration requirements, resulting in low memory bandwidth utilization and low data transmission efficiency.
[0005] Therefore, the present invention proposes a memory access method and system supporting ECC for DSP to solve the above problems. Summary of the Invention
[0006] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a memory access method and system supporting ECC for DSP, which is used to solve the problems that the existing ECC implementation is usually hardware-fixed, lacks the ability of flexible configuration, and cannot be optimized according to actual application requirements; at the same time, the protocol and interface design of memory access often lack flexibility. Especially when it comes to different memory types and configurations, the prior art often cannot efficiently support various configuration requirements, resulting in low memory bandwidth utilization and low data transmission efficiency.
[0007] To achieve the above object, the first aspect of the present invention provides a memory access method supporting ECC for DSP, including:
[0008] Obtain the access request of the DSP and store the access request in the access command cache queue;
[0009] Obtain the access target of each access request in the access command cache queue, and process the access request based on the access target and the type of the access request.
[0010] Preferably, the storing the access request in the access command cache queue includes:
[0011] A1: Establish a connection with the internal host of the DSP by mounting the AXI interface on the AXI bus of the DSP; wherein, the internal host of the DSP includes: hosts such as CPU, DMA, JTAG interface, etc.;
[0012] A2: Receive in real time the access requests sent by the internal host of the DSP through the AXI bus; wherein, the access requests include: write requests and read requests;
[0013] A3: Cache the access requests into the access command cache queue in the order of receiving the access requests.
[0014] It should be noted that the write request includes the target address, data length, and data to be written of the request; the read request includes the target address and data length of the request; wherein, the target address of the write request is the specific position where the data will be written into the memory, and the data to be written refers to the actual content to be stored, such as image pixel values, sensor data, etc.; the target address of the read request is the starting position where the data needs to be read, which is used to locate the storage area of the target data in the memory;
[0015] The access command cache queue is a key component in the memory access system, which is used to manage and schedule the memory access requests from different internal hosts.
[0016] Preferably, the obtaining the access target of each access request in the access command cache queue includes:
[0017] Extract the target address of each access request in the access command cache queue, and extract the address range of each access target; wherein, the access targets include: special function register groups and external memories; the external memories include: asynchronous memories, synchronous static random access memories, and synchronous dynamic random access memories;
[0018] Compare the target address of the access request with each address range;
[0019] If the target address falls within the address range of the special function register group, the access target is the special function register group;
[0020] If the target address falls within the address range of a certain external memory, the access target is the corresponding external memory.
[0021] It should be noted that the special function register group and the external memory are two different access objects; the special function register group is a set of registers used to configure and control the system. They are usually located inside the chip and contain the parameters and status information required for functions such as system operation mode setting, ECC control, and cache management. By accessing these registers, the system configuration and behavior can be dynamically adjusted; while the external memory refers to the storage devices externally connected to the system, including asynchronous memories, synchronous static random access memories (SRAM), and synchronous dynamic random access memories (SDRAM). These external memories are mainly used for data read and write operations, support large-capacity data storage and high-speed data access, and each type has different access timings and performance characteristics, suitable for different application scenarios.
[0022] In the present invention, by comparing the target address of the access request with the predefined address range, the system can accurately identify and determine whether the target of the current access request is a special function register group or a certain type of external memory, and thus select the appropriate access control module for processing. This mechanism ensures efficient and reliable data transmission and optimal utilization of system resources.
[0023] Preferably, processing the access request based on the type of the access target and the access request includes:
[0024] If the access target is a special function register group, process the access request based on the special function register group; if the access target is the corresponding external memory, process the access request based on the corresponding external memory.
[0025] Preferably, processing the access request based on the special function register group includes:
[0026] Extract the target address of the access request, and confirm the corresponding special function register based on the target address;
[0027] For write requests:
[0028] B1: Extract the data to be written in the write request;
[0029] B2: Write the data to be written into the corresponding special function register;
[0030] B3: After writing is completed, send a write completion signal to the request source;
[0031] For read requests:
[0032] Read the current configuration parameters from the corresponding special function register based on the read request;
[0033] Return the read data to the request source through the AXI interface.
[0034] It should be noted that the confirmation of the corresponding special function register based on the target address means finding the specific register to be accessed by the access request by accessing the target address of the request; for example: assuming the target address is 0x00000004, this address corresponds to the ECC configuration register for controlling the ECC module, then the ECC configuration register is the corresponding special function register;
[0035] The writing of the data to be written into the corresponding special function register means modifying the values in the special function register group according to the written data to adjust the operating mode or other characteristics of the system. For example, writing an instruction to the ECC configuration register to enable the Hamming code error correction function;
[0036] Configuration parameters refer to the data stored in the special function register, and these data are used to control the behavior and functions of the system, including but not limited to: system operating mode setting, ECC control, cache management, interrupt control, peripheral control.
[0037] Preferably, the processing of the access request based on the corresponding external memory includes:
[0038] Extract several access requests with the access target being the external memory from the access command cache queue, and perform priority scheduling on the several access requests through an arbiter based on a preset priority policy;
[0039] Process one by one based on the priority of the access request;
[0040] If the access target is an asynchronous memory, process the access request based on the asynchronous memory;
[0041] If the access target is a synchronous static random access memory, process the access request based on the synchronous static random access memory;
[0042] If the access target is a synchronous dynamic random access memory, the access request is processed based on the synchronous dynamic random access memory.
[0043] It should be noted that the preset priority policy is manually set according to the requirements of actual applications. For example, for applications involving a large amount of data transmission and processing, such as video streaming servers or big data analysis platforms, the priority can be set based on the data volume and the impact on system performance. When multiple users or processes share the same set of resources, in order to ensure fairness and avoid the "starvation" phenomenon (i.e., some requests are not served for a long time), a polling mechanism can be adopted.
[0044] Preferably, the processing of the access request based on the asynchronous memory includes:
[0045] For a write request:
[0046] Extract the data to be written in the write request and store the data to be written in the write data cache queue;
[0047] Generate a corresponding check code for the data to be written in the write data cache queue based on the ECC module;
[0048] Write the data to be written and the corresponding check code into the asynchronous memory;
[0049] For a read request:
[0050] Read data from the asynchronous memory based on the read request and store the read data in the read data cache queue;
[0051] Perform ECC check on the data stored in the read data cache queue based on the ECC module; if one check bit does not match, it indicates that a single-bit error exists, and the ECC module corrects it by itself; if multiple check bits do not match, it indicates that a multi-bit error has occurred, and the ECC module sends an interrupt signal to stop the read access and reads the data again;
[0052] Return the verified data to the request source through the AXI interface.
[0053] It should be noted that the ECC module is a software component used to detect and correct errors that occur during data transmission or storage; among them, the ECC module generates check information based on the ECC algorithm and uses these check information to detect and correct errors; the ECC algorithm includes: Hamming code, BCH code, etc.
[0054] Preferably, the processing of the access request based on the synchronous static random access memory includes:
[0055] For a write request:
[0056] Extract the data to be written in the write request, and store the data to be written in the write data cache queue;
[0057] Generate the corresponding check code for the data to be written in the write data cache queue based on the ECC module;
[0058] Set the write access address and the write enable signal to be valid, and wait for the set number of write access delay cycles;
[0059] Write the data to be written and the corresponding check code into the synchronous static random access memory, and write one data per clock cycle;
[0060] For a read request:
[0061] Set the read access address and the read enable signal to be valid, and wait for the set number of read access delay cycles;
[0062] Read data from the synchronous static random access memory based on the read request, and store the read data in the read data cache queue;
[0063] Perform ECC check on the data stored in the read data cache queue based on the ECC module;
[0064] Return the data after check to the request source through the AXI interface.
[0065] It should be noted that setting the write access address and the read access address is to determine the specific location of accessing the memory; the write enable signal being valid and the read enable signal being valid are to indicate the current operation mode. For example, when the write enable signal is valid, it means that the system needs to write data into the memory; different types of memories have different access delays. For example, the synchronous static random access memory has a relatively low access delay, but still requires a certain amount of time to complete the write operation. Therefore, the waiting for the set number of write access delay cycles can ensure that the memory has enough time to complete the writing process.
[0066] Preferably, the processing of the access request by the synchronous dynamic random access memory includes:
[0067] For a write request:
[0068] Extract the row address and column address corresponding to the target address of the write request;
[0069] Activate the row address corresponding to the write request, and select the corresponding column address after waiting for the tRCD time; where the tRCD time refers to the minimum delay time from the activation of the row address to the selection of the column address;
[0070] Extract the data to be written in the write request, and store the data to be written in the write data cache queue;
[0071] Generate a corresponding check code for the data to be written in the write data cache queue based on the ECC module;
[0072] Write the data to be written and the corresponding check code into the synchronous dynamic random access memory;
[0073] For a read request:
[0074] Extract the row address and column address corresponding to the target address of the read request;
[0075] Activate the row address corresponding to the read request, and select the corresponding column address after waiting for the tRCD time;
[0076] Read data from the synchronous dynamic random access memory based on the read request, and store the read data in the read data cache queue;
[0077] Perform ECC check on the data stored in the read data cache queue based on the ECC module;
[0078] Return the verified data to the request source through the AXI interface.
[0079] It should be noted that the row address refers to a specific row in a specific bank within the synchronous dynamic random access memory chip. Each row is actually a capacitor array for storing data, and the row address determines the specific location of the accessed row;
[0080] The column address refers to a specific column in the selected row. The column address further refines the access location and determines the specific data unit to be read or written;
[0081] tRCD refers to the minimum delay time from activating the row address to being able to issue the column address. This is because after activating the row, it takes a certain amount of time for all the capacitors in that row to charge to a stable state so that subsequent column access can be carried out correctly.
[0082] The second aspect of the present invention provides a memory access system supporting ECC applied to a DSP, including: an AXI interface, an arbiter, a special function register group, an access command cache queue, a write data cache queue, a read data cache queue, an ECC module, and a memory access processing module;
[0083] The AXI interface is used to establish a connection with the internal host of the DSP;
[0084] The arbiter is used to manage multiple access requests to the external memory, ensuring that the access requests to the external memory are scheduled according to priority;
[0085] The special function register group is used to store and control configuration parameters;
[0086] The access command cache queue is used to temporarily store the access requests of the internal host of the DSP;
[0087] The write data cache queue is used to store the data to be written that is prepared to be written into the external memory;
[0088] The read data cache queue is used to store the data read from the external memory;
[0089] The ECC module is used to detect and correct errors in the data during the external memory access process;
[0090] The memory access processing module is used to process the access requests for accessing the external memory, including: asynchronous memory, synchronous static random access memory, and synchronous dynamic random access memory.
[0091] Compared with the prior art, the beneficial effects of the present invention are:
[0092] 1. When designing the existing DSP memory access system, it focuses on the bandwidth and timing optimization of memory access, but rarely combines ECC with the configurability of memory access. Especially in high-performance application scenarios, the integrated design of ECC and the flexibility of memory access are insufficient, which limits the improvement of system performance; the existing ECC implementations are usually hardware-fixed and do not have the ability to be flexibly configured and cannot be optimized according to actual application requirements; at the same time, the protocol and interface design of memory access often lack flexibility. Especially when it comes to different memory types and configurations, the prior art often cannot efficiently support various configuration requirements, resulting in low memory bandwidth utilization and low data transmission efficiency; the present invention establishes a connection with the internal host of the DSP through the AXI interface and receives the memory access requests sent by these hosts in real time; by extracting the target address of each access request and comparing it with the predefined address ranges of different types of memories to determine the specific access target; based on the access target and request type, select the corresponding processing module for operation, and at the same time use the ECC module to generate or verify data, solving the above problems; by integrating the ECC module, the present invention can not only detect single-bit errors and automatically correct them, but also trigger an interrupt when detecting multi-bit errors, ensuring the high reliability and integrity of data transmission; by using the access command cache queue to manage and schedule various types of memory access requests from different internal hosts and performing efficient scheduling through the arbiter based on the preset priority policy, ensuring the effective utilization of system resources and the timely response to access requests.
[0093] 2. The present invention establishes a connection with the internal host of the DSP through the AXI interface, receives and caches access requests from different internal hosts in real time, ensuring an efficient data transmission path; by parsing the target address of each access request and matching it with the predefined address ranges of different types of memories, accurately identifying the access target, and thus selecting an appropriate processing module for operation; for the characteristics of different types of memories, the present invention defines corresponding access processes in detail. For example, in SDRAM, the row address and column address are accurately calculated, and the tRCD delay is considered to ensure the accuracy of data access; at the same time, an ECC module is integrated during the read and write processes to automatically detect and correct single-bit errors, and trigger an interruption for multi-bit errors to take further measures, greatly improving the reliability and integrity of data transmission; in addition, by flexibly configuring the ECC strategy and adopting a priority scheduling mechanism to manage the access command cache queue, the present invention not only improves the adaptability and scalability of the system, but also optimizes the resource utilization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0094] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0095] Figure 1 Schematic diagram of the method steps of the embodiment of the present invention;
[0096] Figure 2 Schematic diagram of the method for storing access requests into the access command cache queue in the embodiment of the present invention;
[0097] Figure 3 Schematic diagram of the method for obtaining access targets in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0098] The following will clearly and completely describe the technical solutions of the present invention in combination with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.
[0099] Please refer to Figure 1 , the first aspect embodiment of the present invention provides a memory access method supporting ECC applied to a DSP, including:
[0100] Obtain the access request of the DSP and store the access request in the access command cache queue;
[0101] Obtain the access target of each access request in the access command cache queue, and process the access requests based on the access target and the type of the access requests.
[0102] See Figure 2 , storing the access requests into the access command cache queue, including:
[0103] A1: Establish a connection with the internal host of the DSP by mounting the AXI interface on the AXI bus of the DSP; wherein, the internal host of the DSP includes: hosts such as CPU, DMA, JTAG interface, etc.
[0104] A2: Receive in real time the access requests sent by the internal host of the DSP through the AXI bus; wherein, the access requests include: write requests and read requests.
[0105] A3: Cache the access requests into the access command cache queue in the order of receiving the access requests.
[0106] See Figure 3 , obtaining the access target of each access request in the access command cache queue, including:
[0107] Extract the target address of each access request in the access command cache queue, and extract the address range of each access target; wherein, the access targets include: special function register groups and external memories; the external memories include: asynchronous memories, synchronous static random access memories, and synchronous dynamic random access memories.
[0108] Compare the target address of the access request with each address range.
[0109] If the target address falls within the address range of the special function register group, the access target is the special function register group.
[0110] If the target address falls within the address range of a certain external memory, the access target is the corresponding external memory.
[0111] Process the access requests based on the access target and the type of the access requests, including:
[0112] If the access target is a special function register group, process the access requests based on the special function register group; if the access target is the corresponding external memory, process the access requests based on the corresponding external memory.
[0113] Process the access requests based on the special function register group, including:
[0114] Extract the target address of the access request, and confirm the corresponding special function register based on the target address.
[0115] For write requests:
[0116] B1: Extract the data to be written in the write request;
[0117] B2: Write the data to be written into the corresponding special function register;
[0118] B3: After writing is completed, send a write completion signal to the request source;
[0119] For read requests:
[0120] Read the current configuration parameters from the corresponding special function register based on the read request;
[0121] Return the read data to the request source through the AXI interface.
[0122] Process the access request based on the corresponding external memory, including:
[0123] Extract several access requests with the access target being the external memory from the access command cache queue, and perform priority scheduling on the several access requests through an arbiter based on a preset priority policy;
[0124] Process one by one based on the priority of the access request;
[0125] If the access target is an asynchronous memory, process the access request based on the asynchronous memory;
[0126] If the access target is a synchronous static random access memory, process the access request based on the synchronous static random access memory;
[0127] If the access target is a synchronous dynamic random access memory, process the access request based on the synchronous dynamic random access memory.
[0128] Process the access request based on the asynchronous memory, including:
[0129] For write requests:
[0130] Extract the data to be written in the write request and store the data to be written in the write data cache queue;
[0131] Generate the corresponding check code for the data to be written in the write data cache queue based on the ECC module;
[0132] Write the data to be written and the corresponding check code into the asynchronous memory;
[0133] For read requests:
[0134] Read the data from the asynchronous memory based on the read request and store the read data in the read data cache queue;
[0135] Perform ECC check on the data stored in the read data cache queue based on the ECC module; if one parity bit does not match, it indicates a single-bit error, and the ECC module corrects it by itself; if multiple parity bits do not match, it indicates a multi-bit error, and the ECC module sends an interrupt signal to stop the read access and reread the data;
[0136] Return the verified data to the request source through the AXI interface.
[0137] Process access requests based on the synchronous static random access memory, including:
[0138] For write requests:
[0139] Extract the data to be written in the write request and store the data to be written in the write data cache queue;
[0140] Generate corresponding parity codes for the data to be written in the write data cache queue based on the ECC module;
[0141] Set the write access address and the write enable signal to be valid and wait for the set number of write access delay cycles;
[0142] Write the data to be written and the corresponding parity codes into the synchronous static random access memory, and write one data per clock cycle;
[0143] For read requests:
[0144] Set the read access address and the read enable signal to be valid and wait for the set number of read access delay cycles;
[0145] Read data from the synchronous static random access memory based on the read request and store the read data in the read data cache queue;
[0146] Perform ECC check on the data stored in the read data cache queue based on the ECC module;
[0147] Return the verified data to the request source through the AXI interface.
[0148] Process access requests by the synchronous dynamic random access memory, including:
[0149] For write requests:
[0150] Extract the row address and column address corresponding to the target address of the write request;
[0151] Activate the row address corresponding to the write request and select the corresponding column address after waiting for the tRCD time; where the tRCD time refers to the minimum delay time from row address activation to column address selection;
[0152] Extract the data to be written for the write request and store the data to be written in the write data cache queue;
[0153] Generate a corresponding check code for the data to be written in the write data cache queue based on the ECC module;
[0154] Write the data to be written and the corresponding check code into the synchronous dynamic random access memory;
[0155] For a read request:
[0156] Extract the row address and column address corresponding to the target address of the read request;
[0157] Activate the row address corresponding to the read request and select the corresponding column address after waiting for the tRCD time;
[0158] Read data from the synchronous dynamic random access memory based on the read request and store the read data in the read data cache queue;
[0159] Perform ECC check on the data stored in the read data cache queue based on the ECC module;
[0160] Return the verified data to the request source through the AXI interface.
[0161] Embodiment: Suppose there is a DSP system, which includes a CPU, a DMA controller, and a JTAG debug interface as internal hosts. These hosts need to access different memory resources, including a special function register bank (such as registers for controlling the ECC module), asynchronous memory (for configuration data), synchronous static random access memory (SRAM, for caching), and synchronous dynamic random access memory (SDRAM, for large-capacity data storage). Each host can send read and write requests through the AXI bus.
[0162] Step 1: Obtain and cache the access request;
[0163] 1. Connection establishment:
[0164] Establish a connection with the internal hosts (CPU, DMA, JTAG interface) of the DSP by mounting the AXI interface on the AXI bus of the DSP.
[0165] 2. Receive the access request:
[0166] Suppose the CPU issues a write request with a target address of 0x00000004, a data length of 4 bytes, and the data to be written is X. This address corresponds to the ECC configuration register for controlling the ECC module.
[0167] Assume that the DMA controller issues a read request with a target address of 0x10000000 and a data length of 8 bytes. This address is located in the SDRAM.
[0168] 3. Cache access request:
[0169] Cache the write requests issued by the CPU and the read requests issued by the DMA controller into the access command cache queue in the order of receipt.
[0170] Step 2: Determine the access target;
[0171] 1. Parse the target address:
[0172] For the CPU's write request, assume that the target address 0x00000004 falls within the address range of the special function register group. Therefore, the access target is the special function register group.
[0173] For the DMA's read request, the target address 0x10000000 falls within the address range of the SDRAM. Therefore, the access target is the SDRAM.
[0174] Step 3: Process the access request based on the access target;
[0175] Processing of the special function register group:
[0176] 1. Extract the target address:
[0177] Extract the target address 0x00000004 of the CPU write request. Assume that this address corresponds to the ECC configuration register that controls the ECC module. Then, the ECC configuration register is the corresponding special function register.
[0178] 2. Write operation:
[0179] Extract the data X to be written.
[0180] Write X into the ECC configuration register to enable the Hamming code error correction function.
[0181] After the write is completed, send a write completion signal to the CPU.
[0182] Processing of the SDRAM:
[0183] 1. Row address and column address parsing:
[0184] Extract the target address 0x10000000 of the DMA read request and calculate the corresponding row address and column address. Assume that the row address is 0x100 and the column address is 0x00.
[0185] 2. Activate the row address:
[0186] Activate the row address 0x100 and wait for the tRCD time (e.g., 5 clock cycles) to ensure that all capacitors in the row are charged to a stable state.
[0187] 3. Read data:
[0188] After the tRCD delay, select the column address 0x00, read 8 bytes of data from the SDRAM, and store it in the read data buffer queue.
[0189] 4. ECC check:
[0190] Use the ECC module to check the read data. If a single-bit error is found, the ECC module automatically corrects it; if it is a multi-bit error, an interrupt is triggered and the data is read again.
[0191] 5. Return data:
[0192] The verified data is returned to the DMA controller through the AXI interface.
[0193] As can be seen from the above example, the present invention provides a comprehensive method to manage access requests from different internal hosts and can flexibly handle the access requirements of different types of memories. Specifically:
[0194] Enhanced compatibility: Whether it is a special function register group or an external memory (such as an asynchronous memory, SRAM, and SDRAM), it can be accurately identified and processed, ensuring high compatibility and flexibility of the system.
[0195] - Improved data reliability: The integrated ECC module not only improves the reliability of data transmission but also can be flexibly configured according to actual application requirements to meet the data protection requirements in various environments.
[0196] Efficient scheduling mechanism: Through the access command buffer queue and the priority scheduling mechanism, the concurrent access requests of multiple hosts are effectively managed and optimized, avoiding resource contention and the occurrence of the "starvation" phenomenon.
[0197] Performance optimization: For the specific characteristics of each type of memory (such as access latency, read / write process, etc.), detailed access policies are formulated, significantly improving the memory bandwidth utilization and data transmission efficiency.
[0198] An embodiment of the second aspect of the present invention provides a memory access system supporting ECC applied to a DSP, including: an AXI interface, an arbiter, a special function register group, an access command buffer queue, a write data buffer queue, a read data buffer queue, an ECC module, and a memory access processing module;
[0199] The AXI interface is used to establish a connection with the internal host of the DSP;
[0200] The arbiter is used to manage multiple access requests to an external memory, ensuring that the access requests to the external memory are scheduled according to priorities;
[0201] The special function register group is used to store and control configuration parameters;
[0202] The access command cache queue is used to temporarily store access requests from the internal host of the DSP;
[0203] The write data cache queue is used to store data to be written that is ready to be written to the external memory;
[0204] The read data cache queue is used to store data read from the external memory;
[0205] The ECC module is used to detect and correct errors in the data during the access to the external memory;
[0206] The memory access processing module is used to process access requests to the external memory, including: asynchronous memory, synchronous static random access memory, and synchronous dynamic random access memory.
[0207] The above embodiments are only used to illustrate the technical method of the present invention and not to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical method of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical method of the present invention.
Claims
1. A memory access method supporting ECC applied to DSP, characterized in that, Including: Obtain the access request of the DSP and store the access request in the access command cache queue; Obtain the access target of each access request in the access command cache queue, and process the access request based on the access target and the type of the access request.
2. The memory access method supporting ECC applied to DSP according to claim 1, wherein The storing the access request in the access command cache queue includes: A1: Establish a connection with the internal host of the DSP by mounting the AXI interface on the AXI bus of the DSP; A2: Receive in real time the access requests sent by the internal host of the DSP through the AXI bus; wherein, the access requests include: write requests and read requests; A3: Cache the access requests into the access command cache queue in the order of receiving the access requests.
3. A memory access method supporting ECC applied to DSP according to claim 1, characterized in that, The obtaining the access target of each access request in the access command cache queue includes: Extract the target address of each access request in the access command cache queue, and extract the address range of each access target; wherein, the access targets include: special function register groups and external memories; the external memories include: asynchronous memories, synchronous static random access memories, and synchronous dynamic random access memories; Compare the target address of the access request with each address range; If the target address falls within the address range of the special function register group, the access target is the special function register group; If the target address falls within the address range of a certain external memory, the access target is the corresponding external memory.
4. A memory access method for DSP supporting ECC according to claim 1, characterized in that The processing the access request based on the access target and the type of the access request includes: If the access target is the special function register group, process the access request based on the special function register group; if the access target is the corresponding external memory, process the access request based on the corresponding external memory.
5. The memory access method supporting ECC applied to DSP according to claim 4, wherein The processing the access request based on the special function register group includes: Extract the target address of the access request and confirm the corresponding special function register based on the target address; For the write request: B1: Extract the data to be written of the write request; B2: Write the data to be written into the corresponding special function register; B3: After the writing is completed, send a writing completion signal to the request source; For the read request: Read the current configuration parameters from the corresponding special function register based on the read request; Return the read data to the request source through the AXI interface.
6. The memory access method supporting ECC applied to DSP according to claim 4, wherein The processing the access request based on the corresponding external memory includes: Extract several access requests with the access target being the external memory from the access command cache queue, and perform priority scheduling on the several access requests through an arbiter based on a preset priority policy; Process one by one based on the priority of the access request; If the access target is the asynchronous memory, process the access request based on the asynchronous memory; If the access target is the synchronous static random access memory, process the access request based on the synchronous static random access memory; If the access target is the synchronous dynamic random access memory, process the access request based on the synchronous dynamic random access memory.
7. A memory access method for DSP supporting ECC according to claim 6, characterized in that, The processing the access request based on the asynchronous memory includes: For the write request: Extract the data to be written of the write request and store the data to be written in the write data cache queue; Generate a corresponding check code for the data to be written in the write data cache queue based on the ECC module; Write the data to be written and the corresponding check code into the asynchronous memory; For a read request: Read data from the asynchronous memory based on the read request and store the read data in the read data cache queue; Perform ECC check on the data stored in the read data cache queue based on the ECC module; if one check bit does not match, it indicates a single-bit error and the ECC module corrects it automatically; if multiple check bits do not match, it indicates a multi-bit error and the ECC module sends an interrupt signal to stop the read access and reads the data again; Return the checked data to the request source through the AXI interface.
8. The memory access method supporting ECC applied to DSP according to claim 6, characterized in that, The processing of the access request based on the synchronous static random access memory includes: For a write request: Extract the data to be written in the write request and store the data to be written in the write data cache queue; Generate a corresponding check code for the data to be written in the write data cache queue based on the ECC module; Set the write access address and the write enable signal to be valid and wait for the set number of write access delay cycles; Write the data to be written and the corresponding check code into the synchronous static random access memory, and write one data per clock cycle; For a read request: Set the read access address and the read enable signal to be valid and wait for the set number of read access delay cycles; Read data from the synchronous static random access memory based on the read request and store the read data in the read data cache queue; Perform ECC check on the data stored in the read data cache queue based on the ECC module; Return the checked data to the request source through the AXI interface.
9. The memory access method supporting ECC applied to DSP according to claim 6, wherein, The processing of the access request by the synchronous dynamic random access memory includes: For a write request: Extract the row address and column address corresponding to the target address of the write request; Activate the row address corresponding to the write request and wait for the tRCD time before selecting the corresponding column address; where the tRCD time refers to the minimum delay time from the activation of the row address to the selection of the column address; Extract the data to be written in the write request and store the data to be written in the write data cache queue; Generate a corresponding check code for the data to be written in the write data cache queue based on the ECC module; Write the data to be written and the corresponding check code into the synchronous dynamic random access memory; For a read request: Extract the row address and column address corresponding to the target address of the read request; Activate the row address corresponding to the read request and wait for the tRCD time before selecting the corresponding column address; Read data from the synchronous dynamic random access memory based on the read request and store the read data in the read data cache queue; Perform ECC check on the data stored in the read data cache queue based on the ECC module; Return the checked data to the request source through the AXI interface.
10. A memory access system supporting ECC for DSP, which is used to execute a memory access method supporting ECC for DSP according to any one of claims 1-9, characterized in that, Include: An arbiter, a special function register group, an access command cache queue, a write data cache queue, a read data cache queue, an ECC module, and a memory access processing module; The AXI interface is used to establish a connection with the internal host of the DSP; The arbiter is used to manage multiple access requests to the external memory to ensure that the access requests to the external memory are scheduled according to priority; The special function register group is used to store and control configuration parameters; The access command cache queue is used to temporarily store access requests from the internal host of the DSP; The write data cache queue is used to store data to be written that is ready to be written to the external memory; The read data cache queue is used to store data read from the external memory; The ECC module is used to detect and correct errors in the data during the external memory access process; The memory access processing module is used to process access requests for accessing the external memory, including: asynchronous memory, synchronous static random access memory, and synchronous dynamic random access memory.