Satellite on-orbit high-speed data processing system supporting asynchronous communication based on CPU + FPGA

Abstract

The invention provides a CPU + FPGA-based satellite on-orbit high-speed data processing system and method supporting asynchronous communication, which are used for realizing satellite on-orbit real-time data processing. On-orbit data processing is carried out in a dual-processor assembly line mode, data communication between a CPU and an FPGA adopts a dual-port RAM and a cache mechanism, asynchronous data interaction is carried out in a request amp and response mode, multi-channel data parallel processing is supported, and multi-processor expansion can be carried out. According to the scheme, the data communication design is simplified, the data processing efficiency and reliability are improved, and the satellite load data on-orbit high-speed processing requirement is met.

Description

Technical Field

[0001] The present invention relates to the fields of space technology and embedded system design, and in particular, to a satellite on-orbit high-speed data processing system based on CPU+FPGA that supports asynchronous communication. Background Art

[0002] With the increasing demand for high-speed processing of satellite on-orbit data, it is difficult to meet the performance requirements using a single processor. Existing technologies usually adopt a combination of multiple types of processors, such as CPU+FPGA. However, there are still some defects in this solution on the market at present. One is that for the high-speed data transmission between the CPU and the FPGA, a high-speed data transmission bus is generally used, resulting in high design complexity and software and hardware costs. The other is that due to the different processing speeds and computing tasks of the two, the overall data processing efficiency of the system is usually limited to achieve data synchronization, reducing the processing real-time performance. In addition, data loss problems may occur when the upstream data volume exceeds the processing capacity. A simpler and more efficient solution is needed to achieve satellite on-orbit high-speed data processing. Summary of the Invention

[0003] To solve the above problems, the present invention provides a satellite on-orbit high-speed data processing system based on CPU+FPGA that supports asynchronous communication, which is characterized by including:

[0004] A CUP, an FPGA, an SRAM, an SDRAM, a FLASH, an FPGA refresh chip, and corresponding address and data transmission buses, where the FLASH storage and the FPGA refresh chip are optional configurations;

[0005] The system uses a dual-processor pipeline method of CPU+FPGA for on-orbit data processing;

[0006] Among them, the FPGA is configured to mainly receive, unpack, and preprocess data;

[0007] The CPU is configured to mainly perform more complex algorithm processing and floating-point calculations;

[0008] The SDRAM is configured as a data buffer area to be used for temporarily storing data packets received from the outside, and

[0009] The SRAM is configured as a running memory area to be used for storing preprocessed data.

[0010] In an embodiment of the present invention, the FPGA receives external data input through an LVDS high-speed data transmission interface;

[0011] The FPGA is connected to the SRAM and the SDRAM through data lines and address lines;

[0012] The CPU accesses the FPGA through an EM I F interface.

[0013] In another embodiment of the present invention, the FLASH memory and the FPGA refresh chip are configured to implement dynamic refresh of the FPGA.

[0014] In another embodiment of the present invention, it is characterized in that

[0015] It further includes system software, and the system software includes FPGA software and CPU software;

[0016] The main functional modules of the FPGA software include data reception and verification, data caching, SDRAM read and write control, unpacking and refreshing, SRAM arbitration and read and write control, and data transmission;

[0017] The main functional modules of the CPU software include data request, data reading, data processing, and data output.

[0018] In another embodiment of the present invention, the system performs partition management on the storage space, including:

[0019] A data cache area, located in the SDRAM, is used for the FPGA to cache data packets;

[0020] A shared storage area, located in the SRAM, can be accessed by both the FPGA and the CPU;

[0021] A memory area exclusive to the FPGA is only used for the operation of the FPGA program;

[0022] A memory area exclusive to the CPU is only used for the CPU program and is used for large data storage and calculation;

[0023] Among them, the shared storage area is further divided into:

[0024] An FPGA data transmission area stores the data preprocessed by the FPGA,

[0025] A CPU data transmission area stores the result data after being processed by the CPU.

[0026] In another embodiment of the present invention, a dual-port RAM is used to share the memory space to achieve high-speed data interaction between the CPU and the FPGA. Both the CPU and the FPGA can access the shared storage area on the SRAM;

[0027] Among them, the CPU accesses the SRAM of the FPGA through the EMI F interface for data reading and writing; and

[0028] A partitioned shared storage design is adopted, and data reception and data transmission access different address space partitions. Memory read and write control flag bits are set, and the CPU and the FPGA implement data interaction control by setting and judging relevant flag bits to avoid read and write conflicts.

[0029] In another embodiment of the present invention, a caching mechanism is adopted. The FPGA first caches the received upstream data in the SDRAM;

[0030] A cache status flag is set to identify the status of the cache space;

[0031] The cache space is managed according to the first-in, first-out principle. The data processed by the FPGA will release the occupied buffer;

[0032] It has the function of instructing or automatically clearing the buffer. The CPU program has the function of forcibly clearing the cache space as needed.

[0033] In another embodiment of the present invention, an asynchronous communication method is used for data interaction. The data communication between the CUP and the FPGA adopts an asynchronous request refresh mechanism. After the CPU completes data processing, it sends a data refresh request to the FPGA. The FPGA extracts the data packet from the cache for unpacking and preprocessing, and writes the result into the FPGA transmission data area in the shared memory. The CPU reads it for subsequent processing.

[0034] In another embodiment of the present invention, the system has the ability to parallel-process multi-channel data. By setting corresponding flag bits and address spaces, the number of parallel processing channels is increased, and the data of each channel does not interfere with each other, realizing parallel processing;

[0035] It has the ability to expand the multi-core processing mode. By increasing the number of processors, multi-processor parallel processing can be achieved, improving the system's data processing ability.

[0036] The present invention also provides an asynchronous communication method for high-speed in-orbit data processing of a satellite based on CPU+FPGA, which is characterized by including:

[0037] Use the asynchronous "request - send" method for data interaction;

[0038] It includes the following processing procedures: data reception and processing stage:

[0039] The FPGA receives data through a high-speed data transmission interface;

[0040] The FPGA performs data verification and stores the data packet in the data buffer;

[0041] When the CPU is idle, it requests new data by writing a specific flag bit in the shared memory area;

[0042] After the FPGA reads the CPU request, it unpacks and performs related preprocessing on the data packets in the data buffer according to the first-in, first-out principle;

[0043] The FPGA stores the unpacked data in a specific address space of the shared storage area according to the interface protocol and sets the completion flag.

[0044] After the CPU determines that the FPGA has finished writing, it reads the data from the FPGA data transmission area in the shared storage area for subsequent data processing.

[0045] Result data transmission stage:

[0046] After the CPU determines that the buffer is empty according to the flag bit, it writes the result data into the data input queue of the FPGA.

[0047] The FPGA sends it out through the high-speed data transmission interface.

[0048] Among them, each processing channel is set with an independent flag bit and storage address space, and has the ability to perform multi-channel data parallel transmission and processing.

[0049] The present invention has the following beneficial effects:

[0050] (1) Adopting a dual-processor pipeline method, making a reasonable function division according to the characteristics of the FPGA and the CPU, and supporting expansion to multi-processor and multi-channel parallel processing, thereby improving the system data processing performance.

[0051] (2) Using a dual-port RAM shared memory space to achieve high-speed data interaction. The CPU accesses the RAM of the FPGA through the EM I F interface for data reading and writing. Adopting a partitioned shared storage design, the data reception and data transmission access different address space partitions, and set read and write status flag bits to avoid read and write conflicts.

[0052] (3) Adopting an asynchronous request refresh and data caching mechanism to solve the problems caused by the processing time difference of different processors, improving the overall processing efficiency and avoiding data loss. The traditional method generally processes the data immediately after the FPGA receives it, sends it to the downstream processor immediately after processing, and notifies the downstream processor through interrupts and other methods. The overall performance is restricted by the slower processing nodes, and data loss is likely to occur when the data volume exceeds the processing capacity. According to the functional design and the characteristics of different processors, the CPU processes complex and time-consuming tasks, and the FPGA has a fast preprocessing speed and short processing time. The present invention adopts a "request-send" method. When the CPU is idle, it updates the relevant flag bits. After the FPGA reads the data refresh request, it extracts the data from the buffer area, performs unpacking and other processing, and then writes it to the specified address. The CPU reads it for subsequent processing. The system processing performance is maximized.

[0053] (4) Cache the upstream data, and design functions such as cache status flags and cache clearing, which ensures the timely processing and non-loss of upstream bursty data, facilitates the high-speed processing of large amounts of data within a specific time period, and improves the system security and reliability.

[0054] (5) The present invention improves the data transmission efficiency, solves the problem of mismatched processing speeds between the upstream and downstream processors, ensures the real-time and reliable in-orbit data processing, and meets the requirements of high-speed in-orbit processing of satellite payload data. It effectively solves the performance and processing anomaly problems caused by complex calculations, low processor performance, and long running time during the in-orbit real-time processing of satellite payload data, and is applicable to low-cost, large-volume, and complex in-orbit soft real-time data processing with complex calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Shows the composition and interface block diagram of the satellite in-orbit high-speed data processing system in an embodiment of the present invention;

[0056] Figure 2 Shows an example table of the components of the satellite in-orbit high-speed data processing system in an embodiment of the present invention;

[0057] Figure 3 Shows the data flow diagram of the satellite in-orbit high-speed data processing system in an embodiment of the present invention; and

[0058] Figure 4 Shows an example table of the storage space management design of the satellite in-orbit high-speed data processing system in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0059] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments can be implemented without one or more specific details or in combination with other alternative and / or additional methods, materials, or components. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive points of the present invention. Similarly, for the purpose of explanation, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details.

[0060] In this specification, the reference to "an embodiment" or "the embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. The phrase "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment.

[0061] Figure 1 Shows the composition and interface block diagram of the satellite in-orbit high-speed data processing asynchronous communication system in an embodiment of the present invention.

[0062] As can be seen from Figure 1 , in an embodiment of the present invention, the satellite on-orbit high-speed data processing system includes:

[0063] The system hardware components include a CUP, an FPGA, an SRAM, an SDRAM, a FLASH, an FPGA refresh chip, and corresponding address and data transmission buses, where the FLASH storage and the FPGA refresh chip are optional configurations;

[0064] The on-orbit data processing is performed in a CPU+FPGA dual-processor pipeline manner;

[0065] The FPGA is configured to mainly receive, unpack, and preprocess data;

[0066] The CPU is configured to mainly perform more complex algorithm processing and floating-point calculations;

[0067] The SDRAM is configured as a data buffer area for temporarily storing the data packets received from the outside, and

[0068] The SRAM is configured as a running memory area for storing the preprocessed data.

[0069] Among them, the FPGA receives external data input through the LVDS high-speed data transmission interface;

[0070] The FPGA is connected to the SRAM and the SDRAM through data lines and address lines;

[0071] The CPU accesses the FPGA through the EM I F interface.

[0072] Figure 2 Shows an example table of the components of the satellite on-orbit high-speed data processing system in an embodiment of the present invention.

[0073] As Figure 2 shown, only the selection of each component in an embodiment of the present invention is shown. The present invention has no limitation on the selection of the processor, and can be specifically designed according to data processing performance, storage, reliability requirements, etc. Figure 2 It is only used as a reference for the hardware selection in an embodiment of the present invention. In addition, in this embodiment, the refresh chip and the FLASH are optional configurations.

[0074] Figure 3 Shows the data flow diagram of the satellite on-orbit high-speed data processing system in an embodiment of the present invention. As Figure 3As shown, the system software includes FPGA software and CPU software. The main functional modules of the FPGA software include data reception and verification, data caching, SDRAM read / write control, unpacking and refreshing, SRAM arbitration and read / write control, and data transmission. The main functional modules of the CPU software include data request, data reading, data processing, and data output.

[0075] The processing procedure is as follows:

[0076] (1) Data reception and processing stage:

[0077] The FPGA receives data through a high-speed data transmission interface;

[0078] The FPGA performs data verification and stores the data packet in the data buffer;

[0079] When the CPU is idle, it requests new data by writing a specific flag bit in the shared storage area;

[0080] After the FPGA reads the CPU request, it unpacks and performs related preprocessing on the data packets in the data buffer according to the first-in-first-out principle;

[0081] The FPGA stores the unpacked data in a specific address space of the shared storage area according to the interface protocol and sets the completion flag;

[0082] After the CPU determines that the FPGA writing is completed, it reads the data from the FPGA data sending area in the shared storage area for subsequent data processing;

[0083] (2) Processing result sending stage:

[0084] After the CPU determines that the buffer is empty according to the flag bit, it writes the result data into the data input queue of the FPGA;

[0085] The FPGA sends it out through the high-speed data transmission interface;

[0086] Each channel is set with an independent flag bit and storage address space, and has the ability to perform multi-channel data parallel transmission and processing.

[0087] Figure 4 Shows the storage space management design example table of the satellite on-orbit high-speed data processing system in an embodiment of the present invention. As Figure 4 shown, the storage space is partitioned and managed, including

[0088] The data buffer area, located in the SDRAM, is used for the FPGA to cache data packets;

[0089] The shared storage area, located in the SRAM, can be accessed by both the FPGA and the CPU;

[0090] The exclusive memory area for the FPGA is only used for the operation of the FPGA program;

[0091] The exclusive memory area for the CPU is only used for the CPU program and is used for large data storage and calculation;

[0092] Among them, the shared storage area is further divided into:

[0093] The data sending area of the FPGA stores the data preprocessed by the FPGA,

[0094] The data sending area of the CPU stores the result data after the CPU processing is completed;

[0095] Set the memory read / write control flag bits. The CPU and the FPGA realize data interaction control by setting and judging the relevant flag bits. See Figure 4 。

[0096] In summary, the present invention makes full use of the respective advantages of the CPU and the FPGA for function division, realizes pipeline-style high-speed data processing, supports multi-channel parallel processing, supports multi-processor expansion, and can realize high-speed on-orbit data processing using low-cost processors.

[0097] Adopt the dual-port RAM method for data interaction, reduce the use of relatively complex high-speed data transmission buses, manage the storage space in partitions, and use simple flag bit control to prevent access conflicts without a complex access conflict resolution mechanism.

[0098] Adopt the asynchronous "request-response" mode for data interaction. The FPGA caches the upstream data received, avoiding problems such as data loss caused by differences in data processing rates, and maximizing the integrity of the data and the overall processing efficiency of the system. It has obvious advantages especially for upstream phased bursty data processing and data processing that requires complex algorithms.

[0099] The present invention is applicable to high-speed on-orbit data processing of satellites based on the CPU and the FPGA, and has obvious advantages especially in the on-orbit complex processing of bursty data and the realization of high-speed soft real-time data processing using low-cost processors. It can be extended to other application scenarios and has universality and practicality. This solution has been applied to the on-orbit real-time processing of certain X-ray astronomical observation data of the Tianguan satellite (launched in January 2024), and good results have been obtained. By applying this solution, it is possible to quickly discover effective targets on orbit and conduct observations, improving the timeliness of scientific exploration.

[0100] Although the embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not by way of limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined only by the appended claims and their equivalents.

Claims

1. A satellite on-orbit high-speed data processing system based on CPU + FPGA and supporting asynchronous communication, characterized in that, Including: CUP, FPGA, SRAM, SDRAM, FLASH, FPGA refresh chip and corresponding address and data transmission buses, where FLASH storage and FPGA refresh chip are optional configurations; The system uses a CPU+FPGA dual-processor pipeline method for on-orbit data processing; Among them, the FPGA is configured to mainly receive, unpack and preprocess data; The CPU is configured to mainly perform more complex algorithm processing and floating-point calculations; The SDRAM is configured as a data buffer area for temporarily storing data packets received from the outside, and The SRAM is configured as a running memory area for storing preprocessed data.

2. The satellite on-orbit high-speed data processing system according to claim 1, characterized in that The FPGA receives external data input through an LVDS high-speed data transmission interface; The FPGA is connected to the SRAM and SDRAM through data lines and address lines; The CPU accesses the FPGA through the EMIF interface.

3. The satellite in-orbit high-speed data processing system according to claim 1, characterized in that The FLASH storage and FPGA refresh chip are configured to realize dynamic refresh of the FPGA.

4. The satellite on-orbit high-speed data processing system according to claim 1, characterized in that It further includes system software, and the system software includes FPGA software and CPU software; Among them, the main functional modules of the FPGA software include data reception and verification, data caching, SDRAM read and write control, unpacking and refreshing, SRAM arbitration and read and write control, and data sending; The main functional modules of the CPU software include data request, data reading, data processing, and data output.

5. The satellite on-orbit high-speed data processing system according to claim 1, characterized in that, The system performs partition management on the storage space, including: The data buffer area, located in the SDRAM, is used for the FPGA to cache data packets; The shared storage area, located in the SRAM, can be accessed by both the FPGA and the CPU; The FPGA exclusive memory area is only used for the operation of the FPGA program; The CPU exclusive memory area is only used by the CPU program for large data storage and calculation; Among them, the shared storage area is further divided into: The FPGA data sending area stores the data preprocessed by the FPGA, The CPU data sending area stores the result data after the CPU processing is completed.

6. The satellite on-orbit high-speed data processing system according to claim 5, wherein Use dual-port RAM to share the memory space to achieve high-speed data interaction between the CPU and the FPGA, and both the CPU and the FPGA can access the shared storage area on the SRAM; Among them, the CPU accesses the SRAM of the FPGA through the EM IF interface for data reading and writing; And Adopt a partitioned shared storage design, where data reception and data sending access different address space partitions, set memory read and write control flag bits, and the CPU and the FPGA realize data interaction control by setting and judging relevant flag bits to avoid read and write conflicts.

7. The satellite in-orbit high-speed data processing system according to claim 1, wherein Adopt a caching mechanism, and the FPGA first caches the upstream data received in the SDRAM; Set a cache status flag to identify the status of the cache space; Adopt the first-in-first-out principle for cache space management, and the data processed by the FPGA will release the occupied buffer area; It has the function of instructing or automatically clearing the buffer, and the CPU program has the function of forcibly emptying the cache space as needed.

8. The satellite on-orbit high-speed data processing system according to claim 1, characterized in that, Asynchronous communication is used for data interaction. The data communication between the CUP and the FPGA adopts an asynchronous request refresh mechanism. After the CPU finishes data processing, it sends a data refresh request to the FPGA. The FPGA takes out the data packet from the cache for unpacking and preprocessing, and writes the result into the FPGA transmission data area in the shared memory. The CPU reads it for subsequent processing.

9. The satellite on-orbit high-speed data processing system according to claim 1, wherein The system has the parallel processing ability for multi-channel data. By setting corresponding flag bits and address spaces, the number of parallel processing channels is increased, and the data of each channel does not interfere with each other to achieve parallel processing; It has the expansion ability of multi-core processing mode. By increasing the number of processors, multi-processor parallel processing can be achieved, and the data processing ability of the system can be improved.

10. An asynchronous communication method for high-speed data processing on-orbit of a satellite based on CPU + FPGA, characterized in that, It includes: Asynchronous "request-send" mode is used for data interaction; It includes the following processing processes: data reception and processing stage: The FPGA receives data through the high-speed data transmission interface; The FPGA performs data verification and stores the data packet in the data buffer; When the CPU is idle, it requests new data by writing a specific flag bit in the shared memory area; After the FPGA reads the CPU request, it unpacks and performs related preprocessing on the data packets in the data buffer according to the first-in-first-out principle; The FPGA stores the unpacked data in a specific address space in the shared memory according to the interface protocol and sets the completion flag; After the CPU determines that the FPGA writing is completed, it reads the data from the FPGA transmission data area in the shared memory for subsequent data processing; Processing result sending stage: After the CPU determines that the buffer is empty according to the flag bit, it writes the result data into the data input queue of the FPGA; The FPGA sends it out through the high-speed data transmission interface; Among them, each processing channel is set with an independent flag bit and storage address space, and has the multi-channel data parallel transmission and processing ability.

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