Mutual exclusion lock device based on hardware implementation and control method thereof

Abstract

The present application discloses a hardware-based mutual exclusion lock device and a control method thereof, belonging to the field of data processing technology. The hardware-based mutual exclusion lock device includes: hardware and software, wherein the hardware is connected to the software; the hardware includes: a first register, a second register, and a first counter, wherein the first register is connected to the first counter; the software includes: a lock interface and a release lock interface, wherein the lock interface is connected to the release lock interface, the first register, and the second register, and the release lock interface is connected to the second register. The hardware-based mutual exclusion lock device of the present application can implement a high-speed mutual exclusion scheme for mutual exclusion in different address spaces without the aid of an operating system kernel, thereby meeting the mutual exclusion requirements of different address spaces in high-performance application scenarios such as today's high-speed data forwarding interfaces.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a hardware-based mutual exclusion lock device and a control method thereof. Background Art

[0002] Mutual exclusion is primarily used to protect access to shared resources between different contexts, such as between multiple processes or threads. Generally speaking, when multiple processes or threads collaborate, they need to access one or more shared resources. However, not all threads or processes can access shared resources simultaneously. Simultaneous access can lead to errors and unintended collaboration. Therefore, a mutual exclusion mechanism is necessary to ensure that only one thread or process can access a shared resource at a time. In operating system implementations, existing critical section mutual exclusion mechanisms primarily include semaphores and spinlocks. The basic principle is that shared resource accessors first compete for a semaphore or spinlock. Only one contender can acquire the semaphore or spinlock at a time. The successful contender is considered to have successfully acquired the lock, effectively locking the shared resource. Once the lock is acquired, other contenders are unable to successfully acquire the lock until the successful contender releases the lock. The successfully acquired contender can then safely access the shared resource. Once the access is complete, the lock is released, allowing other contenders to access the shared resource. This achieves the goal of multiple competitors mutually exclusive access to shared resources.

[0003] The aforementioned semaphore and spinlock implementations typically operate within the same address space, such as a process or different threads within the kernel. However, different processes and user and kernel states occupy different address spaces, and direct access between these spaces is prohibited. Therefore, the mutex lock must be placed in kernel state. User-state processes then fall into kernel state through system calls such as ioctl to compete for the semaphore or spinlock lock, achieving mutual exclusion between different address spaces.

[0004] In today's high-concurrency and high-speed data processing scenarios, network interface speeds are high, CPU cores process large numbers of messages, and high performance is a must. Traditional kernel-space mutual exclusion technologies, which rely on kernel space between different address spaces, suffer from poor performance due to the system calls involved in kernel traps, exits, and context switches, and cannot meet the requirements of high-speed data processing and forwarding. While this kernel-space mutual exclusion technology requires kernel traps through the system call interface to contend for locks, and the system call interface involves kernel traps, exits, and context switches, it works well in traditional low-speed applications, but it no longer meets the high-speed requirements of today's data processing and forwarding. Summary of the Invention

[0005] The purpose of this application is to overcome the defects of the prior art and provide a hardware-based mutual exclusion lock device and a control method thereof to meet the high-speed mutual exclusion competition requirements in different address spaces.

[0006] In a first aspect, the present application provides a mutual exclusion lock device based on hardware implementation, comprising: hardware and software, wherein the hardware is connected to the software;

[0007] The hardware includes: a first register, a second register, and a first counter, wherein the first register is connected to the first counter;

[0008] The software includes: a locking interface and a locking release interface, wherein the locking interface is connected to the locking release interface, the first register, and the second register, and the locking release interface is connected to the second register.

[0009] Optionally, the first register is a read-only register, and the second register is a readable and writable register.

[0010] Optionally, the first register includes a first sequence number, and the first sequence number is used to represent a queue sequence number when the software competes for a lock.

[0011] Optionally, the first register atomically obtains the current value of the first counter and adds one to the current value of the first counter; the two tasks of obtaining the current value of the first counter and returning it to the software and adding one to the current value of the first counter are completed by the hardware logic in the implementation of the software reading the first register. For the software, these two tasks are atomic.

[0012] Optionally, the second register includes a second serial number, and the second serial number is used to indicate a serial number of a lock currently allowed to be acquired.

[0013] Optionally, the locking interface reads the first serial number of the first register and the second serial number of the second register, judges the first serial number and the second serial number, and completes the locking; the releasing locking interface obtains the first serial number from the locking interface, adds one to the first serial number, and sends a write request to the second register, and adds one to the first serial number and writes it into the second register.

[0014] Optionally, the software further includes an address mapping interface, which is connected to the release lock interface and the release lock interface respectively, and is used to map the physical addresses of the first register and the second register to the address space in which the software runs.

[0015] In a second aspect, the present application further provides a method for controlling a hardware-based mutual exclusion lock device, which is used to control the hardware-based mutual exclusion lock device described in any one of the first aspects, comprising the following steps:

[0016] Initializing the first register, the second register, and the first counter;

[0017] Mapping the physical addresses of the first register and the second register to an address mapping interface of software;

[0018] When acquiring the lock, the software sends a read request to the first register through the lock interface to obtain the first serial number of the first register; the lock interface sends a read request to the second register to obtain the second serial number of the second register, and the first serial number and the second serial number are compared to complete the lock;

[0019] When releasing the lock, the lock release interface obtains the first sequence number from the lock interface, increases the obtained first sequence number by one, and sends a write request to the second register; the second register receives the write request, performs a write operation, and completes the lock release.

[0020] Optionally, when acquiring the lock, the software sends a read request to the first register through the lock interface to obtain the first serial number of the first register; the lock interface sends a read request to the second register to obtain the second serial number of the second register, and the first serial number and the second serial number are judged to complete the locking, including:

[0021] sending a read request to the first register via the locking interface;

[0022] The first register receives the read request, obtains the value of the first counter, and increases the value of the first counter by one;

[0023] The first register uses the acquired value of the first counter as a first serial number, and returns the first serial number to the locking interface;

[0024] The locking interface sends a read request to the second register to obtain a second serial number of the second register;

[0025] The first serial number is compared with the second serial number. If the first serial number is the same as the second serial number, locking is completed. If the first serial number is different from the second serial number, waiting and repeatedly reading the second serial number until the obtained second serial number is equal to the first serial number, locking is completed.

[0026] Optionally, when releasing the lock, the lock release interface obtains the first sequence number from the lock interface, increments the obtained first sequence number by one, and sends a write request to the second register; the second register receives the write request, performs a write operation, and completes the lock release, including:

[0027] Release the lock interface to obtain a first serial number, increase the obtained first serial number by one, and send a write request to the second register;

[0028] The second register receives the write request and determines whether the written value is equal to the current value of the second register plus one. If not, the write request is discarded and the current value of the second register remains unchanged. If the written value is equal to the current value of the second register plus one, the write operation is performed to update the value of the second register.

[0029] After the second register completes the write operation, the lock release interface returns a status code indicating that the lock is successfully released, thereby achieving lock release.

[0030] The present application provides a hardware-based mutual exclusion lock device and a control method thereof, which avoids interference and realizes fast mutual exclusion lock by setting two registers and arranging them for queued access; ensures the uniqueness and orderliness of the sequence numbers during multi-threaded competition by setting a first sequence number and a second sequence number; and directly maps the physical address of the register to different software spaces so that software running in different address spaces can directly access the register, and no longer needs to trap into the kernel through system calls to complete locking and unlocking, thereby reducing the overhead caused by context saving and refilling during context switching, reducing the performance impact caused by cache invalidation due to context switching, and reducing performance jitter during CPU operation, providing a low-latency, highly reliable mutual exclusion solution for high-speed data processing and multi-process high-performance scenarios.

[0031] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a schematic structural diagram of a hardware-implemented mutual exclusion lock device provided in one embodiment of the present application.

[0034] Figure 2 This is a flowchart of a method for controlling a hardware-implemented mutual exclusion lock device provided in another embodiment of the present application.

[0035] Figure 3 This is a flowchart of step S3 in a method for controlling a mutual exclusion lock device based on hardware implementation provided in another embodiment of the present application.

[0036] Figure 4This is a flowchart of the sequence number request register read operation in step S32 of the control method of the hardware-based mutual exclusion lock device provided in another embodiment of the present application.

[0037] Figure 5 This is a flowchart of step S4 in a method for controlling a mutual exclusion lock device based on hardware implementation provided in another embodiment of the present application.

[0038] Figure 6 This is a flowchart of the sequence number confirmation register write operation in step S42 of the control method of the hardware-based mutual exclusion lock device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0039] To make the purpose and technical solutions of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] In one embodiment, see Figure 1 The present application provides a mutual exclusion lock device based on hardware implementation, which may include: hardware 1 and software 2, and the hardware 1 is connected to the software 2; the hardware 1 includes a sequence request register (Token-Require register) 11, a sequence confirmation register (Token-Current register) 12, and a sequence counter (sequence counter) 13, and the sequence request register 11 is connected to the sequence counter 13; the software 2 includes a locking interface 21 and a releasing locking interface 22, and the locking interface 21 is connected to the releasing locking interface 22, the sequence request register 11, and the sequence confirmation register 12, and the releasing locking interface 22 is connected to the sequence confirmation register 12.

[0041] As an example, the sequence number request register 11 may be a read-only register to limit the operating authority of the software 2 on the sequence number request register 11 , thereby preventing malicious software from tampering with the sequence number request register 11 .

[0042] As an example, the sequence number request register 11 includes a first queue sequence number Require-ID, which is used to indicate the sequence number when the software competes for a lock. The first queue sequence number Require-ID may be unique and self-incrementing.

[0043] As an example, the sequence number request register 11 is used to obtain the current value of the sequence number counter 13 , use the current value of the sequence number counter 13 as the first queue sequence number Require-ID of the sequence number request register 11 , and output the first queue sequence number Require-ID to the software 2 .

[0044] For example, when Software 2 acquires a lock, it reads Sequence Request Register 11, which obtains the current value of Sequence Counter 13 and increments it by one. Sequence Request Register 11 then returns the current value of Sequence Counter 13 to Software 2 as the first queue sequence number Require-ID. This first queue sequence number Require-ID is unique. Software 2 obtains the unique first queue sequence number Require-ID value by reading Sequence Request Register 11 without directly manipulating Sequence Counter 13. This ensures the atomicity and efficiency of the read mechanism while simplifying the development complexity of Software 2.

[0045] As an example, the sequence number request register 11 obtains the current value of the sequence number counter 13 and adds one to the value of the sequence number counter 13. These two tasks are completed by the hardware logic in the implementation of the software 2 reading the sequence number request register 11. For software 2, these two tasks are atomic, that is, the two operations are inseparable. Each time the sequence number request register 11 obtains the current value of the sequence number counter 13, it will immediately add one to the value of the sequence number counter 13 to ensure the uniqueness and orderliness of the generated first queue sequence number Require-ID value. Software 2 can only obtain the first queue sequence number Require-ID value through a read operation, and the increment of the sequence number counter 13 is automatically completed by the sequence number request register 11 without the intervention of software 2. Even in a multi-processor / multi-thread concurrent request scenario, the sequence number request register 11 will ensure that each read operation returns a unique, incrementing first queue sequence number Require-ID, avoiding duplication or competition conditions of the first queue sequence number Require-ID.

[0046] As an example, the serial number confirmation register 12 can be a readable and writable register to achieve the correct locking and releasing of the lock, so that the software 2 can directly operate the serial number confirmation register 12 without the help of the operating system kernel, avoiding the context switching caused by the system call, and making the mutual exclusion lock mechanism adaptable to high-speed data processing scenarios, thereby improving the overall performance of the system in multi-process high-performance application scenarios.

[0047] As an example, the sequence number confirmation register 12 is used to store the second queue sequence number Current-ID value currently allowed to acquire the lock, which is the value of the sequence number confirmation register 12. The second queue sequence number Current-ID is used to indicate the queue sequence number currently allowed to acquire the lock.

[0048] As an example, the sequence number confirmation register 12 inputs the value written by the software 2 when releasing the lock, and outputs the currently stored second queue sequence number Current-ID value.

[0049] As an example, when the sequence number confirmation register 12 performs a write operation, the sequence number confirmation register 12 needs to determine whether the written value is equal to the current value of the second queue sequence number Current-ID of the sequence number confirmation register 12 plus one. If the written value is equal to the current value of the second queue sequence number Current-ID of the sequence number confirmation register 12 plus one, the write operation is performed, and the value of the sequence number confirmation register 12 is updated to the written value, that is, updated to the current second queue sequence number Current-ID value of the sequence number confirmation register 12 plus one; if the written value is any other value, the write request is discarded, and the second queue sequence number Current-ID value of the sequence number confirmation register 12 remains unchanged. This can prevent the sequence number confirmation register 12 from being maliciously rewritten to a certain extent.

[0050] As an example, when software 2 releases the lock, software 2 adds one to the first queue sequence number Require-ID value obtained from the sequence number request register 11 and writes it into the sequence number confirmation register 12. The sequence number confirmation register 12 checks the written value. If the written value is equal to the current value of the second queue sequence number Current-ID of the sequence number confirmation register 12 plus one, the second queue sequence number Current-ID value is updated to obtain a new second queue sequence number Current-ID value. The new second queue sequence number Current-ID value is equal to the first queue sequence number Require-ID value plus one, that is, the original second queue sequence number Current-ID plus one.

[0051] As an example, the access speed of the sequence number request register 11 and the sequence number confirmation register 12 is very fast, much faster than memory access, making it faster than semaphore spin lock access implemented by relying on memory variables.

[0052] As an example, the sequence number counter 13 is bound to the sequence number request register 11 to provide the sequence number request register 11 with a unique first queue sequence number Require-ID value, ensuring the mutually exclusive access order, ensuring the sequentiality of lock requests, the fairness of lock competition, the correctness of lock release, and the orderliness of lock competition.

[0053] For example, when sequence number counter 13 receives a read request from sequence number request register 11, it outputs the current value of sequence number counter 13 to sequence number request register 11. After the read operation is completed, the current value of sequence number counter 13 is automatically incremented by one, achieving automatic updating. This ensures that each read operation produces a unique and increasing value, thereby ensuring the sequentiality and uniqueness of the first queue sequence number Require-ID value.

[0054] As an example, the hardware 1 may be a chip.

[0055] As an example, access requests to the sequence request register 11 and the sequence confirmation register 12 are always queued serially, and the access requests will not be discarded or concurrent within the hardware 1 to ensure the accuracy and orderliness of data access to the sequence request register 11 and the sequence confirmation register 12.

[0056] As an example, the initial values of the sequence number request register 11 , the sequence number confirmation register 12 , and the sequence number counter 13 are all zero.

[0057] As an example, the locking interface 21 is used to read the first queue sequence number Require-ID value of the sequence number request register 11 and the second queue sequence number Current-ID value of the sequence number confirmation register 12, and completes the locking by judging the first queue sequence number Require-ID value and the second queue sequence number Current-ID value, and returns the "locked successfully" status.

[0058] As an example, the lock interface 21 reads the first queue sequence number Require-ID value from the sequence number request register 11 atomically, and the lock interface 21 reads the first queue sequence number Require-ID value from the sequence number request register 11 cyclically. Specifically, the lock interface 21 reads the first queue sequence number Require-ID value from the sequence number request register 11 and the second queue sequence number Current-ID value from the sequence number confirmation register 12, and compares the first queue sequence number Require-ID value with the second queue sequence number Current-ID value. If the first queue sequence number Require-ID value and the second queue sequence number Current-ID value are the same, locking is completed. If the first queue sequence number Require-ID value and the second queue sequence number Current-ID value are different, the lock interface 21 waits and repeatedly reads the second queue sequence number Current-ID value until the obtained second queue sequence number Current-ID value equals the first queue sequence number Require-ID value, and locking is completed.

[0059] As an example, the locking interface 21 can also be used to send the first queue sequence number Require-ID value to the release lock interface 22, so that the release operation does not rely on re-reading the sequence number request register 11, but directly uses the sequence number saved when locking, ensuring consistency with the operating logic of the register in the hardware, ensuring that the acquisition and release of the lock are completed by the same entity, avoiding accidental release, and reducing one hardware interaction and delay.

[0060] As an example, the lock release interface 22 is used to atomically update the sequence number confirmation register 12 to release the acquired lock resources, efficiently and safely release the lock resources, and ensure concurrency correctness and performance optimization.

[0061] As an example, the release lock interface 22 obtains the first queue sequence number Require-ID value from the lock interface 21, adds one to the first queue sequence number Require-ID value, and then sends a write request to the sequence number confirmation register 12, and writes the first queue sequence number Require-ID value plus one into the sequence number confirmation register 12. After receiving the write request, the sequence number confirmation register 12 determines whether the value after adding one to the first queue sequence number Require-ID value is equal to the current second queue sequence number Current-ID value plus one in the sequence number confirmation register 12. If they are equal, the current value of the second queue sequence number Current-ID in the sequence number confirmation register 12 is updated to the value after adding one to the written first queue sequence number Require-ID value, obtaining a new second queue sequence number Current-ID value, completing the lock release and returning; if they are not equal, the write request is discarded, and the second queue sequence number Current-ID value in the sequence number confirmation register 12 remains unchanged.

[0062] As an example, the locking interface 21 and the locking release interface 22 may be implemented through codes.

[0063] As an example, software 2 may further include an address mapping interface (not shown), which is connected to the operating system's standard interface, the lock release interface, and the lock release interface, and is used to map the physical addresses of sequence request register 11 and sequence confirmation register 12 to the address space in which the software is running. Specifically, the physical addresses of sequence request register 11 and sequence confirmation register 12 are mapped to the address space in which the software is running via the operating system's standard interface through the address mapping interface of software 2. This allows software 2 to directly access hardware 1 through a pointer, without requiring kernel transit, thereby providing high-speed, kernel-free mutual exclusion capabilities for different address spaces with mutual exclusion requirements.

[0064] For example, mutually exclusive address spaces refer to independent virtual memory spaces that require mutually exclusive access to shared resources. These can include user-mode memory spaces of different processes, user-mode and kernel-mode memory spaces, and the memory spaces of different cores in a multi-core processor. By mapping registers in hardware 1 to these mutually exclusive address spaces through the operating system, software 2 can directly operate on the registers to achieve high-speed mutual exclusion, avoiding the performance bottlenecks associated with traditional kernel relays.

[0065] For example, different operating systems have different standard interfaces and parameter settings, which can be selected based on actual conditions, such as the mmap function in Linux and the CreateFile, DeviceIoControl, MapPhysicalMemory, and ioremap functions in Windows.

[0066] The above-mentioned hardware-based mutual exclusion lock device is simple to implement, and realizes fast mutual exclusion lock by setting two queue access registers; atomically reads and increments the sequence counter through the sequence request register to generate a unique first queue sequence number Require-ID, ensuring the uniqueness and orderliness of the sequence number during multi-thread competition; verifies the write operation through the sequence confirmation register, and only allows legal writes that increase the current value by one, which can ensure the correctness of the lock release and resist malicious tampering; directly maps the register physical address to the address space of different software through the address mapping interface, and can directly access the register in the address space. It is no longer necessary to trap into the kernel through a system call to complete locking and unlocking, reducing the overhead caused by context saving and refilling during context switching, reducing the performance impact caused by cache failure due to context switching, and reducing performance jitter during CPU operation, providing a low-latency, highly reliable mutual exclusion solution for high-speed data processing and multi-process high-performance scenarios.

[0067] In another embodiment, see Figure 2 The present application also provides a method for controlling a mutual exclusion lock device based on hardware implementation, which may include the following steps: step S1 to step S4.

[0068] Step S1: Initialize the sequence number request register, sequence number confirmation register and sequence number counter.

[0069] Step S2: Mapping the physical addresses of the sequence number request register and the sequence number confirmation register to the address space where the software runs through the address mapping interface.

[0070] Step S3: When acquiring the lock, the software sends a read request to the sequence request register through the locking interface to obtain the first queue sequence number Require-ID value of the sequence request register; the locking interface sends a read request to the sequence confirmation register to obtain the second queue sequence number Current-ID value of the sequence confirmation register, and judges the first queue sequence number Require-ID value and the second queue sequence number Current-ID value to complete the locking.

[0071] Step S4: When releasing the lock, the lock release interface obtains the first queue sequence number Require-ID value from the lock interface, adds one to the obtained first queue sequence number Require-ID value, and sends a write request to the sequence number confirmation register; the sequence number confirmation register receives the write request, performs the write operation, and completes the lock release.

[0072] In the control method of the hardware-based mutual exclusion lock device of the present application, the consistency and reliability of the initial state of the mutual exclusion lock are ensured through the initialization operation, providing an orderly starting point for subsequent operations; the physical address of the register is mapped to the address space of the software through the address mapping interface, so that the software can directly access the register of the hardware, avoiding the context switching overhead of the kernel system call, and laying the foundation for high-speed mutual exclusion access; the unique first queue sequence number Require-ID value is obtained from the sequence request register through the locking interface, ensuring the uniqueness and orderliness of the lock request sequence number during multi-thread competition; the second queue sequence number Current-ID value of the sequence confirmation register is updated through the release lock interface to realize the release of the lock and ensure the security of the release operation. The method of the present application realizes high-speed mutual exclusion without kernel transit, can reduce the delay of lock acquisition and release, improve the concurrency efficiency in multi-process and multi-address space scenarios, and effectively meet the demand of high-speed data processing for low-latency mutual exclusion mechanism.

[0073] In step S1, see Figure 2 In step S1, the sequence number request register, the sequence number confirmation register and the sequence number counter are initialized.

[0074] As an example, the sequence number request register, sequence number confirmation register and sequence number counter are initialized, and the initial values of the sequence number request register, sequence number confirmation register and sequence number counter are set to zero, that is, the initial values of the first queue sequence number Require-ID and the second sequence number Current-ID are both zero, which provides a reliable initial condition for subsequent lock acquisition and release operations, and ensures the correctness and stability of the mutual exclusion lock mechanism.

[0075] In step S2, see Figure 2 In step S2, the physical addresses of the sequence request register and the sequence confirmation register are mapped to the address space of the software through the address mapping interface.

[0076] As an example, the physical addresses of the serial request register and the serial confirmation register are mapped to the address space in the software by operating the address mapping interface to establish a direct communication channel between the software and the registers in the hardware, so that the software can directly access the registers in the hardware through pointers without going through the kernel, thereby improving the interaction efficiency between the software and hardware, reducing the call overhead and context switching time, and providing high-speed, kernel-free mutual exclusion capabilities for different address spaces with mutual exclusion requirements.

[0077] As an example, the address mapping interface may adopt a standard interface of the system. Different operating systems have different standard interfaces and parameter settings, and the standard interface and parameter settings may be selected according to actual conditions.

[0078] In step S3, see Figure 2 In step S3, when acquiring the lock, the software sends a read request to the sequence request register through the locking interface to obtain the first queue sequence number Require-ID value of the sequence request register; the locking interface sends a read request to the sequence confirmation register to obtain the second queue sequence number Current-ID value of the sequence confirmation register, and judges the first queue sequence number Require-ID value and the second queue sequence number Current-ID value to complete the locking.

[0079] As an example, see Figure 3 , step S3 may include the following steps: step S31 to step S35.

[0080] Step S31: Send a read request to the sequence number request register through the locking interface.

[0081] Step S32: The sequence number request register receives the read request, obtains the value of the sequence number counter, and increases the value of the sequence number counter by one.

[0082] Step S33: the sequence number request register uses the obtained value of the sequence number counter as the first queue sequence number Require-ID value, and returns the first queue sequence number Require-ID value to the locking interface.

[0083] Step S34: the locking interface sends a read request to the sequence number confirmation register to obtain the second queue sequence number Current-ID value of the sequence number confirmation register.

[0084] Step S35: Compare the Require-ID value of the first queue number with the Current-ID value of the second queue number. If the Require-ID value of the first queue number is the same as the Current-ID value of the second queue number, the lock is completed. If the Require-ID value of the first queue number is different from the Current-ID value of the second queue number, wait and repeatedly read the Current-ID value of the second queue number until the Current-ID value of the second queue number is equal to the Require-ID value of the first queue number, and the lock is completed.

[0085] As an example, in step S31, when acquiring the lock, the software calls the lock interface and sends a read request to the sequence request register in the hardware through the lock interface to obtain a unique sequence number for subsequent lock contention judgment.

[0086] As an example, see Figure 4 In step S32, the sequence request register receives the read request from the locking interface, initiates a read operation to the sequence counter, obtains the current value of the sequence counter, adds one to the current value of the sequence counter, and realizes automatic update of the sequence counter.

[0087] As an example, the sequence request register obtains the current value of the sequence counter and adds one to the value of the sequence counter atomically, so as to ensure the uniqueness and orderliness of the generated value of the first queue sequence number Require-ID.

[0088] As an example, in step S33, the current value of the sequence number counter is saved to the sequence number request register as the first queue sequence number Require-ID value, that is, the first queue sequence number Require-ID value is updated with the obtained value of the sequence number counter, and the sequence number request register returns the first queue sequence number Require-ID value to the locking interface.

[0089] As an example, the value of the sequence number counter is always 1 greater than the value of the first queue sequence number Require-ID of the sequence number request register.

[0090] As an example, in step S34, the software sends a read request to the sequence number confirmation register through the lock interface to obtain the sequence number currently allowed to acquire the lock stored in the sequence number confirmation register, that is, obtains the value of the second queue sequence number Current-ID.

[0091] As an example, in step S35, the locking interface compares the Require-ID value of the first queue sequence number with the Current-ID value of the second queue sequence number. If the Require-ID value of the first queue sequence number is the same as the Current-ID value of the second queue sequence number, the right to use the lock is obtained and the lock is successfully locked. If the Require-ID value of the first queue sequence number is different from the Current-ID value of the second queue sequence number, the lock is currently held by other software and enters a spin-wait state. The locking interface continuously sends read requests to the sequence number confirmation register to obtain the latest Current-ID value of the second queue sequence number. After each read, the new Current-ID value of the second queue sequence number is immediately compared with the Require-ID value of the first queue sequence number until the obtained Current-ID value of the second queue sequence number is equal to the Require-ID value of the first queue sequence number, and the lock is successfully locked.

[0092] Furthermore, after the lock is successfully acquired, the lock interface can return a non-zero value indicating that the lock is successfully acquired.

[0093] As an example, when the software returns a non-zero value from the lock interface, it indicates that the software successfully competes for the lock and can initiate access to the critical section and perform read and write operations on the shared resource.

[0094] As an example, the lock interface may return 1 to indicate that the lock is complete.

[0095] As an example, during the spin wait process, the thread will not be suspended, that is, no kernel scheduling is required, but it will continue to send read requests to the sequence confirmation register to ensure low-latency response to lock release events.

[0096] In step S4, see Figure 2 In step S4, when the lock is released, the lock release interface obtains the first queue sequence number Require-ID value from the lock interface, increases the obtained first queue sequence number Require-ID value by one, and sends a write request to the sequence number confirmation register; the sequence number confirmation register receives the write request, performs the write operation, and completes the lock release.

[0097] As an example, see Figure 5 , step S4 may include the following steps: step S41 to step S43.

[0098] Step S41: releasing the locking interface to obtain the first queue sequence number Require-ID value, adding one to the obtained first queue sequence number Require-ID value, and sending a write request to the sequence number confirmation register.

[0099] Step S42: The sequence number confirmation register receives a write request and determines whether the written value is equal to the current value of the second queue sequence number Current-ID of the sequence number confirmation register plus one. If they are not equal, the write request is discarded and the current value of the second queue sequence number Current-ID of the sequence number confirmation register remains unchanged; if the written value is equal to the current value of the second queue sequence number Current-ID of the sequence number confirmation register plus one, the write operation is performed to update the value of the second queue sequence number Current-ID of the sequence number confirmation register.

[0100] Step S43: After the serial number confirmation register completes the write operation, the lock release interface returns a status code indicating that the lock is successfully released, thereby achieving lock release.

[0101] As an example, in step S41, after accessing the critical section, the software needs to release the lock to allow the software to continue locking the critical section. The software obtains the currently held first queue sequence number Require-ID value from the lock interface through the release lock interface, increments the obtained first queue sequence number Require-ID value by one to obtain a new first queue sequence number Require-ID value, and sends a write request to the sequence number confirmation register to write the new first queue sequence number Require-ID value to the sequence number confirmation register.

[0102] As an example, see Figure 6 In step S42, the sequence number confirmation register receives the write request and determines whether the written first queue sequence number Require-ID is equal to the current value of the second queue sequence number Current-ID in the sequence number confirmation register plus one. If the written first queue sequence number Require-ID value is not equal to the current value of the second queue sequence number Current-ID plus one, the sequence number confirmation register refuses to perform the write operation, discards the current write request, keeps the current second queue sequence number Current-ID unchanged, and returns an error status code to the software; if the written first queue sequence number Require-ID value is equal to the current value of the second queue sequence number Current-ID in the sequence number confirmation register plus one, the write operation is performed, the first queue sequence number Require-ID value is written to the sequence number confirmation register, and the second queue sequence number Current-ID value in the current sequence number confirmation register is updated.

[0103] As an example, a refusal to write to the sequence confirmation register can indicate an illegal release, where someone other than the lock holder attempts to release the lock; a duplicate release, where the lock holder releases the same lock multiple times; or a concurrency conflict, where multiple threads attempt to release the lock simultaneously.

[0104] As an example, when the software writes to the sequence number confirmation register, the written value must be equal to the current value of the first queue sequence number Require-ID of the sequence number confirmation register plus one, because the locking condition is that the first queue sequence number Require-ID value is equal to the second queue sequence number Current-ID value.

[0105] As an example, in step S43, after the sequence number confirmation register is successfully updated, it sends a write completion signal to the lock release interface, indicating that the write operation has been completed atomically. The lock release interface returns a status code to the caller, that is, the lock release interface returns a status code indicating successful lock release to the software, thus releasing the lock.

[0106] As an example, after the serial number confirmation register completes the write operation, if there is a lock interface in spin waiting in step S35, the lock interface will end the spin waiting and successfully acquire the lock.

[0107] For example, since the Require-ID value of the first queue sequence number in the sequence request register always returns the current value of the sequence counter and increments the sequence counter by 1 when the software reads it, other competitors (i.e., other software) will inevitably increment the queue sequence number value by 1 when they read it. After the software that successfully locked the lock releases the lock, the Current-ID value of the second queue sequence number in the sequence confirmation register will also be updated to the original Current-ID value of the second queue sequence number plus 1. Therefore, after the lock is released, the next competitor whose first queue sequence number Require-ID value is 1 greater than that of the competitor that successfully locked the lock (i.e., the software that successfully locked the lock) can definitely complete the lock. And so on, continuously implementing mutual exclusion service.

[0108] In one example, consider a restaurant with a single pick-up window. Each competitor attempting to acquire the lock is assigned a queue number at the pick-up window. This queue number increments by 1, so different competitors will receive different queue numbers. The sequence request register and the sequence counter together ensure that each competitor is assigned a unique queue number. Once the queue number is assigned, the call phase begins. The pick-up window calls out the numbers sequentially, and only competitors whose numbers are called can pick up their food. Those whose numbers are not called must wait, thus ensuring orderly service for all competitors. The call is accomplished through the sequence confirmation register. The initial values of the sequence request register and the sequence confirmation register are 0. Therefore, the first competitor to obtain a queue number will receive a Require-ID value of 0 for the first queue number and a Current-ID value of 0 for the second queue number. This successfully locks the lock and allows safe access to the critical section. The second competitor to obtain a number will obtain a first-queue sequence number Require-ID value of 1. However, before the first competitor releases the lock, the second competitor will always read a second-queue sequence number Current-ID value of 0. Therefore, the second competitor can only spin and wait and repeatedly read the sequence confirmation register until the first competitor releases the lock. When the first competitor releases the lock, it will add 1 to its first-queue sequence number Require-ID value and write it into the sequence confirmation register. The judgment logic of the sequence confirmation register will judge the write operation. Only if it meets the write conditions of the sequence confirmation register can the write be successful. After the write is successful, the second-queue sequence number Current-ID value of the sequence confirmation register will become 1. At this time, if the second competitor repeatedly reads the sequence confirmation register, it will read the second-queue sequence number Current-ID value as 1, and its first-queue sequence number Require-ID value is also 1. At this time, it will complete the lock and can safely access the critical section. Similarly, other competitors that obtain other first-queue sequence number Require-ID values will wait in line until the first-queue sequence number Require-ID value is equal to the second-queue sequence number Current-ID value before acquiring the lock. Only after acquiring the lock can they access the critical section.

[0109] In the control method of the hardware-based mutual exclusion lock device of the present application, by directly mapping the physical address of the register to the address space of the software, the register can be directly accessed locally, and it is no longer necessary to trap into the kernel through a system call to complete locking and unlocking, thereby reducing the overhead caused by context preservation and refilling during frequent context switching, reducing the performance impact caused by cache invalidation due to frequent context switching, reducing performance jitter during CPU operation, and building a high-speed mutual exclusion access channel; obtaining the unique first queue sequence number Require-ID from the sequence request register through the locking interface, ensuring the uniqueness and orderliness of the lock request sequence number during multi-thread competition; releasing the lock by updating the second queue sequence number Current-ID of the sequence confirmation register through the release locking interface, effectively preventing problems such as illegal release and repeated release, and ensuring the security of the release operation. The method of the present application realizes high-speed mutual exclusion without kernel transit, can greatly reduce the delay of lock acquisition and release, significantly improve the concurrency efficiency in multi-process and multi-address space scenarios, and effectively meet the stringent requirements of high-speed data processing for low-latency mutual exclusion mechanism.

[0110] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The order of execution of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0111] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] Although the present application has been disclosed above with reference to the embodiments, they are not intended to limit the present application. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope of the appended patent application.

Claims

1. A mutual exclusion lock device based on hardware implementation, characterized in that: include: Hardware and software, the hardware is connected to the software; The hardware includes: a first register, a second register, and a first counter, wherein the first register is connected to the first counter; The software includes: a locking interface and a locking release interface, wherein the locking interface is connected to the locking release interface, the first register, and the second register, and the locking release interface is connected to the second register; The first register includes a first sequence number, which is used to represent a queue sequence number when the software competes for a lock; the first register is used to obtain a current value of a first counter, use the current value of the first counter as the first sequence number of the first register, and output the first sequence number to the software; when the software acquires the lock, the first register is read, the first register obtains the current value of the first counter, and the value of the first counter is incremented by one, and the first register returns the read current value of the first counter to the software as the first sequence number; The second register includes a second sequence number, the second sequence number is used to indicate the queue sequence number currently allowed to acquire the lock, and the second register is used to store the second sequence number value currently allowed to acquire the lock; when the software releases the lock, the software increments the first sequence number value obtained from the first register by one and writes the value to the second register; the second register checks the written value, and if the written value is equal to the current value of the second sequence number of the second register plus one, the second sequence number value is updated to obtain a new second sequence number value, and the new second sequence number value is equal to the first sequence number value plus one; The locking interface reads the first sequence number value of the first register and the second sequence number value of the second register, compares the first sequence number value with the second sequence number value, and completes the locking if the first sequence number value and the second sequence number value are the same; if the first sequence number value and the second sequence number value are different, waits and repeatedly reads the second sequence number value until the obtained second sequence number value is equal to the first sequence number value, and completes the locking; The release lock interface obtains the first serial number value from the lock interface, adds one to the first serial number value and sends a write request to the second register, adds one to the first serial number value and writes it to the second register. The second register receives the write request and determines whether the value after adding one to the first serial number value is equal to the current second serial number value of the second register plus one. If they are equal, the current value of the second serial number in the second register is updated to the value after adding one to the written first serial number value to obtain a new second serial number value, complete the lock release and return. If they are not equal, the write request is discarded and the second serial number value of the second register remains unchanged.

2. The hardware-based mutual exclusion lock device according to claim 1, characterized in that: The first register is a read-only register, and the second register is a readable and writable register.

3. The hardware-based mutual exclusion lock device according to claim 2, characterized in that: The first register atomically obtains a current value of a first counter and increases the current value of the first counter by one.

4. The hardware-based mutual exclusion lock device according to claim 1, characterized in that: The software further includes an address mapping interface for mapping the physical addresses of the first register and the second register to the address space in which the software runs.

5. A control method for a hardware-based mutual exclusion lock device, characterized in that: The method for controlling a hardware-based mutual exclusion lock device according to any one of claims 1 to 4 comprises the following steps: Initializing the first register, the second register, and the first counter; Mapping the physical addresses of the first register and the second register to the address space where the software runs through an address mapping interface; When acquiring the lock, the software sends a read request to the first register through the lock interface to obtain the first serial number of the first register; the lock interface sends a read request to the second register to obtain the second serial number of the second register, and the first serial number and the second serial number are compared to complete the lock; When releasing the lock, the lock release interface obtains the first sequence number from the lock interface, increases the obtained first sequence number by one, and sends a write request to the second register; the second register receives the write request, performs a write operation, and completes the lock release.

6. The control method of the hardware-based mutual exclusion lock device according to claim 5, characterized in that: When acquiring the lock, the software sends a read request to the first register through the lock interface to obtain the first serial number of the first register; the lock interface sends a read request to the second register to obtain the second serial number of the second register, and the first serial number and the second serial number are judged to complete the locking, including: sending a read request to the first register via the locking interface; The first register receives the read request, obtains the value of the first counter, and increases the value of the first counter by one; The first register uses the acquired value of the first counter as a first serial number, and returns the first serial number to the locking interface; The locking interface sends a read request to the second register to obtain a second serial number of the second register; The first serial number is compared with the second serial number. If the first serial number is the same as the second serial number, locking is completed. If the first serial number is different from the second serial number, waiting and repeatedly reading the second serial number until the obtained second serial number is equal to the first serial number, locking is completed.

7. The control method of the hardware-based mutual exclusion lock device according to claim 5, characterized in that: When releasing the lock, the lock release interface obtains the first sequence number from the lock interface, increases the obtained first sequence number by one, and sends a write request to the second register; The second register receives the write request, performs a write operation, and completes the lock release, including: Release the lock interface to obtain a first serial number, increase the obtained first serial number by one, and send a write request to the second register; The second register receives the write request and determines whether the written value is equal to the current value of the second register plus one. If not, the write request is discarded and the current value of the second register remains unchanged. If the written value is equal to the current value of the second register plus one, the write operation is performed to update the value of the second register. After the second register completes the write operation, the lock release interface returns a status code indicating that the lock is successfully released, thereby achieving lock release.

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