Apparatus for processing log data, method of operating same, and system including same

Abstract

A log processing apparatus for processing log data, an operating method thereof, and a system including the log processing apparatus are presented. The log processing apparatus includes an internal memory for storing log data and an internal processor for processing the log data. The operation method for processing log data includes: receiving log data from at least one storage device; storing the received log data; generating fault analysis data by performing fault analysis on the log data; and transmitting the fault analysis data to the host device.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0003111, filed on January 8, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present technical field relates to a processing device, and more particularly, to a device for processing logs, an operation method thereof, and a system including the device. Background art

[0004] Semiconductor memories are classified into volatile memories and non - volatile memories. Volatile memories (such as SRAM, DRAM, etc.) lose stored data when the power is cut off, and non - volatile memories (such as flash memories, PRAM, MRAM, RRAM, FRAM, etc.) retain stored data even when the power is cut off.

[0005] As storage systems become more integrated and miniaturized, fault analysis and prediction may become important, and the importance of predictive maintenance using log data from storage devices may increase. However, the process of collecting and analyzing long - term log data imposes a great burden on existing hosts. Summary of the invention

[0006] The present disclosure describes a device for processing log data, an operation method thereof, and a system including the device.

[0007] According to an example, there is provided an operation method of a log processing device, the log processing device including an internal memory for storing log data and an internal processor for processing log data, the operation method including: receiving log data from at least one storage device, storing the received log data, generating fault analysis data by performing fault analysis on the log data, and transmitting the fault analysis data to a host device.

[0008] According to other examples, there is provided a log processing device for processing log data, the log processing device including: an internal memory configured to store log data received from at least one storage device; and an internal processor configured to perform fault analysis on the log data and generate fault analysis data, wherein the log processing device transmits the fault analysis data to a host device.

[0009] According to other examples, a system is provided that includes at least one storage device for storing data, a host device, and a log processing device for processing log data. The log processing device includes an internal memory configured to store log data received from the at least one storage device and an internal processor configured to perform a failure analysis on the log data and generate failure analysis data. The log processing device transmits the failure analysis data to the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Implementations will be understood more clearly from the following detailed description in conjunction with the accompanying drawings. In

[0011] the drawings:

[0012] Figure 1 is a block diagram of a host-storage system including a log processing device according to an implementation;

[0013] Figure 2 is a block diagram of a host-storage system including a log processing device according to an implementation;

[0014] Figure 3 is a flowchart of an operation method of a log processing device according to an implementation;

[0015] Figure 4 is a flowchart of an operation method of a log processing device according to an implementation;

[0016] Figure 5A and Figure 5B is a detailed flowchart of an operation method of a log processing device according to an implementation;

[0017] Figure 6 is a flowchart of an operation method of a log processing device according to an implementation;

[0018] Figure 7 is a flowchart of an operation method of a log processing device according to an implementation;

[0019] Figure 8 is a flowchart of an operation method of a log processing device according to an implementation;

[0020] Figure 9 is a flowchart of an operation method of a log processing device according to an implementation;

[0021] Figure 10 is a block diagram of a system applying a storage device according to an implementation;

[0022] Figure 11 is a block diagram of a data center applying a storage device according to an implementation; and

[0023] Figure 12A cross-sectional view of a BVNAND structure applicable to a storage device according to an implementation. Detailed implementation

[0024] Hereinafter, the implementation will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 A block diagram of a host-storage system 10 including a log processing device 200 according to an implementation.

[0026] Referring to Figure 1 , the host-storage system 10 may include a host 100, a log processing device 200, and at least one storage device 300 and 400. The host-storage system 10 is shown herein as including two storage devices, but this is merely an example. The host-storage system 10 may include a different number of storage devices.

[0027] The host 100 may control data processing operations of at least one storage device 300 and 400, for example, a data read operation or a data write operation. The host 100 may refer to a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, or an application processor (AP). The host 100 may run an operating system (OS) and / or various applications. In an implementation, the host-storage system 10 may be included in a mobile device, and the host 100 may be implemented as an AP. In some implementations, the host 100 may be implemented as a system on chip (SoC) and thus may be embedded in an electronic device.

[0028] The host 100 may include an interface (I / F) circuit 110 and a host controller 120. In addition, although not shown, the host 100 may additionally include a host memory. The host controller 120 may be a device configured to control the overall operation of the host 100 or to control at least one storage device 300 and 400 on the host 100 side. The host memory may be used as a buffer memory for temporarily storing data to be transmitted to at least one storage device 300 and 400 or data transmitted from at least one storage device 300 and 400.

[0029] The interface circuit 110 can provide an interface for exchanging data between the host 100, at least one storage device 300 and 400, and the log processing device 200. For example, the interface circuit 110 can be implemented in various interface methods, such as Peripheral Component Interconnect (PCI), high-speed PCI (PCIe), and Non-Volatile Memory Express (NVMe). In some implementations, the interface circuit 110 can include multiple physical layers (PHY) 112, 114, and 116. The PHY 112, 114, and 116 can include physical components for exchanging data between the host 100, at least one storage device 300 and 400, and the log processing device 200. Referring to Figure 1 , the host 100 and the log processing device 200 can be connected to each other through the PHY 112 of the interface circuit 110 to exchange data. In addition, at least one storage device 300 and 400 can be connected to the host 100 through the PHY 114 and 116 of the interface circuit 110 respectively to exchange data.

[0030] In addition, the interface circuit 110 can provide an interface for exchanging data between multiple devices connected to the multiple PHY 112, 114, and 116. That is, the interface circuit 110 can provide an interface for supporting peer-to-peer (P2P) communication between multiple devices connected to the multiple PHY 112, 114, and 116. For example, the log processing device 200 connected to the PHY 112 can directly exchange data with the storage device 300 connected to the PHY 114 and the storage device 400 connected to the PHY 116 through the interface circuit 110.

[0031] The P2P connection can enable the log processing device 200 to directly access the data in at least one of the storage devices 300 and 400, thus reserving the limited bandwidth of the connection between the host 100 and at least one of the storage devices 300 and 400 and the connection between the host 100 and the log processing device 200. Depending on the implementation details, compared with sending data through the host 100 and / or the host memory, the P2P connection can increase the bandwidth or reduce the overhead, memory usage, and / or power consumption regarding transferring data between at least one of the storage devices 300 and 400 and the log processing device 200. In some implementations, the P2P connection can be particularly used for shuffle acceleration operations, which can involve migrating data multiple times between at least one of the storage devices 300 and 400 and the log processing device 200.

[0032] The P2P connection can be implemented using any type of communication architecture and / or protocol, such as an interconnect, a network, and / or a storage interface. In some implementations, the P2P connection can be implemented as a separate logical or virtual connection on a shared physical connection that can be used to implement a communication interface, either in whole or in part.

[0033] The communication interface can be implemented using any type of communication architecture and / or protocol. For example, the communication interface can be implemented, in whole or in part, using an interconnect architecture and / or protocol, such as PCIe, Compute Express Link (CXL), Cache Coherent Interconnect for Accelerators (CCIX), etc. As another example, the communication interface can be implemented, in whole or in part, using a network architecture and / or protocol, such as Ethernet, TCP / IP, Fibre Channel (FC), InfiniBand, etc. As an additional example, the communication interface can be implemented, in whole or in part, as a storage interface and / or protocol, such as Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), NVMe, etc. Additionally, any one of these architectures, protocols, and / or interfaces can be combined in a hybrid combination, such as NVMe over Fabrics (NVMe-oF).

[0034] Additionally, although interface circuit 110 is shown as being included in Figure 1 host 100, interface circuit 110 can be a component different from host 100. For example, as described below with reference to Figure 2 interface circuit 110 can be implemented in the form of a bus.

[0035] Although not shown, at least one of storage devices 300 and 400 can include a storage controller and non-volatile memory (NVM). The storage controller in at least one of storage devices 300 and 400 can control the NVM to write data to the NVM in response to a write request from host 100, or can control the NVM to read data stored in the NVM in response to a read request from host 100.

[0036] The log processing device 200 can exchange data with host 100 and at least one of storage devices 300 and 400, and can process log data. The log processing device 200 can be connected to PHY 112 of interface circuit 110 to exchange data with host 100. Additionally, the log processing device 200 connected to PHY 112 of interface circuit 110 can exchange data with at least one of storage devices 300 and 400 connected to PHYs 114 and 116 through P2P communication.

[0037] The log processing device 200 may include an internal processor 210 and an internal memory 220. The log processing device 200 may receive log data from at least one of the storage devices 300 and 400. The log data may be data representing the state or condition in the process of accessing the storage device. The log data may include data for determining the state of software, hardware, and infrastructure and may be in the form of telemetry data. The log data according to an implementation may include the state of hardware, such as its voltage, space, and memory usage. In addition, the log data according to an implementation may include software error information. The log processing device 200 may receive log data from at least one of the storage devices 300 and 400 and may store the log data in the internal memory 220.

[0038] The internal processor 210 may perform a failure analysis on the log data. The log data may be important in the analysis of discovering and removing failure factors that impede the productivity of the storage system. Since the log data generated from each semiconductor device may include a very large amount of data, it is not only difficult to analyze in detail the log data generated from each semiconductor device, but also the analysis of the log data may take a very long time. In addition, it is difficult to comprehensively compare and analyze each log data generated from each semiconductor device, and it is difficult to accurately analyze the correlation between each semiconductor device.

[0039] The internal processor 210 may download, compare, analyze, and transform a large amount of log data generated from at least one of the storage devices 300 and 400 in a database to generate data to improve productivity and product quality. In addition, the internal processor 210 may improve the operation efficiency of the storage system by comparing and analyzing the log data generated from at least one of the storage devices 300 and 400 and analyzing the correlation between at least one of the storage devices 300 and 400. The internal processor 210 may generate failure analysis data by performing a failure analysis on the stored log data. The log processing device 200 may transmit the failure analysis data to the host 100. Hereinafter, a specific operation method of the log processing device 200 will be described with reference to Figures 3 to 7 A detailed description will be given of the specific operation method of the log processing device 200.

[0040] To effectively perform a failure analysis of the storage device, relatively long-term log data of several months or longer may be required, rather than short-term log data. In addition, since an excessive load may be caused when the existing host 100 performs tasks, the task of storing and analyzing a large amount of log data is not performed. According to the above implementation, since the log processing device 200 is separated from the host 100 and at least one of the storage devices 300 and 400, the log processing device 200 may directly collect and store log data through P2P communication with at least one of the storage devices 300 and 400 and may perform a failure analysis by itself, thereby minimizing the load on the host 100.

[0041] Figure 2 It is a block diagram of a host-storage system including a log processing device according to an implementation.

[0042] Referring to Figure 2 , the host-storage system 10 may include a host 100, a log processing device 200, at least one storage device 300 and 400, and a bus 500. Figure 2 The host-storage system 10 of Figure 1 is an example of the host-storage system 10 of Figure 1 . The host-storage system 10 is shown herein as including two storage devices, but this is merely an example. The host-storage system 10 may include a different number of storage devices. Hereinafter, referring to Figure 2 for description

[0043] The host 100 may include an interface circuit 110 and a host controller 120. Additionally, although not shown, the host 100 may additionally include a host memory. The host 100 may control data processing operations of at least one of the storage devices 300 and 400, such as a data read operation or a data write operation.

[0044] The log processing device 200 may include an internal processor 210 and an internal memory 220. The log processing device 200 may exchange data with the host 100 and at least one of the storage devices 300 and 400, and may process log data.

[0045] The storage controller in at least one of the storage devices 300 and 400 may control the NVM to write data into the NVM in response to a write request from the host 100, or may control the NVM to read data stored in the NVM in response to a read request from the host 100.

[0046] The bus 500 may provide an interface for exchanging data among the host 100, at least one of the storage devices 300 and 400, and the log processing device 200. For example, the interface circuit 110 may be implemented in various interface methods, such as PCI, PCIe, and NVMe. The bus 500 according to the implementation may provide an interface for exchanging data among the host 100, at least one of the storage devices 300 and 400, and the log processing device 200. For example, the host 100 and the log processing device 200 may be connected to each other through the bus 500 to exchange data. Additionally, at least one of the storage devices 300 and 400 may be connected to the host 100 through the bus 500 to exchange data.

[0047] The bus 500 may provide an interface for exchanging data among multiple connected devices. That is, the bus 500 may provide an interface for supporting P2P communication among multiple connected devices. For example, the log processing device 200 may directly exchange data with the storage device 300 through the bus 500. In addition, the log processing device 200 may directly exchange data with the storage device 400 through the bus 500.

[0048] The bus 500 may correspond to Figure 1 the interface circuit 110. That is, in Figure 2 it, the bus 500 is shown as a component different from the host 100, but the bus 500 may be included in the host 100. For example, as described above with reference to Figure 1 it, the bus 500 may be implemented in the form of the interface circuit 110 and may be included in the host 100.

[0049] Figure 3 is a flowchart of an operation method of the log processing device 200 according to an implementation.

[0050] Referring to Figure 3 , the operation method of the log processing device 200 may include multiple operations S110 to S140. In Figure 3 it, one of the at least one storage device 300 and 400, the storage device 300, and the log processing device 200 are shown to exchange data, but it is not limited thereto. Hereinafter, referring to Figure 1 it describes Figure 3 , and descriptions repeated with the above are omitted.

[0051] In operation S110, the log processing device 200 may receive log data from the storage device 300. The log data may be data representing the state or condition in the process of accessing the storage device, and may include the state of hardware, software error information, etc. In operation S120, the log processing device 200 may store the received log data. For example, the log processing device 200 may store the log data in the internal memory 220.

[0052] In operation S130, the log processing device 200 may perform a failure analysis on the log data. The failure analysis may include an analysis of finding and removing failure factors that impede the productivity of the storage device. The log processing device 200 according to an implementation may perform a failure analysis on the log data through the internal processor 210. The log processing device 200 may generate failure analysis data by performing a failure analysis on the log data. In operation S140, the log processing device 200 may transmit the generated failure analysis data to the host 100.

[0053] Since the log processing device 200 is separated from the host 100 and at least one storage device 300 and 400, the log processing device 200 can directly collect and store log data through P2P communication with at least one storage device 300 and 400, and can perform fault analysis by itself, thereby minimizing the load on the host 100.

[0054] Figure 4 is a flowchart of an operation method of a log processing device according to an implementation.

[0055] Referring to Figure 4 , the operation method of the log processing device 200 may include a plurality of operations S210 to S260. In Figure 4 , one of the at least one storage device 300 and 400, the storage device 300, and the log processing device 200 are shown to exchange data, but it is not limited thereto. Hereinafter, referring to Figure 1 and Figure 3 description Figure 4 , descriptions that are repetitive with the above description are omitted.

[0056] In operation S210, the log processing device 200 can receive log data from the storage device 300. In operation S220, the log processing device 200 can store the received log data. In operation S230, the log processing device 200 can perform fault analysis on the log data. Operations S210 to S230 may correspond to Figure 3 operations S110 to S130.

[0057] In operation S240, the log processing device 200 can store the generated fault analysis data. For example, the log processing device 200 can store the generated fault analysis data in the internal memory 220.

[0058] In addition, in operation S250, the log processing device 200 can receive a data command from the host 100. For example, the data command can be a call request signal for log data or a call request signal for fault analysis data. The data command can be a call request signal for all other types of data within the log processing device 200.

[0059] In operation S260, the log processing device 200 can transmit output data corresponding to the data command to the host 100. For example, when the data command is a call request signal for log data, the output data can be log data. In addition, in the case where the data command is a call request signal for fault analysis data, the output data can be fault analysis data.

[0060] Operations S250 and S260 can be executed before operations S230 and S240. For example, when the data command is a call request signal for log data, operations S250 and S260 can be executed before performing a fault analysis on the received log data in operation S230. That is, before performing a fault analysis on the log data, the log processing device 200 can receive a log data call request signal from the host 100 and transmit the log data to the host 100.

[0061] Figure 5A and Figure 5B is a detailed flowchart of the operation method of the log processing device according to the implementation.

[0062] Refer to Figure 5A and Figure 5B , the operation method of the log processing device 200 can include multiple operations S210 to S260. In Figure 5A and Figure 5B , at least one of the storage devices 300 and 400 and the log processing device 200 are shown to exchange data, but it is not limited thereto. Operations S210 to S240 can correspond to Figure 3 Operations S110 to S140. Hereinafter, refer to the above implementation and describe Figure 5A and Figure 5B , and descriptions that are repetitive with the above description are omitted.

[0063] In operation S210, the log processing device 200 can receive log data from the storage device 300. In operation S220, the internal memory 220 of the log processing device 200 can store the received log data. In operation S225, the internal processor 210 can pre-receive the log data from the internal memory 220 for fault analysis.

[0064] In operation S230, the internal processor 210 can perform a fault analysis on the log data. The internal processor 210 can generate fault analysis data by performing a fault analysis on the log data. In operation S235, the internal processor 210 can transmit the generated fault analysis data to the internal memory 220. In operation S240, the internal memory 220 can store the received fault analysis data.

[0065] In operation S250, the log processing device 200 may receive a data command from the host 100. For example, the data command may be a call request signal for log data or a call request signal for fault analysis data. The internal processor 210 may request data corresponding to the data command from the internal memory 220. The internal processor 210 may receive output data corresponding to the data command from the internal memory 220. For example, when the data command is a call request signal for log data, the output data may be log data. In addition, when the data command is a call request signal for fault analysis data, the output data may be fault analysis data. In operation S260, the log processing device 200 may transmit the output data corresponding to the data command to the host 100.

[0066] Referring to Figure 5A , in operation S250_1, the log processing device 200 may receive a fault analysis data command from the host 100. In operation S260_1, the log processing device 200 may transmit the fault analysis data to the host 100. Operations S250_1 and S260_1 may be examples of operations S250 and S260.

[0067] Referring to Figure 5B , in operation S250_2, the log processing device 200 may receive a log data command from the host 100. In operation S260_2, the log processing device 200 may transmit the log data to the host 100. Operations S250_2 and S260_2 may be examples of operations S250 and S260.

[0068] Since the log processing device 200 is separated from the host 100 and at least one storage device 300 and 400, the log processing device 200 may directly collect and store log data through P2P communication with at least one storage device 300 and 400, and may perform fault analysis by itself, thereby minimizing the load on the host 100.

[0069] Figure 6 is a flowchart of an operation method of a log processing device according to an implementation.

[0070] Referring to Figure 6 , the operation method of the log processing device 200 may include a plurality of operations S310 to S320. Hereinafter, it will be described with reference to the above implementation Figure 6 , and descriptions that are repeated with the above description will be omitted.

[0071] In operation S310, the log processing device 200 may receive a fault analysis data command from the host 100. The fault analysis data command is a call request signal for fault analysis data. Operation S310 may be an example of operation S250. In operation S320, the log processing device 200 may send the fault analysis data to the host 100. Operation S320 may be an example of operation S260.

[0072] Operations S310 and S320 may be executed independently of the above-described operations S210 to S260. For example, operations S310 and S320 may be executed before performing fault analysis on the received log data in operation S230. For example, before performing fault analysis on the log data, the log processing device 200 may receive a fault analysis data call request signal from the host 100 and may transmit the previously executed and stored analysis data to the host 100.

[0073] According to the above implementation, since the log processing device 200 is separated from the host 100 and at least one of the storage devices 300 and 400, the log processing device 200 may directly collect and store log data through P2P communication with at least one of the storage devices 300 and 400 and may perform fault analysis on its own, thereby minimizing the load on the host 100.

[0074] Figure 7 is a flowchart of an operation method of a log processing device according to an implementation.

[0075] Refer to Figure 7 , the operation method of the log processing device 200 may include a plurality of operations S410 to S420. Hereinafter, it will be described with reference to the above implementation Figure 7 , and descriptions that are repeated with the above description will be omitted.

[0076] In operation S410, the log processing device 200 may receive a log data command from the host 100. The log data command is a call request signal for log data. Operation S410 may be an example of operation S250. In operation S420, the log processing device 200 may send the log data to the host 100. Operation S420 may be an example of operation S260.

[0077] Operations S410 and S420 may be executed independently of the above-described operations S210 to S260. For example, operations S410 and S420 may be executed before performing fault analysis on the received log data in operation S230. For example, before performing fault analysis on the log data, the log processing device 200 may receive a log data call request signal from the host 100 and may transmit the log data to the host 100.

[0078] According to the above implementation, since the log processing device 200 is separated from the host 100 and at least one storage device 300 and 400, the log processing device 200 can directly collect and store log data through P2P communication with at least one storage device 300 and 400, and can perform fault analysis by itself, thereby minimizing the load on the host 100.

[0079] Figure 8 is a flowchart of an operation method of a log processing device according to an implementation.

[0080] Referring to Figure 8 , the operation method of the log processing device 200 may include a plurality of operations S110 to S140. Hereinafter, referring to Figure 1 and Figure 3 describe Figure 8 , and descriptions that are repeated with the above descriptions are omitted.

[0081] In operation S110, the log processing device 200 may receive log data from the storage device 300. The log data may be data representing the state or condition in the process of accessing the storage device, and may include the state of hardware, software error information, etc. In operation S120, the log processing device 200 may store the received log data. For example, the log processing device 200 may store the log data in the internal memory 220.

[0082] In operation S130, the log processing device 200 may perform fault analysis on the log data. The fault analysis may include an analysis of finding and removing fault factors that impede the productivity of the storage device. The log processing device 200 according to the implementation may perform fault analysis on the log data through the internal processor 210. The log processing device 200 may generate fault analysis data by performing fault analysis on the log data. In operation S140, the log processing device 200 may transmit the generated fault analysis data to the host 100.

[0083] Figure 9 is a flowchart of an operation method of a log processing device according to an implementation.

[0084] Referring to Figure 9 , the operation method of the log processing device 200 may include a plurality of operations S210 to S260. Hereinafter, described with reference to the above implementation Figure 9 , and descriptions that are repeated with the above descriptions are omitted.

[0085] In operation S210, the log processing device 200 may receive log data from the storage device 300. In operation S220, the log processing device 200 may store the received log data. In operation S230, the log processing device 200 may perform a failure analysis on the log data. Operations S210 to S230 may correspond to Figure 8 operations S110 to S130.

[0086] In operation S240, the log processing device 200 may store the generated failure analysis data. For example, the log processing device 200 may store the generated failure analysis data in the internal memory 220.

[0087] In operation S250, the log processing device 200 may receive a data command from the host 100. For example, the data command may be a call request signal for the log data or a call request signal for the failure analysis data.

[0088] In operation S260, the log processing device 200 may send the output data corresponding to the data command to the host 100. For example, when the data command is a call request signal for the log data, the output data may be the log data. In addition, when the data command is a call request signal for the failure analysis data, the output data may be the failure analysis data.

[0089] Operations S250 and S260 may be performed before operations S230 and S240. For example, when the data command is a call request signal for the log data, operations S250 and S260 may be performed before performing a failure analysis on the received log data in operation S230. That is, before performing a failure analysis on the log data, the log processing device 200 may receive a log data call request signal from the host 100 and send the log data to the host 100.

[0090] Figure 10 is a block diagram of a system that applies a storage device according to an implementation.

[0091] Figure 10 The system 1000 may be a mobile system, such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a health care device, or an Internet of Things (IoT). However, Figure 10 the system 1000 is not necessarily limited to a mobile system. The system 1000 may include a personal computer, a laptop computer, a server, a media player, or an automotive device, such as a navigation system.

[0092] Referring to Figure 10, the system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b. The system 1000 may additionally include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0093] The main processor 1100 may control the overall operation of the system 1000, and more specifically, control the operations of the other components that form the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an AP.

[0094] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling the memories 1200a and 1200b and / or the storage devices 1300a and 1300b. According to the implementation, the main processor 1100 may also include an accelerator 1130 as a dedicated circuit for high-speed data computing (such as artificial intelligence (AI) data computing). The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of the other components of the main processor 1100.

[0095] The memories 1200a and 1200b may be used as the main memory devices of the system 1000. The memories 1200a and 1200b may include volatile memories such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), and may also include NVM such as flash memory, phase change memory (PRAM), and / or resistive random access memory (RRAM). The memories 1200a and 1200b may also be implemented in the same package as the main processor 1100.

[0096] The storage devices 1300a and 1300b may be used as non-volatile storage devices for storing data regardless of whether they are powered, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and NVMs 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. The NVMs 1320a and 1320b may include V-NAND flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) structure, but may also include other types of NVM such as PRAM and / or RRAM.

[0097] In system 1000, storage devices 1300a and 1300b may be physically separated from main processor 1100, or may be implemented in the same package as main processor 1100. Additionally, since storage devices 1300a and 1300b have the same form as solid-state devices (SSDs) or memory cards, storage devices 1300a and 1300b may be removably coupled to other components of system 1000 through an interface such as connection interface 1480 described below. Storage devices 1300a and 1300b may be devices that apply standard protocols such as Universal Flash Storage (UFS), embedded multimedia card (eMMC), or NVMe, but are not limited thereto.

[0098] Image capture device 1410 may capture still images or moving images, and may include a camera, a video camera, and / or a webcam.

[0099] User input device 1420 may receive various types of data inputs from a user of system 1000, and may include a touchpad, a keypad, a mouse, and / or a microphone.

[0100] Sensor 1430 may detect various types of physical quantities obtained from outside system 1000, and may convert the sensed physical quantities into electrical signals. Sensor 1430 may include a temperature sensor, a pressure sensor, a lighting sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope.

[0101] Communication device 1440 may exchange signals with other devices outside system 1000 according to various communication protocols. Communication device 1440 may be implemented to include an antenna, a transceiver, and / or a modem.

[0102] Display 1450 and speaker 1460 may be used as output devices that output visual information and auditory information to a user of system 1000, respectively.

[0103] Power supply device 1470 may appropriately convert power supplied from a battery (not shown) built in system 1000 and / or an external power source, and may supply power to each component of system 1000.

[0104] Connection interface 1480 may provide a connection between system 1000 and an external device connected to system 1000 to exchange data with system 1000. Connection interface 1480 may be implemented in various interface methods, such as ATA, SATA, external SATA (e-SATA), SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), eMMC, UFS, embedded UFS (eUFS), and Compact Flash (CF) card interface.

[0105] System 1000 may additionally include the above-mentioned log processing device 200. The log processing device 200 included in system 1000 may collect the log data of storage devices 1300a and 1300b and perform a fault analysis on the log data. The log processing device 200 may transmit the fault analysis data to the main processor 1100. According to the above implementation, since the log processing device 200 is separated from the host 100 and at least one of the storage devices 300 and 400, the log processing device 200 may directly collect and store the log data through P2P communication with at least one of the storage devices 300 and 400, and may perform the fault analysis by itself, thereby minimizing the load on the host 100.

[0106] Figure 11 It is a block diagram of a data center of a storage device according to an implementation.

[0107] Referring to Figure 11 , a data center 3000, as a facility for collecting various types of data and providing services, may also be referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, or may be a computing system used in a company such as a bank or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected in various ways according to the implementation. In addition, the number of application servers 3100 to 3100n may be different from the number of storage servers 3200 to 3200m.

[0108] The application server 3100 or the storage server 3200 may include at least one of processors 3110 and 3210 and memories 3120 and 3220. For the storage server 3200, the processor 3210 may control the overall operation of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 may be a double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVDIMM). Depending on the implementation, the number of the processor 3210 and the memory 3220 included in the storage server 3200 may be selected in various ways. In an implementation, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an implementation, the number of the processor 3210 may be different from the number of the memory 3220. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. Depending on the implementation, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one or more storage devices 3250. The number of the storage devices 3250 included in the storage server 3200 may be selected in various ways according to the implementation.

[0109] The application servers 3100 to 3100n may communicate with the storage servers 3200 to 3200m via the network 3300. The network 3300 may be implemented using FC or Ethernet. FC, as a medium for relatively high-speed data transmission, may use an optical switch that provides high performance / high availability. According to the access method of the network 3300, the storage servers 3200 to 3200m may provide file storage, block storage, or object storage.

[0110] In an implementation, the network 3300 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In another implementation, the network 3300 may be a general network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as Fibre Channel over Ethernet (FCoE), network-attached storage (NAS), and NVMe-oF.

[0111] In the following, the description focuses on the application server 3100 and the storage server 3200. The description of the application server 3100 can also be applied to another application server 3100n, and the description of the storage server 3200 can also be applied to another storage server 3200m.

[0112] The application server 3100 can store, via the network 3300, data requested by a user or a client and to be stored in one of the storage servers 3200 to 3200m. In addition, the application server 3100 can obtain, via the network 3300, data requested by a user or a client to be read from one of the storage servers 3200 to 3200m. For example, the application server 3100 can be implemented as a web server or a database management system (DBMS).

[0113] The application server 3100 can access, via the network 3300, the memory 3120n or the storage device 3150n included in another application server 3100n, or can access, via the network 3300, the memory 3220 to 3220m or the storage device 3250 to 3250m included in the storage servers 3200 to 3200m. Thus, the application server 3100 can perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 can execute commands to move or copy data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. The data can be directly moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the memory 3120 to 3120n, or can be moved to the memory 3120 to 3120n through the memory 3220 to 3220m of the storage servers 3200 to 3200m. For security or privacy, the data moved through the network 3300 can be encrypted data.

[0114] For the storage server 3200, the interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface controller (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented in a direct attached storage (DAS) method that directly connects the storage device 3250 to a dedicated cable. In addition, for example, the interface 3254 can be implemented in various interface methods, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB, SD card, MMC, eMMC, UFS, eUFS, and CF card interfaces.

[0115] The storage server 3200 may further include a switch 3230 and a NIC 3240. Under the control of the processor 3210, the switch 3230 may selectively connect the processor 3210 to the storage device 3250, or may selectively connect the NIC 3240 to the storage device 3250.

[0116] In an implementation, the NIC 3240 may include a network interface card, a network adapter, etc. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 3240 may include an internal memory, a DSP, and a host bus interface, and may be connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as an example of the above interface 3254. In an implementation, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0117] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor 3210 may send commands to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m to program or read data. The data may be data corrected by an error correction code (ECC) engine. The data may be data that has undergone data bus inversion (DBI) or data masking (DM), and may include cyclic redundancy code (CRC) information. The data may be encrypted data for security or privacy.

[0118] The storage devices 3150 to 3150n and 3250 to 3250m may transmit control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to read commands received from the processor 3210. Therefore, when reading data from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal, and the data may be output to the DQ bus. A data strobe signal (DQS) may be generated using the RE signal. The command and address signals may be latched in the page buffer according to the rising edge or falling edge of a write enable (WE) signal.

[0119] The controller 3251 can generally control the operation of the storage device 3250. In an implementation, the controller 3251 can include SRAM. The controller 3251 can write data to the NAND flash memory device 3252 in response to a write command, or can read data from the NAND flash memory device 3252 in response to a read command. For example, the write command and / or the read command can be provided from the processor 3210 in the storage server 3200, the processor 3210m in another storage server 3200m, or the processors 3110 and 3110n in the application servers 3100 and 3100n. The DRAM 3253 can temporarily buffer the data to be written to the NAND flash memory device 3252 or the data read from the NAND flash memory device 3252. In addition, the DRAM 3253 can store metadata. The metadata is data generated by the controller 3251 to manage user data or the NAND flash memory device 3252. The storage device 3250 can include a security element (SE) for security or privacy.

[0120] The storage servers 3200 to 3200m or the application servers 3100 to 3100n can additionally include the above-mentioned log processing device 200 therein. The log processing device 200 can collect log data from the storage devices 3150 to 3150n and 3250 to 3250m and perform fault analysis. The log processing device 200 can transmit the fault analysis data to the processor 3210 in the storage server 3200, the processor 3210m in another storage server 3200m, or the processors 3110 and 3110n in the application servers 3100 and 3100n. According to the above implementation, since the log processing device 200 is separated from the host 100 and at least one storage device 300 and 400, the log processing device 200 can directly collect and store log data through P2P communication with at least one storage device 300 and 400, and can perform fault analysis by itself, thereby minimizing the load on the host 100.

[0121] Figure 12 is a cross-sectional view of a BVNAND structure applicable to a storage device according to an implementation.

[0122] Refer to Figure 12, the memory device 4000 may have a chip-to-chip (C2C) structure. The C2C structure may be obtained by fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and connecting the upper chip to the lower chip using a bonding method. For example, the bonding method may refer to a method of electrically connecting bonding metals formed on the top metal layer of the upper chip to bonding metals formed on the top metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method. In addition, the bonding metal may also be formed of aluminum or tungsten.

[0123] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 4000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0124] The peripheral circuit region PERI may include: a first substrate 4110, an interlayer insulating layer 4115, a plurality of circuit elements 4120a, 4120b, and 4120c formed on the first substrate 4110, first metal layers 4130a, 4130b, and 4130c respectively connected to the plurality of circuit elements 4120a, 4120b, and 4120c, and second metal layers 4140a, 4140b, and 4140c formed on the first metal layers 4130a, 4130b, and 4130c. In an implementation, the first metal layers 4130a, 4130b, and 4130c may be formed of tungsten having a relatively high resistance, and the second metal layers 4140a, 4140b, and 4140c may be formed of copper having a relatively low resistance.

[0125] Only the first metal layers 4130a, 4130b, and 4130c and the second metal layers 4140a, 4140b, and 4140c are shown and described herein, but the metal layers are not limited thereto. At least one or more metal layers may be further formed on the second metal layers 4140a, 4140b, and 4140c. At least some of one or more metal layers formed on the top of the second metal layers 4140a, 4140b, and 4140c may be formed of aluminum having a bulk resistivity higher than that of the copper forming the second metal layers 4140a, 4140b, and 4140c.

[0126] The interlayer insulating layer 4115 may be formed on the first substrate 4110 to cover the plurality of circuit elements 4120a, 4120b, and 4120c, the first metal layers 4130a, 4130b, and 4130c, and the second metal layers 4140a, 4140b, and 4140c, and may include insulating materials such as silicon oxide, silicon nitride, etc.

[0127] Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area CELL through a bonding method. The lower bonding metals 4171b and 4172b and the upper bonding metals 4271b and 4272b may be formed of aluminum, copper, or tungsten.

[0128] The cell area CELL may provide at least one memory block. The cell area CELL may include a second substrate 4210 and a common source line 4220. On the second substrate 4210, a plurality of word lines 4230 (4231 to 4238) may be stacked in a direction (Z-axis direction) perpendicular to the top surface of the second substrate 4210. The string select line and the ground select line may be located above and below the word lines 4230, respectively. The plurality of word lines 4230 may be located between the string select line and the ground select line.

[0129] In the bit line bonding area BLBA, the channel structure CHS may extend in a direction perpendicular to the top surface of the second substrate 4210 and may extend through the word lines 4230, the string select line, and the ground select line. The channel structure CHS may include a data storage layer, a channel layer, and a buried insulating layer, wherein the channel layer may be electrically connected to the first metal layer 4250c and the second metal layer 4260c. For example, the first metal layer 4250c may be a bit line contact, and the second metal layer 4260c may be a bit line. In an implementation, the bit line 4260c may extend in a first direction (Y-axis direction) parallel to the top surface of the second substrate 4210.

[0130] In Figure 12 the illustrated implementation, the area where the channel structure CHS and the bit line 4260c are located may be defined as the bit line bonding area BLBA. The bit line 4260c may be electrically connected to a circuit element 4120c that provides a page buffer 4293 in the bit line bonding area BLBA in the peripheral circuit area PERI. For example, the bit line 4260c may be connected to the upper bonding metals 4271c and 4272c in the peripheral circuit area PERI, wherein the upper bonding metals 4271c and 4272c may be connected to the lower bonding metals 4171c and 4172c, and the lower bonding metals 4171c and 4172c are connected to the circuit element 4120c of the page buffer 4293.

[0131] In a word line bonding area WLBA, a word line 4230 may extend in a second direction (X-axis direction) parallel to a top surface of a second substrate 4210 and may be connected to a plurality of unit contact plugs 4240 (4241 to 4247). The word line 4230 may be connected to the unit contact plugs 4240 at pads provided by at least some of the word lines 4230 extending to different lengths in the second direction. A first metal layer 4250b and a second metal layer 4260b may be sequentially connected to tops of the unit contact plugs 4240 connected to the word line 4230. The unit contact plugs 4240 may be connected to a peripheral circuit area PERI through upper bonding metals 4271b and 4272b of a cell area CELL and lower bonding metals 4171b and 4172b of the peripheral circuit area PERI in the word line bonding area WLBA.

[0132] The unit contact plugs 4240 may be electrically connected to a circuit element 4120b that provides a row decoder 4294 in the peripheral circuit area PERI. In an implementation, an operating voltage of the circuit element 4120b that provides the row decoder 4294 may be different from an operating voltage of a circuit element 4120c that provides a page buffer 4293. For example, the operating voltage of the circuit element 4120c that provides the page buffer 4293 may be greater than the operating voltage of the circuit element 4120b that provides the row decoder 4294.

[0133] A common source line contact plug 4280 may be located in an external pad bonding area PA. The common source line contact plug 4280 may be made of a conductive material such as metal, metal compound, or polysilicon and may be electrically connected to a common source line 4220. A first metal layer 4250a and a second metal layer 4260a may be sequentially stacked on the common source line contact plug 4280. For example, an area where the common source line contact plug 4280, the first metal layer 4250a, and the second metal layer 4260a are located may be defined as the external pad bonding area PA.

[0134] Meanwhile, input / output pads 4105 and 4205 may be located in the external pad bonding area PA. Refer to Figure 12 , a lower insulating film 4101 may be formed under a first substrate 4110 to cover a bottom surface of the first substrate 4110. A first input / output pad 4105 may be formed on the lower insulating film 4101. The first input / output pad 4105 may be connected to at least one of a plurality of circuit elements 4120a, 4120b, and 4120c in the peripheral circuit area PERI through a first input / output contact plug 4103 and may be separated from the first substrate 4110 through the lower insulating film 4101. In addition, a side insulating film may be located between the first input / output contact plug 4103 and the first substrate 4110 to electrically isolate the first input / output contact plug 4103 from the first substrate 4110.

[0135] Reference Figure 12 As shown in Figure 12 , an upper insulating film 4201 may be formed on a second substrate 4210 to cover a top surface of the second substrate 4210. A second input / output pad 4205 may be disposed on the upper insulating film 4201. The second input / output pad 4205 may be connected to at least one of a plurality of circuit elements 4120a, 4120b, and 4120c located in a peripheral circuit region PERI through a second input / output contact plug 4203.

[0136] According to an implementation, the second substrate 4210 and a common source line 4220 may not be located in a region where the second input / output contact plug 4203 is located. In addition, the second input / output pad 4205 may not overlap with a word line 4230 in a third direction (Z-axis direction). Refer to Figure 12 . Figure 12 As shown in Figure 12 , the second input / output contact plug 4203 may be separated from the second substrate 4210 in a direction parallel to a top surface of the second substrate 4210, and may be connected to the second input / output pad 4205 through an interlayer insulating layer 4215 in a cell region CELL.

[0137] According to an implementation, a first input / output pad 4105 and a second input / output pad 4205 may be selectively formed. For example, the memory device 4000 may include only the first input / output pad 4105 disposed on top of a first substrate 4110, or may include only the second input / output pad 4205 disposed on top of the second substrate 4210. Alternatively, the memory device 4000 may include the first input / output pad 4105 and the second input / output pad 4205.

[0138] In an external pad bonding region PA and a bit line bonding region BLBA included in each of the cell region CELL and the peripheral circuit region PERI, a metal pattern of a top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0139] In the external pad bonding region PA, in response to an upper metal pattern 4272a formed on a top metal layer of the cell region CELL, the memory device 4000 may form a lower metal pattern 4173a having the same shape as the upper metal pattern 4272a of the cell region CELL on a top metal layer of the peripheral circuit region PERI. The lower metal pattern 4173a formed on the top metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in response to a lower metal pattern formed on the top metal layer of the peripheral circuit region PERI in the external pad bonding region PA, the memory device 4000 may form an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI on the top metal layer.

[0140] Lower bonding metals 4171b and 4172b may be formed on a second metal layer 4140b of a word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of a peripheral circuit area PERI may be electrically connected to upper bonding metals 4271b and 4272b of a cell area CELL by a bonding method.

[0141] In addition, in a bit line bonding area BLBA, in response to a lower metal pattern 4152 formed on a top metal layer of a peripheral circuit area PERI, an upper metal pattern 4292 having the same shape as the lower metal pattern 4152 of the peripheral circuit area PERI may be formed on a top metal layer of the cell area CELL. A contact may not be formed on the upper metal pattern 4292 that may not be formed on the top metal layer of the cell area CELL.

[0142] Figure 12 A memory device 4000 may correspond to the NVM inside at least one of the above-described storage devices 300 and 400. In addition, the memory device 4000 may correspond to at least some of the various types of memories or memory devices described above.

[0143] Although this disclosure contains many specific implementation details, these should not be construed as limitations on the scope that may be claimed. Certain features described in the context of separate implementations in this disclosure may also be implemented combinatorially in a single implementation. Conversely, the various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. In addition, although the features may be described above as acting in certain combinations, one or more features from a combination may in some cases be removed from the combination, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0144] Although the present disclosure has been specifically shown and described with reference to its implementations, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a log processing device, the log processing device including an internal memory for storing log data and an internal processor for processing the log data, the method comprising: Receiving the log data from at least one storage device; Storing the received log data; Generating fault analysis data by performing fault analysis on the log data; And Transmitting the fault analysis data to a host device.

2. The method of operation according to claim 1, further comprising: Receiving a data command from the host device; And Transmitting output data corresponding to the data command to the host device.

3. The operating method according to claim 2, wherein, The data command includes a call request signal for the log data, and the output data includes the log data.

4. The operating method according to claim 2, wherein, The data command includes a call request signal for the fault analysis data, and the output data includes the fault analysis data.

5. The method of operation according to claim 1, further comprising storing the fault analysis data in the internal memory.

6. The operating method according to claim 1, wherein, The log processing device performs peer-to-peer communication with the at least one storage device.

7. The operating method according to claim 6, wherein, The peer-to-peer communication is based on the Peripheral Component Interconnect Express communication method.

8. The operating method according to claim 1, wherein, The log processing device is connected to the host device through a physical terminal.

9. A log processing device for processing log data, the log processing device comprising: An internal memory configured to store the log data received from at least one storage device; And An internal processor configured to perform fault analysis on the log data and generate fault analysis data, Wherein the log processing device transmits the fault analysis data to a host device.

10. The log processing device according to claim 9, wherein, The log processing device receives a data command from the host device and transmits output data corresponding to the data command to the host device.

11. The log processing device according to claim 10, wherein, The data command includes a call request signal for the log data, and the output data includes the log data.

12. The log processing apparatus according to claim 10, wherein, The data command includes a call request signal for the fault analysis data, and the output data includes the fault analysis data.

13. The log processing device according to claim 9, wherein, The internal memory is configured to store the fault analysis data.

14. The log processing device according to claim 9, wherein, The log processing device performs peer-to-peer communication with the at least one storage device.

15. The log processing device according to claim 14, wherein, The peer-to-peer communication is based on the Peripheral Component Interconnect Express communication method.

16. The log processing device according to claim 9, wherein, The log processing device is connected to the host device through a physical terminal.

17. A system, comprising: At least one storage device for storing data; A host device; And A log processing device for processing log data, Wherein the log processing device includes an internal memory and an internal processor, the internal memory is configured to store the log data received from the at least one storage device, the internal processor is configured to perform fault analysis on the log data and generate fault analysis data, and The log processing device transmits the fault analysis data to the host device.

18. The system according to claim 17, wherein, The log processing device receives a data command from the host device and transmits output data corresponding to the data command to the host device.

19. The system according to claim 17, wherein, The log processing device performs peer-to-peer communication with the at least one storage device.

20. The system according to claim 17, wherein, The log processing device is connected to the host device through a physical terminal.

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