Cache consistency method, device and equipment for multi-core multi-thread heterogeneous system

Abstract

The embodiment of the invention discloses a cache consistency method, device and equipment for a multi-core multi-thread heterogeneous system, and the method comprises the steps: prying a copy cache through a first prying channel, and enabling the copy cache to be arranged in a local cache to which a first core in the heterogeneous system belongs, a first snooping channel is arranged between the first kernel and a shared cache of the heterogeneous system, and the shared cache comprises a first sub-cache; when it is detected that the copy cache writes first data corresponding to the first function type, a first write request is sent to a first kernel, so that the first kernel writes the first data into a first sub-cache; first synchronization information is sent to a second kernel in the heterogeneous system, so that the second kernel reads the first data from the first sub-cache and synchronizes the first data to the local cache; full cache consistency between the first kernel and the second kernel can be achieved, data are separately stored according to different function types for cache consistency management, and the data synchronization rate is increased.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a cache coherence method, apparatus, and device for a multi-core and multi-thread heterogeneous system. Background Art

[0002] In a heterogeneous system applied to autonomous driving, the number of Central Processing Unit / Processor (CPU) cores is more than 2, up to 128 or more, and the number of Neural Network Processing Unit (NPU) cores is up to dozens, with 16 - 64 threads or more in each NPU core. Usually, three levels of caches are set in the CPU cluster, namely, level 1 cache, level 2 cache, and level 3 cache. The cache line size of the three-level cache is 64 bytes of data. The three-level cache helps to make full use of temporal locality and spatial locality and is suitable for data migration and synchronization between multiple cores. Usually, two levels of caches are set in the NPU cluster, namely, level 1 cache and level 2 cache. The cache line size of the two-level cache is 128 bytes of data, which is suitable for high-parallelism and bandwidth-sensitive parallel programs. The Shared Last Level Cache is a cache shared by CPU cores, NPU cores, Graphics Processing Unit (GPU) cores in the heterogeneous system, and other devices. There are a Shared Host Cache and a Shared System Cache in the Shared Last Level Cache. The cache line size of both caches is 64 bytes of data. Among them, the Shared Host Cache is shared among CPU cores, GPU cores, and other devices, and the Shared System Cache is shared among CPU cores, NPU cores, GPU cores, and other devices. A System on Chip (SoC) Double Data Rate (DDR) is also shared among CPU cores, NPU cores, GPU cores, and other devices. The SoC DDR correspondingly stores Host Memory, System Memory, and Computing Memory.

[0003] Among them, a full coherent mechanism is adopted between the level-1 cache, level-2 cache, and level-3 cache of the CPU core and the shared last-level cache. The NPU core, GPU core, and other devices can read the latest data cached by the CPU core through the shared last-level cache. However, an input / output coherent (I / O Coherent) mechanism is adopted between the level-2 cache of the NPU core and the shared last-level cache. The CPU core cannot timely read the latest data cached by the NPU core through the shared last-level cache. The NPU core is the core for processing data parallelism, and a lot of data exchange and synchronization are required between the NPU core and the CPU core.

[0004] Currently, for the CPU core to read the data of the NPU core, it needs to perform a Cache Maintenance Operation (CMO) each time, resulting in poor performance of data exchange and synchronization between the CPU core and the NPU core. Summary of the Invention

[0005] Embodiments of this application disclose a cache coherence method, device, and equipment for a multi-core and multi-thread heterogeneous system, which can improve the performance of data synchronization and cache coherence between a first core and a second core in the heterogeneous system.

[0006] In a first aspect, embodiments of this application disclose a cache coherence method for a multi-core and multi-thread heterogeneous system, which is applied to a synchronization control device. The method includes:

[0007] Snooping on a copy cache through a first snooping channel. The copy cache is set in the local cache of the first core in the heterogeneous system. The first snooping channel is set between the first core and the shared cache of the heterogeneous system. The shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache data corresponding to a first functional type shared.

[0008] When it is snooped that the copy cache writes the first data corresponding to the first functional type, send a first write request to the first core so that the first core writes the first data into the first sub-cache.

[0009] Send first synchronization information to a second core in the heterogeneous system so that the second core reads the first data from the first sub-cache and synchronizes it to the local cache.

[0010] In a second aspect, embodiments of this application disclose a cache coherence method for a multi-core and multi-thread heterogeneous system,

[0011] which is applied to the first core in the heterogeneous system. The method includes:

[0012] Receive a first write request sent by a synchronization control device, where the first write request is sent by the synchronization control device when it snoops through a first snooping channel that a copy cache writes first data corresponding to a first function type. The copy cache is set in a local cache to which the first core belongs. A first snooping channel is set between the first core and a shared cache of the heterogeneous system. The shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache data corresponding to the shared first function type;

[0013] In response to the first write request, write the first data into the first sub-cache.

[0014] In a third aspect, an embodiment of the present application discloses a cache coherence method for a multi-core and multi-thread heterogeneous system,

[0015] applied to a second core in a heterogeneous system. The method includes:

[0016] Receive first synchronization information sent by a synchronization control device. The first synchronization information is sent by the synchronization control device to a first core in the heterogeneous system to send a first write request to enable the first core to write the first data into a first sub-cache when it snoops through a first snooping channel that a copy cache writes first data corresponding to a first function type. The copy cache is set in a local cache to which the first core belongs. A first snooping channel is set between the first core and a shared cache of the heterogeneous system. The shared cache includes the first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache data corresponding to the shared first function type;

[0017] In response to the first synchronization information, read the first data from the first sub-cache and synchronize it to the local cache.

[0018] In a fourth aspect, an embodiment of the present application discloses a cache coherence device for a multi-core and multi-thread heterogeneous system, which may include:

[0019] A snooping module for snooping on a copy cache through a first snooping channel. The copy cache is set in a local cache to which a first core in a heterogeneous system belongs. A first snooping channel is set between the first core and a shared cache of the heterogeneous system. The shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache data corresponding to the shared first function type;

[0020] A first communication module for sending a first write request to the first core when it snoops that the copy cache writes first data corresponding to the first function type, so that the first core writes the first data into the first sub-cache;

[0021] The first communication module is configured to send first synchronization information to a second core in the heterogeneous system, so that the second core reads the first data from the first sub-cache and synchronizes it to the local cache.

[0022] In a fifth aspect, an embodiment of the present application discloses a cache coherence device for a multi-core and multi-thread heterogeneous system, which may include:

[0023] A second communication module, configured to receive a first write request sent by a synchronization control device, where the first write request is sent by the synchronization control device when it snoops through a first snooping channel that a copy cache writes first data corresponding to a first function type, the copy cache is set in the local cache to which the first core belongs, a first snooping channel is set between the first core and a shared cache of the heterogeneous system, the shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache the data corresponding to the shared first function type;

[0024] A writing module, configured to, in response to the first write request, write the first data into the first sub-cache.

[0025] In a sixth aspect, an embodiment of the present application discloses a cache coherence device for a multi-core and multi-thread heterogeneous system, which may include:

[0026] A third communication module, configured to receive first synchronization information sent by a synchronization control device, where the first synchronization information is sent by the synchronization control device to a first core in the heterogeneous system to make the first core write the first data into the first sub-cache after snooping through a first snooping channel that a copy cache writes first data corresponding to a first function type, the copy cache is set in the local cache to which the first core belongs, a first snooping channel is set between the first core and a shared cache of the heterogeneous system, the shared cache includes the first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache the data corresponding to the shared first function type;

[0027] A reading module, configured to, in response to the first synchronization information, read the first data from the first sub-cache and synchronize it to the local cache.

[0028] In a seventh aspect, an embodiment of the present application discloses an electronic device, which may include:

[0029] A memory storing executable program code;

[0030] A processor coupled to the memory;

[0031] The processor calls the executable program code stored in the memory and executes a cache coherence method for a multi-core and multi-thread heterogeneous system disclosed in the first aspect, the second aspect, or the third aspect of the embodiments of the present application.

[0032] In an eighth aspect, an embodiment of the present application discloses a computer-readable storage medium storing a computer program, where the computer program causes a computer to execute a cache coherence method for a multi-core and multi-thread heterogeneous system disclosed in the first aspect, the second aspect, or the third aspect of the embodiments of the present application.

[0033] In a ninth aspect, an embodiment of the present application discloses a computer program product, which, when running on a computer, causes the computer to execute some or all of the steps of any one of the methods in the first aspect, the second aspect, or the third aspect.

[0034] In a tenth aspect, an embodiment of the present application discloses an application publishing platform for publishing a computer program product, where, when the computer program product runs on a computer, it causes the computer to execute some or all of the steps of any one of the methods in the first aspect, the second aspect, or the third aspect.

[0035] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0036] In the embodiments of the present application, a replica cache is set in the local cache of the first core of the heterogeneous system, a first snooping channel is set between the first core and the shared cache of the heterogeneous system, the shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the replica cache and is used to cache data corresponding to the first functional type shared. The synchronization control device snoops on the replica cache through the first snooping channel. When it snoops that the replica cache writes the first data corresponding to the first functional type, it sends a first write request to the first core. The first core responds to the first write request, writes the first data into the first sub-cache, and sends a first synchronization message to the second core in the heterogeneous system. The second core responds to the first synchronization message and reads the first data from the first sub-cache and synchronizes it to the local cache. It can be seen that in the heterogeneous system provided by the embodiments of the present application, by setting a first snooping channel between the first core and the shared cache of the heterogeneous system, it is possible to quickly snoop on the first data written into the replica cache of the first core based on this first snooping channel, and implement cache coherence between the first core and the second core through hardware technology. Further, a replica cache is set in the local cache of the first core, and a first sub-cache is set in the shared cache. The replica cache matches and corresponds to the first sub-cache and is only used to store data corresponding to the first functional type shared. The data is stored separately according to different functional types for cache coherence management, improving the data synchronization rate, and ultimately improving the performance of cache coherence between the first core and the second core. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0038] Figure 1a It is a schematic diagram of the storage architecture of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 1 of the present application;

[0039] Figure 1b It is a schematic diagram of the storage architecture of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 2 of the present application;

[0040] Figure 2 It is an interaction schematic diagram of the cache coherence method of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 1 of the present application;

[0041] Figure 3 It is an interaction schematic diagram of the cache coherence method of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 2 of the present application;

[0042] Figure 4 For Figure 1a It is a schematic diagram of achieving cache coherence between the CPU core and the NPU core in the heterogeneous system of;

[0043] Figure 5 It is an interaction schematic diagram of the cache coherence method of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 3 of the present application;

[0044] Figure 6 For Figure 1a It is a schematic diagram of achieving cache coherence between the CPU core and the CPU core, GPU core, and other devices in the heterogeneous system of;

[0045] Figure 7 For Figure 1a It is a schematic diagram of the interaction between the computing cache and computing storage of the NPU core in the heterogeneous system of;

[0046] Figure 8 It is a schematic diagram of the structure of the cache coherence device of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 1 of the present application;

[0047] Figure 9 It is a schematic diagram of the structure of the cache coherence device of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 2 of the present application;

[0048] Figure 10 It is a schematic diagram of the structure of the cache coherence device of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 3 of the present application;

[0049] Figure 11 The structural schematic diagram of the electronic device disclosed in the embodiments of the present invention. Specific embodiments

[0050] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0051] It should be noted that the terms "first", "second", "third", "fourth", etc. in the description and claims of the present application are used to distinguish different objects, rather than to describe a specific order. The terms "include" and "have" and any variations thereof in the embodiments of the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] Exemplarily, Figure 1a The storage architecture schematic diagram of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 1 of the present application. Figure 1a Shown is a heterogeneous system applicable to autonomous driving applications (abbreviated as heterogeneous system in the present application). In Figure 1a , the number of CPU cores is more than 2, up to 128 or more, including multiple CPU clusters, namely CPU cluster 1 to CPU cluster m (m is a positive integer). Each CPU cluster may include multiple CPU cores, namely CPU core 1 to CPU core n (n is a positive integer). Figure 1a It also includes an NPU cluster. The number of NPU cores included in the NPU cluster is also up to dozens, and there are 16 - 64 threads or more in each NPU core. Among them, CPU cores are good at processing programs with strong data dependencies and latency sensitivity by means of speculative execution, out-of-order execution, instruction set parallelism, and memory access-level parallelism, etc. NPU cores process large amounts of data and bandwidth-sensitive programs through a large amount of parallelism and large bandwidth.

[0053] In the storage structure hierarchy of this heterogeneous system, there are three levels of caches within the CPU cluster, namely, Level 1 cache, Level 2 cache, and Level 3 cache. The cache line size of the three-level cache is 64 bytes of data. The three-level cache helps the CPU cores make full use of temporal locality and spatial locality, and is suitable for data migration and synchronization between multiple cores. There are two levels of caches within the NPU cluster, namely, Level 1 cache and Level 2 cache. The cache line size of the two-level cache is 128 bytes of data, which is suitable for parallel programs with high parallelism and bandwidth sensitivity. The Shared Last Level Cache is a cache shared by CPU cores, NPU cores, GPU cores in the heterogeneous system, and other devices, etc.

[0054] In this heterogeneous system, according to different functional types, HostSystem Memory, System Memory, and Computing Memory are set in the SoC DDR. Among them, the Computing Memory is the storage exclusive to the NPU core, that is, the functional type is an exclusive feature, and only the corresponding Shared Computing Cache is set in the Level 2 cache in the NPU core. A direct read / write DDR path (Direct DDR path) is set between the shared computing cache and the SoC DDR, and the SoC DDR can be directly read / written. The Shared Last Level Cache includes the Shared Host System Cache and the Shared System Cache. The Shared Host System Cache is the corresponding cache of the host system storage in the Shared Last Level Cache, and the Shared System Cache is the corresponding cache of the system storage in the Shared Last Level Cache. The host system storage and the Shared Host System Cache are used to store data shared between CPU cores, between CPU cores and GPU cores, or with other devices. The system storage and the Shared System Storage are used to store data that can be shared by CPU cores, NPU cores, GPU cores, and other devices in the system. Further, the Shared System Cache corresponding to the system storage is set in the Level 2 cache corresponding to the NPU core, as the cache of the system storage in the NPU core, corresponding to the Shared System Cache in the Shared Last Level Cache.

[0055] Further, the network operation center (Noc) mechanism is adopted between the level-2 cache to which the NPU core belongs and each NPU core and the level-1 cache. However, the full coherent mechanism is adopted between the level-2 cache to which the NPU core belongs and the shared last-level cache through hardware. Therefore, there are a read channel, a write channel, and a snoop channel between the level-2 cache to which the NPU core belongs and the shared last-level cache. The CPU core can then snoop through this snoop channel whether the shared system cache in the level-2 cache to which the NPU core belongs is updated with data, realizing full cache coherence between the NPU core and the CPU core. The NPU is the core for processing data in parallel. A lot of data exchange and synchronization are required between the NPU core and the CPU core. By setting the full coherent mechanism in hardware, it is satisfied that the NPU core quickly writes data into the shared last-level cache or the SoC DDR, greatly reducing the latency of cache coherence and improving the data processing efficiency and the overall system performance.

[0056] Further, the full coherent mechanism is adopted between the shared last-level cache and the level-3 cache in the CPU cluster. Then, the full coherent mechanism is adopted between the level-3 cache and the level-2 cache, and between the level-2 cache and the level-1 cache. Therefore, there are a read channel, a write channel, and a snoop channel between the shared last-level cache and the CPU core. Through this snoop channel, it can be snooped whether there is data update in the level-3 cache in the CPU core, so as to realize cache coherence with the NPU core, as well as with the GPU core or other devices in a timely manner.

[0057] It should be noted in particular that the cache line sizes of the shared system cache stored in the shared last-level cache by the system and the shared system cache in the NPU cluster are both 128-byte data. The NPU core only reads and writes the shared system cache in the shared last-level cache, increasing the bandwidth for data exchange and cache coherence between the NPU core and the CPU core. The cache line size of the shared host cache stored in the shared last-level cache by the host system is 64-byte data, and the shared host cache stores data shared between CPU cores, between CPU cores and GPU cores, or with other devices. The shared computing cache in the second-level cache of the NPU cluster is exclusive to NPU cores. The NPU cores need to access it at high speed and have high bandwidth requirements. The shared computing cache is 128-byte data.

[0058] Figure 1a The I / O Coherent mechanism is adopted between the GPU core and other devices in the heterogeneous system shown and the shared last-level cache. There are only a read channel and a write channel between them and the shared last-level cache.

[0059] Exemplarily, such as Figure 1b shown, Figure 1b is a schematic diagram of the storage architecture of the multi-core and multi-thread heterogeneous system disclosed in the second embodiment of this application. Figure 1b Compared with Figure 1a the difference is that Figure 1b in [reference] only has a secondary cache, namely a level-1 cache and a level-2 cache. The cache line sizes of the level-1 cache and the level-2 cache are both 64-byte data; within the NPU cluster, there can be a tertiary cache, namely a level-1 cache, a level-2 cache, and a level-3 cache. The cache line sizes of the level-1 cache, the level-2 cache, and the level-3 cache are all 128-byte data. The full coherent mechanism is adopted between the shared last-level cache and the level-2 cache in the CPU cluster, and the full coherent mechanism is also adopted between the level-2 cache and the level-1 cache; the full coherent mechanism is adopted between the shared last-level cache and the level-3 cache within the NPU cluster, and the full coherent mechanism is also adopted between the level-3 cache and the level-2 cache. The Noc mechanism is adopted between the level-2 cache and the level-1 cache. The shared system cache and the shared computing cache are set in the level-3 cache of the NPU cluster.

[0060] It can be understood that this application Figure 1a andFigure 1b The disclosed heterogeneous system does not constitute a specific limitation to this application. In some other embodiments of this application, it can also be implemented by making deformations or changing the number of caches, etc. on the above heterogeneous system. For example, the CPU cluster can also be set to have four-level caches or more, and the NPU cluster can also be set to have four-level caches or more, etc. At this time, a shared system cache and a shared computing cache are set in the 4th-level cache of the NPU cluster. A full coherent mechanism is adopted between the 4th-level cache of the NPU cluster and the shared last level cache. A full coherent mechanism is adopted between the 4th-level cache of the NPU cluster and the 3rd-level cache, and between the 3rd-level cache and the 2nd-level cache.

[0061] Based on the above introduction, embodiments of this application disclose a cache coherence method, apparatus, and device for a multi-core and multi-thread heterogeneous system, which can improve the performance of full cache coherence between the kernels of the heterogeneous system, and can also store data separately according to different functional types for cache coherence management, improve the data synchronization rate, and the cache line sizes of the data between the first kernel and the second kernel match, which is beneficial to accelerating cache coherence.

[0062] Next, the technical solution of this application will be introduced in detail through specific embodiments. First, please refer to Figure 2 , Figure 2 is an interaction schematic diagram of the cache coherence method for the multi-core and multi-thread heterogeneous system disclosed in the first embodiment of this application; as Figure 2 shown, the cache coherence method for the multi-core and multi-thread heterogeneous system may include:

[0063] 201. The synchronization control device snoops on the replica cache through the first snooping channel. The replica cache is set in the local cache of the first kernel in the heterogeneous system. A first snooping channel is set between the first kernel and the shared cache of the heterogeneous system. The shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the replica cache and is used to cache data corresponding to the first functional type shared.

[0064] Among them, the synchronization control device can be a controller in the heterogeneous system or an independent device, and is used to manage and control the data exchange and synchronization between the shared cache in the heterogeneous system and each kernel.

[0065] In the embodiments of the present application, in a heterogeneous system, there are multiple first cores and multiple second cores. The shared cache in the heterogeneous system is used for sharing between the first cores and the second cores. A replica cache is set in the local cache of the first core. The shared cache includes a first sub-cache, and the first sub-cache and the replica cache are matched correspondingly. The replica cache can be used as a replica of the first sub-cache in the first core. The first sub-cache and the replica cache are used to cache data corresponding to the first functional type shared, and are only used to cache data that meets the first functional type, so as to manage cache coherence according to the functional type. The first sub-cache is the corresponding cache of the first storage in the shared cache in the heterogeneous system, and the replica cache is the corresponding cache of the first storage in the local cache of the first core.

[0066] A first snooping channel is set between the local cache of the first core and the shared cache. Through the first snooping channel, it can be snooped in real time whether there is data update in the replica cache, that is, whether there is new data written, and the data written into the replica cache meets the first functional type, and the first functional type is the type used for sharing between the first core and the second core. Among them, the first snooping channel is implemented by adopting a Full Coherent mechanism in the hardware design between the local cache of the first core and the shared cache. At the same time, there are also a read channel and a write channel between the first core and the shared cache. Among them, the read channel and the write channel adopt unidirectional reading and writing, that is, the first core can read data from the shared cache through the read channel, and the first core can write data to the shared cache through the write channel. It should be noted that when the first core reads and writes data in the shared cache, it only reads and writes data in the first sub-cache. Therefore, the first core reads data from the first sub-cache through the read channel, and the first core writes data to the first sub-cache through the write channel.

[0067] Exemplarily, the heterogeneous system disclosed in the embodiments of the present application may be Figure 1a or the multi-core and multi-thread heterogeneous system shown in Figure 1b. The first core may be the NPU core therein, and the second core is the CPU core therein. The local cache of the first core includes a level 2 cache as shown in Figure 1a or a level 2 cache and a level 3 cache as shown in Figure 1b . The shared cache is the shared last-level cache therein, and the first snooping channel is the level 2 cache (such as Figure 1a ) or the level 3 cache (such as Figure 1b)The snoop channel between it and the shared last-level cache. The first sub-cache in the shared cache is the shared system cache in the shared last-level cache among them. The replica cache is the shared system cache set in the level-2 cache (as shown in Figure 1a ) or level-3 cache (as shown in Figure 1b ) of the NPU cluster, and the first storage is the system storage. Combining Figure 1a or Figure 1b , the first function type is specifically the type shared by NPU cores, CPU cores, GPU cores, and other devices.

[0068] Furthermore, it should be noted that the replica cache of the first core is shared by all the first cores in the heterogeneous system. Combining Figure 1a or Figure 1b , the level-2 cache (as shown in Figure 1a ) or level-3 cache (as shown in Figure 1b ) of the NPU cluster is shared by all the NPU cores within the NPU cluster.

[0069] 202. When the synchronization control device snoops that the replica cache writes the first data corresponding to the first function type, it sends a first write request to the first core so that the first core writes the first data into the first sub-cache.

[0070] It should be noted that the first data is the data corresponding to the first function type. The first data is the data newly written into the replica cache by the first core, and the first data has not been synchronously written into the shared cache by the first core yet. Then, the synchronization control device snoops through this first snoop channel and sends a first write request to the first core. This first write request is used to request the first core to write the first data newly written into the replica cache into the first sub-cache for sharing with the second core.

[0071] It should be noted that the first core can be specifically the core that writes the first data into the replica cache. In the embodiment of this application, the synchronization control device directly sends a first read / write request to this first core.

[0072] 203. The first core receives the first write request and, in response to this first write request, writes the first data into the first sub-cache.

[0073] Correspondingly, after receiving this first write request, the first core, in response to this first write request, writes the first data in the replica cache into the first sub-cache. And there is a write channel between the first core and the shared cache, and the first core writes the first data into the first sub-cache through this write channel.

[0074] Among them, combining the above introduction, the first write request is sent by the synchronization control device when it snoops through the first snoop channel that the replica cache writes the first data corresponding to the first function type.

[0075] Optionally, after writing the first data to the first sub-cache, the first core may send a first response message to the synchronization control device. After receiving the first response message, the synchronization control device determines that the first data has been written to the first sub-cache and executes step 204.

[0076] 204. The synchronization control device sends first synchronization information to the second core in the heterogeneous system, so that the second core reads the first data from the first sub-cache and synchronizes it to the local cache.

[0077] Wherein, the control unit also sends the first synchronization information to the second core, and the first synchronization information is used to notify the second core that there is data in the shared cache (or specifically the first sub-cache) that needs to be synchronized.

[0078] In step 204, the synchronization control device sends the first synchronization information to each second core in the heterogeneous system to achieve cache coherence.

[0079] 205. The second core receives the first synchronization information, and in response to the first synchronization information, reads the first data from the first sub-cache and synchronizes it to the local cache.

[0080] Correspondingly, after receiving the first synchronization information, the second core reads the first data from the first sub-cache in response to the first synchronization information, and then synchronizes it to the local cache.

[0081] Wherein, the first synchronization information is sent by the synchronization control device to the first core in the heterogeneous system to make the first core write the first data to the first sub-cache after the synchronization control device snoops through the first snooping channel that the replica cache writes the first data corresponding to the first function type.

[0082] There are a read channel (Read Channel) and a write channel (WriteChannel) between the local cache of the second core and the shared cache. The second core reads the first data from the first sub-cache through the read channel (Read Channel) and synchronizes it to the local cache. Exemplarily, the local cache of the second core includes Figure 1a the level 1 cache, level 2 cache, and level 3 cache in the CPU core in, or the local cache of the second core includes Figure 1b the level 1 cache and level 2 cache in the CPU core in.

[0083] In the embodiment of the present application, after the first kernel writes the first data to the copy cache, the synchronization control device snoops through the first snooping channel that the copy cache writes the first data, and then sends a first write request to the first kernel, requesting the first kernel to write the first data to the first sub-cache of the shared cache, and sending a first synchronization message to the second kernel, so that the second kernel synchronizes the first data to the local cache, realizing the cache consistency between the second kernel and the first kernel.

[0084] Optionally, the heterogeneous system in the embodiment of the present application may further include, for example, Figure 1a or Figure 1b the GPU kernel and other devices in. In the embodiment of the present application, the GPU kernel and other devices are used as the second other kernels. Then, after step 202 is executed, the following steps are further executed: sending a fourth synchronization message to the second other kernels in the heterogeneous system, so that the second other kernels read the first data from the first sub-cache and synchronize it to the local cache. The second other kernels are all kernels in the heterogeneous system except the first kernel and the second kernel. In this embodiment, the first sub-cache is used for sharing by the first kernel, the second kernel, and the second other kernels. The first data written by the first kernel to the first sub-cache will also be synchronized in the second other kernels. Therefore, the synchronization control device will also send a fourth synchronization message to the second other kernels, so that the second other kernels complete data synchronization, realizing the complete cache consistency of the system.

[0085] Therefore, in the heterogeneous system provided by the embodiment of the present application, a first snooping channel is set between the first kernel and the shared cache of the heterogeneous system. Based on this first snooping channel, the first data written to the copy cache of the first kernel can be quickly snooped. Through hardware technology, the cache consistency between the first kernel and the second kernel is realized. Further, a copy cache is set in the local cache of the first kernel, and a first sub-cache is set in the shared cache. The copy cache and the first sub-cache are matched and corresponding, and are only used to store data corresponding to the first function type of sharing. The data is stored separately according to different function types for cache consistency management, improving the data synchronization rate, and finally improving the performance of the cache consistency between the first kernel and the second kernel. Especially when the first kernel is an NPU kernel and the second kernel is a CPU kernel, through the above embodiment, the CPU kernel can timely realize the cache consistency of the shared data with the NPU kernel.

[0086] Please refer to Figure 3 , Figure 3 which is an interaction schematic diagram of the cache consistency method of the multi-core and multi-thread heterogeneous system disclosed in the second embodiment of the present application; as Figure 3 shown, the cache consistency method of the multi-core and multi-thread heterogeneous system may include:

[0087] 301. The synchronization control device snoops on the local cache of the second core through the second snooping channel, and the second snooping channel is set between the local cache of the second core and the shared cache.

[0088] Among them, the second snooping channel is set between the local cache of the second core and the shared cache. Through the second snooping channel, it can be snooped in real time whether there is data update in the local cache of the second core, that is, whether new data is written. And the data written into the local cache of the second core meets the first functional type, and the first functional type is the type shared by the first core and the second core. Among them, the second snooping channel is implemented by adopting a Full Coherent mechanism in the hardware design between the local cache of the second core and the shared cache. At the same time, there are also a read channel and a write channel between the second core and the shared cache. Among them, the read channel and the write channel adopt unidirectional reading and writing, that is, the second core can read data from the first sub-cache of the shared cache through the read channel (ReadChannel), and the second core can write data to the first sub-cache of the shared cache through the write channel (WriteChannel).

[0089] Exemplarily, the second core is Figure 1a or Figure 1b the CPU core shown. The local cache of the second core includes, for example, Figure 1a the level 1 cache, level 2 cache and level 3 cache in the CPU core in Figure 1b or the local cache of the second core includes

[0090] 302. When the synchronization control device snoops that the second data corresponding to the first functional type is written into the local cache of the second core, it sends a second write request to the second core so that the second core writes the second data into the first sub-cache.

[0091] It should be noted that the second data is the data corresponding to the first functional type. The second data is the data newly written by the second core into the local cache, and the second data has not been synchronously written by the second core into the first sub-cache of the shared cache. Then the synchronization control device snoops through the second snooping channel and sends a second write request to the second core. The second write request is used to request the second core to write the second data newly written into the local cache into the first sub-cache for sharing with the first core.

[0092] It should be noted that the second data written by the second kernel to the first sub-cache is only used for sharing with the first kernel. However, the first data written by the first kernel to the first sub-cache, in addition to being able to be shared with the second kernel, when there are also other second kernels in the heterogeneous system (such as Figure 1a or Figure 1b GPU kernels and other devices in the heterogeneous system), can also be shared with the other second kernels. By partitioning the cache according to functional types, fast data exchange between the first kernel and the second kernel can be achieved, not only realizing full caching between the two, but also improving the rate of cache coherence.

[0093] 303. The second kernel receives a second write request and, in response to the second write request, writes the second data to the first sub-cache.

[0094] Correspondingly, after receiving the second write request, the second kernel, in response to the second write request, writes the second data in its local cache to the first sub-cache. And there is a write channel between the second kernel and the shared cache, and the second kernel writes the second data to the first sub-cache through this write channel.

[0095] Among them, in combination with the above introduction, the second write request is sent by the synchronization control device when it snoops through the second snooping channel that the replica cache writes the second data corresponding to the first functional type.

[0096] Optionally, after writing the second data to the first sub-cache, the second kernel can send a second response message to the synchronization control device. After receiving the second response message, the synchronization control device determines that the second data is written to the first sub-cache and executes step 304.

[0097] 304. The synchronization control device sends second synchronization information to the first kernel so that the first kernel reads the second data from the first sub-cache and synchronizes it to the replica cache.

[0098] Among them, the control unit also sends second synchronization information to the first kernel, and this second synchronization information is used to notify the first kernel that there is data in the shared cache (or specifically the first sub-cache) that needs to be synchronized.

[0099] 305. The first kernel receives the second synchronization information and, in response to the second synchronization information, reads the second data from the first sub-cache and synchronizes it to the replica cache.

[0100] Among them, the above second synchronization information is sent by the synchronization control device after snooping through the second snooping channel that the local cache of the second kernel writes the second data corresponding to the first functional type, sending a second write request to the second kernel to make the second kernel write the second data to the first sub-cache.

[0101] Correspondingly, after receiving the second synchronization information, the first core reads the second data from the first sub-cache in response to the second synchronization information, and then synchronizes it to the replica cache.

[0102] There are read channels and write channels between the local cache of the first core and the shared cache. The first core reads the second data from the first sub-cache through the read channel and synchronizes it to the replica cache.

[0103] In the embodiment of the present application, after the second core writes the second data to the local cache, the synchronization control device snoops the first data written to the local cache through the second snooping channel, and then sends a second write request to the second core, requesting the second core to write the second data to the first sub-cache of the shared cache, and sending the second synchronization information to the first core, so that the first core synchronizes the second data to the local cache, realizing cache consistency between the first core and the second core.

[0104] Therefore, in the heterogeneous system provided by the embodiment of the present application, a second snooping channel is set between the second core and the shared cache of the heterogeneous system. Based on this second snooping channel, the second data written to the local cache of the second core can be quickly snooped and then synchronized to the shared cache and the replica cache of the first core, realizing cache consistency between the first core and the second core through hardware technology. Further, a replica cache is set in the local cache of the first core, and a first sub-cache is set in the shared cache. The replica cache and the first sub-cache are matched and corresponding, and are only used to store data corresponding to the first functional type shared. The data is stored separately according to different functional types for cache consistency management, improving the data synchronization rate, and ultimately enhancing the performance of cache consistency between the first core and the second core.

[0105] Optionally, in the embodiment of the present application, the cache line sizes of the above-mentioned replica cache and the first sub-cache are both 128 bytes, which satisfies the matching of the cache lines of the first sub-cache and the replica cache. Furthermore, when the first core writes the data of a cache line of the replica cache to the cache line of the first sub-cache, it only takes one clock cycle. Similarly, when the first core reads data from the first sub-cache, reading a cache line of data from the first sub-cache just fits into a cache line of the replica cache, accelerating the processing efficiency.

[0106] Exemplarily, please refer to Figure 4 , Figure 4 For Figure 1a the schematic diagram of realizing cache consistency between the CPU core and the NPU core in the heterogeneous system of; from Figure 4It can be seen that there is system storage in the SoC DDR. Correspondingly, a shared system cache corresponding to the system storage is set in the shared last-level cache, and a shared system cache corresponding to the system storage is set in the second-level cache corresponding to the NPU cluster. The cache line size of both caches is 128 bytes. The second-level cache of the NPU core and the shared last-level cache adopt a Full Coherent mechanism, with read channels, write channels, and snooping channels. The read channels and write channels can only be used for the NPU core to read and write to the shared last-level cache, performing unidirectional read and write operations. The local cache of the CPU core, Figure 4 only shows the third-level cache corresponding to the CPU core, which also adopts a Full Coherent mechanism with the shared last-level cache, having read channels, write channels, and snooping channels. It is also a unidirectional read and write from the CPU core to the shared last-level cache. Based on this schematic diagram, when the NPU core writes new data to the shared system cache in the second-level cache, the synchronization control device detects the newly written data through the snooping channel between the second-level cache of the NPU core and the shared last-level cache. The synchronization control device will notify the NPU core through a write request to write the above new data through the write channel to the shared system cache in the shared last-level cache. Then, the synchronization control device notifies all CPU cores through synchronization information. The CPU cores read the new data from the shared system cache in the shared last-level cache through their read channels and then synchronize it to the third-level cache (of course, it can also be synchronized to the second-level cache or the first-level cache, Figure 4 only shown as the third-level cache for illustration), thereby synchronizing the data of the NPU core to the CPU core.

[0107] Conversely, after a certain CPU core writes new data to the third-level cache (of course, it can also be written to the second-level cache or the first-level cache, Figure 4 only shown as the third-level cache for illustration), the synchronization control device detects the newly written data through the snooping channel between the third-level cache of the CPU core and the shared last-level cache. The synchronization control device will notify the CPU core through a write request to write the above new data through the write channel to the shared system cache in the shared last-level cache. Then, the synchronization control device notifies all NPU cores through synchronization information. The NPU cores read the new data from the shared system cache in the shared last-level cache through their read channels and then synchronize it to the shared system cache in the second-level cache, thereby synchronizing the data of the CPU core to the NPU core, achieving full cache coherence between the NPU core and the CPU core.

[0108] In addition, both storage and caches are divided according to functional types to achieve unified cache management, which can also improve the rate of cache coherence.

[0109] Please refer to Figure 5 ,Figure 5 Interaction schematic diagram of the cache coherence method for the multi-core and multi-thread heterogeneous system disclosed in Embodiment 3 of the present application; in Figure 5 it, the cache coherence method for the multi-core and multi-thread heterogeneous system may include:

[0110] 501. The synchronization control device snoops on the local cache of the second core through the second snooping channel, and the second snooping channel is set between the local cache of the second core and the shared cache.

[0111] In the embodiment of the present application, the shared cache further includes a second sub-cache, which is used to store data corresponding to the second functional type shared, and the second functional type indicates that the data is shared by other cores except the first core, that is, the first core will not read the data in the second sub-cache.

[0112] Correspondingly, the second sub-cache is the corresponding cache in the shared cache of the second storage in the heterogeneous system. Exemplarily, the second storage may be Figure 1a or Figure 1b the host system storage in, and the second sub-cache is Figure 1a or Figure 1b the shared host system cache in, which is mainly used to store data shared between CPU cores and will also be provided for sharing by, for example, GPU cores or other devices.

[0113] It should also be noted that the first sub-cache and the second sub-cache in the shared cache in the embodiment of the present application are divided according to the functional type, which is equivalent to dividing the shared cache into two regions. The first sub-cache corresponds to one region, and the second sub-cache corresponds to the second region, and there will be no interference between the two.

[0114] 502. When the synchronization control device snoops through the second snooping channel that the local cache of the second core writes the third data corresponding to the second functional type, it sends a third write request to the second core so that the second core writes the third data into the second sub-cache.

[0115] It should be noted that the third data is the data corresponding to the second functional type, the third data is the data newly written by the second core into the local cache, and the third data has not been synchronously written by the second core into the second sub-cache of the shared cache yet, and then the synchronization control device snoops through the second snooping channel and sends a third write request to the second core. The third write request is used to request the second core to write the newly written third data in the local cache into the second sub-cache.

[0116] 503. The second core receives the third write request and, in response to the third write request, writes the third data into the second sub-cache.

[0117] Among them, the third write request is sent when the synchronization control device snoops through the second snooping channel that the local cache of the second core writes the third data corresponding to the second function type.

[0118] Correspondingly, after receiving the third write request, the second core, in response to the third write request, writes the third data in the local cache into the second sub-cache. And there is a write channel between the second core and the shared cache, and the second core writes the third data into the second sub-cache through this write channel.

[0119] Optionally, the second core may send a third response message to the synchronization control device after writing the third data into the second sub-cache. After receiving the third response message, the synchronization control device determines that the third data is written into the second sub-cache and executes step 504.

[0120] 504. The synchronization control device sends third synchronization information to the first other core in the heterogeneous system, so that the first other core reads the third data from the second sub-cache and synchronizes it to the local cache. The first other core is all cores in the heterogeneous system except the first core and the second core that writes the third data.

[0121] Among them, the first other core is all cores in the heterogeneous system except the first core and the second core that writes the third data. When there are only the first core and the second core in the heterogeneous system, the first other core is the remaining second core except the second core that writes the third data. When there are other cores in the heterogeneous system, the first other core also includes other cores. Exemplarily, the first other core is Figure 1a or Figure 1b the CPU cores (excluding the CPU core that writes the third data), GPU cores, and other devices in

[0122] Among them, the control unit also sends third synchronization information to the first other core. The third synchronization information is used to notify the first other core that there is data in the second sub-cache that needs to be synchronized.

[0123] 505. The first other core receives the third synchronization information and, in response to the third synchronization information, reads the third data from the second sub-cache and synchronizes it to the local cache.

[0124] Among them, the above third synchronization information is sent after the synchronization control device snoops through the second snooping channel that the local cache of the second core writes the third data corresponding to the second function type, and sends a third write request to the second core to make the second core write the third data into the second sub-cache.

[0125] Correspondingly, after receiving the third synchronization information, the first other core, in response to the third synchronization information, reads the third data from the second sub-cache and then synchronizes it to the local cache.

[0126] The second other-core local cache and the shared cache have a Read Channel and a Write Channel. The second other core reads the third data from the second sub-cache through the Read Channel and synchronizes it to the local cache.

[0127] In the embodiments of the present application, after the second core writes the third data to the local cache, the synchronization control device snoops through the second snooping channel that the third data is written to the local cache, and then sends a third write request to the second core, requesting the second core to write the third data to the second sub-cache of the shared cache, and sending third synchronization information to the first other core, so that the second core synchronizes the third data to the local cache, realizing cache coherence between the second core and the first other core.

[0128] It should be specifically noted that the cache line sizes of the local cache of the second core and the second sub-cache are 64-byte data, satisfying the matching of the cache lines between the local cache of the second core and the second sub-cache. Exemplarily, such as Figure 1a the L1 cache, L2 cache, and L3 cache of the CPU core in are all 64-byte data, and the cache line of the shared host system cache in the last-level shared cache is also 64-byte data.

[0129] Exemplarily, please refer to Figure 6 , Figure 6 For Figure 1a a schematic diagram of realizing cache coherence between CPU cores, GPU cores, and other devices in a heterogeneous system of, as can be seen from Figure 6 that there is host system storage in the SoC DDR, and a corresponding shared host system cache for the host system storage is set in the last-level shared cache. There are a Read Channel, a Write Channel, and a Snooping Channel between the L3 cache (only exemplified by the L3 cache in Figure 1a ) of the CPU core and the shared host system cache. There are a Read Channel and a Write Channel between the GPU core and the shared host system cache, and there are also only a Read Channel and a Write Channel between other devices and the shared host system cache. Thus, when a certain CPU core writes new data of the second functional type to the L3 cache, the synchronization control device snoops through the snooping channel and then sends a write request, so that the CPU core writes the new data to the shared host system cache through the Write Channel, and then sends synchronization information to other CPU cores, GPU cores, and other devices, so that they can read the new data from the shared host system cache through their respective Read Channels and then synchronize it to the local cache, realizing cache coherence between CPU cores, between CPU cores and GPU cores, and between CPU cores and other devices.

[0130] It should also be noted that a private cache is further provided in the local cache of the first core in the embodiments of the present application. The private cache is used to store data corresponding to the third functional type, and the data corresponding to the third functional type is for private use among the first cores (that is, exclusive to the first cores).

[0131] Among them, the first functional type indicates that the data in the private cache is private (exclusive) to the first core, and neither the second core nor other cores in the system will access it. Optionally, the access permission of the private cache is implemented at the software level, managed through a page table. By setting the access permission in the page table, the access permission is only set for the NPU core, and not for the CPU core, GPU core, and other devices in the heterogeneous system. When the CPU core, GPU core, or other devices in the system access it, a page fault will be reported.

[0132] Furthermore, a third storage corresponding to the private cache is also provided in the storage of the heterogeneous system. The cache line size of the private cache is 128 bytes, with high bandwidth, enabling the first core to perform fast read and write operations on it, and meeting the bandwidth sensitivity of the program executed by the first core.

[0133] Exemplarily, the private cache can be Figure 1a the shared computing cache in Figure 1a and the third storage is the computing storage in

[0134] It should be noted that the replica cache and the private cache are separate, which is equivalent to dividing the local cache of the first core into two regions, one region corresponding to the replica cache and the other region corresponding to the private cache, and the two do not interfere with each other.

[0135] Furthermore, exemplarily, please refer to Figure 7 Figure 7 is a schematic diagram of the interaction between the computing cache and the computing storage of the NPU core in the heterogeneous system of Figure 1a As can be seen from Figure 7 there is computing storage in the SoC DDR, and a computing cache corresponding to the computing storage is set in the secondary cache corresponding to the NPU core. The cache line size of the computing cache is 128 - byte data. There is a direct read - write DRR path between the NPU core and the computing storage. The NPU core can directly write data (or the data in the computing cache) into the computing storage, or read data from the computing storage (or read it into the computing cache).

[0136] Please refer to Figure 8 Figure 8 is a schematic diagram of the structure of the cache coherence device of the multi - core and multi - thread heterogeneous system disclosed in the first embodiment of the present application; as shown in Figure 8 ​As shown, the cache coherence device of the multi-core and multi-thread heterogeneous system may include:

[0137] A snooping module 801, configured to snoop on a replica cache through a first snooping channel, where the replica cache is set in a local cache of a first core in the heterogeneous system, and the first snooping channel is set between the first core and a shared cache of the heterogeneous system. The shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the replica cache and is used to cache data corresponding to a first functional type shared.

[0138] A first communication module 802, configured to send a first write request to the first core when it snoops that the replica cache writes a first data corresponding to the first functional type, so that the first core writes the first data into the first sub-cache.

[0139] The first communication module 802 is configured to send first synchronization information to a second core in the heterogeneous system, so that the second core reads the first data from the first sub-cache and synchronizes it to the local cache.

[0140] In some optional embodiments, the above-mentioned snooping module 801 is further configured to snoop on the local cache of the second core through a second snooping channel, and the second snooping channel is set between the local cache of the second core and the shared cache.

[0141] The above-mentioned first communication module 802 is further configured to send a second write request to the second core when it snoops that the local cache of the second core writes a second data corresponding to the first functional type, so that the second core writes the second data into the first sub-cache; and send second synchronization information to the first core, so that the first core reads the second data from the first sub-cache and synchronizes it to the replica cache.

[0142] In some optional embodiments, the above-mentioned first communication module 802 is further configured to send a third write request to the second core when it snoops through the second snooping channel that the local cache of the second core writes a third data corresponding to a second functional type, so that the second core writes the third data into a second sub-cache; and send third synchronization information to a first other core in the heterogeneous system, so that the first other core reads the third data from the second sub-cache and synchronizes it to the local cache, where the first other core is all cores in the heterogeneous system except the first core and the second core that writes the third data.

[0143] In some alternative embodiments, the first communication module 802 is further configured to, when snooping that the replica cache writes the first data corresponding to the first functional type, send a first write request to the first kernel, so that after the first kernel writes the first data into the first sub-cache, send fourth synchronization information to other second kernels in the heterogeneous system, so that the other second kernels read the first data from the first sub-cache and synchronize it to the local cache, and the other second kernels are all kernels in the heterogeneous system except the first kernel and the second kernel.

[0144] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a cache coherence device of a multi-core and multi-thread heterogeneous system disclosed in Embodiment 2 of the present application; as Figure 9 shown, the cache coherence device of the multi-core and multi-thread heterogeneous system may include:

[0145] A second communication module 901, configured to receive a first write request sent by a synchronization control device, where the first write request is sent by the synchronization control device when snooping through a first snooping channel that a replica cache writes first data corresponding to a first functional type, the replica cache is set in the local cache to which the first kernel belongs, a first snooping channel is set between the first kernel and a shared cache of the heterogeneous system, the shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the replica cache and is used to cache the shared data corresponding to the first functional type.

[0146] A writing module 902, configured to write the first data into the first sub-cache in response to the first write request.

[0147] In some alternative embodiments, Figure 9 the device shown includes a first reading module (not shown), where the second communication module 901 is further configured to receive second synchronization information sent by the synchronization control device, and the second synchronization information is sent by the synchronization control device after snooping through a second snooping channel that the local cache of the second kernel writes second data corresponding to the first functional type, and then sending a second write request to the second kernel to cause the second kernel to write the second data into the first sub-cache, and a second snooping channel is set between the local cache of the second kernel and the shared cache.

[0148] The first reading module is configured to read the second data from the first sub-cache and synchronize it to the replica cache in response to the second synchronization information.

[0149] Please refer to Figure 10 , Figure 10The structural schematic diagram of the cache coherence device of the multi-core and multi-thread heterogeneous system disclosed in Embodiment 3 of the present application; as Figure 10 shown, the cache coherence device of the multi-core and multi-thread heterogeneous system may include:

[0150] A third communication module 1001, configured to receive the first synchronization information sent by the synchronization control device. The first synchronization information is sent by the synchronization control device to the first kernel in the heterogeneous system to make the first kernel write the first data into the first sub-cache after the synchronization control device snoops through the first snooping channel that a copy cache writes the first data corresponding to the first function type. The copy cache is set in the local cache to which the first kernel belongs. The first snooping channel is set between the first kernel and the shared cache of the heterogeneous system. The shared cache includes the first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache the data corresponding to the shared first function type.

[0151] A reading module 1002, configured to read the first data from the first sub-cache and synchronize it to the local cache in response to the first synchronization information.

[0152] In some optional embodiments, Figure 10 the device shown further includes a first writing module (not shown). Among them, the above-mentioned third communication module 1001 is further configured to receive a second write request sent by the synchronization control device. The second write request is sent by the synchronization control device when it snoops through the second snooping channel that the local cache of the second kernel writes the second data corresponding to the first function type. The second snooping channel is set between the local cache of the second kernel and the shared cache.

[0153] The first writing module is configured to write the second data into the first sub-cache in response to the second write request.

[0154] Further optionally, the above-mentioned third communication module 1001 is further configured to receive a third write request sent by the synchronization control device. The third write request is sent by the synchronization control device when it snoops through the second snooping channel that the local cache of the second kernel writes the third data corresponding to the second function type.

[0155] The above-mentioned first writing module is further configured to write the third data into the second sub-cache in response to the third write request.

[0156] Please refer to Figure 11 , Figure 11 The structural schematic diagram of the electronic device disclosed in the embodiment of the present invention; Figure 11 the electronic device shown may include:

[0157] A memory 1101 storing executable program code;

[0158] A processor 1102 coupled to the memory 1101;

[0159] Wherein, the processor 1102 calls the executable program code stored in the memory 1101 and executes Figure 2 , Figure 3 , Figure 5 Some steps of any one of the methods.

[0160] An embodiment of the present application also discloses a computer-readable storage medium, which stores a computer program, wherein the computer program causes a computer to execute Figure 2 , Figure 3 , Figure 5 Any one of the disclosed methods.

[0161] An embodiment of the present application also discloses a computer program product, when the computer program product runs on a computer, it causes the computer to execute Figure 2 , Figure 3 , Figure 5 Some or all of the steps of any one of the disclosed methods.

[0162] An embodiment of the present application also discloses an application publishing platform, the application publishing platform is used to publish a computer program product, wherein, when the computer program product runs on a computer, it causes the computer to execute Figure 2 , Figure 3 , Figure 5 Some or all of the steps of any one of the disclosed methods.

[0163] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program, and this program can be stored in a computer-readable storage medium. The storage medium includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc memories, magnetic disc memories, tape memories, or any other computer-readable medium that can be used to set or store data.

[0164] The above has introduced in detail a cache coherence method, apparatus and device for a multi-core and multi-thread heterogeneous system disclosed in the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A cache coherence method for a multi-core and multi-thread heterogeneous system, characterized in that Applied to a synchronization control device, the method includes: Snooping on a copy cache through a first snooping channel, where the copy cache is set in the local cache of a first core belonging to a heterogeneous system, and the first snooping channel is set between the first core and a shared cache of the heterogeneous system. The shared cache includes a first sub-cache that matches and corresponds to the copy cache and is used to cache data corresponding to a first functional type shared among them; When it is snooped that the first data corresponding to the first functional type is written to the copy cache, sending a first write request to the first core so that the first core writes the first data to the first sub-cache; Sending first synchronization information to a second core in the heterogeneous system so that the second core reads the first data from the first sub-cache and synchronizes it to the local cache.

2. The method according to claim 1, wherein The method further includes: Snooping on the local cache of the second core through a second snooping channel, where the second snooping channel is set between the local cache of the second core and the shared cache; When it is snooped that the second data corresponding to the first functional type is written to the local cache of the second core, sending a second write request to the second core so that the second core writes the second data to the first sub-cache; Sending second synchronization information to the first core so that the first core reads the second data from the first sub-cache and synchronizes it to the copy cache.

3. The method according to claim 2, characterized in that, The shared cache further includes a second sub-cache that is used to store data corresponding to a second functional type shared among them; the method further includes: When it is snooped through the second snooping channel that the third data corresponding to the second functional type is written to the local cache of the second core, sending a third write request to the second core so that the second core writes the third data to the second sub-cache; Sending third synchronization information to a first other core in the heterogeneous system so that the first other core reads the third data from the second sub-cache and synchronizes it to the local cache, where the first other core is all cores in the heterogeneous system except the first core and the second core that writes the third data.

4. The method according to claim 1, wherein After the step of, when it is snooped that the first data corresponding to the first functional type is written to the copy cache, sending a first write request to the first core so that the first core writes the first data to the first sub-cache, the method further includes: Sending fourth synchronization information to a second other core in the heterogeneous system so that the second other core reads the first data from the first sub-cache and synchronizes it to the local cache, where the second other core is all cores in the heterogeneous system except the first core and the second core.

5. The method according to claim 1, characterized in that A private cache is further set in the local cache of the first core, and the private cache is used to store data corresponding to a third functional type, and the data corresponding to the third functional type is for private use among the first cores.

6. The method according to claim 5, wherein The cache line size of the copy cache is 128 bytes, the cache line size of the first sub-cache is 128 bytes, and the cache line size of the private cache is 128 bytes.

7. The method according to claim 3, wherein The cache line size of the second sub-cache is 64 bytes, and the cache line size of the local cache of the second core is 64 bytes.

8. A cache coherence method for a multi-core and multi-thread heterogeneous system, characterized in that, Applied to the first core in a heterogeneous system, the method includes: Receiving a first write request sent by a synchronization control device, where the first write request is sent by the synchronization control device when it snoops through a first snooping channel that the copy cache writes the first data corresponding to the first function type. The copy cache is set in the local cache to which the first core belongs, and the first snooping channel is set between the first core and the shared cache of the heterogeneous system. The shared cache includes a first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache the data corresponding to the shared first function type. In response to the first write request, writing the first data into the first sub-cache.

9. The method according to claim 8, characterized in that, The method further includes: Receiving second synchronization information sent by the synchronization control device, where the second synchronization information is sent by the synchronization control device after it snoops through a second snooping channel that the local cache of the second core writes the second data corresponding to the first function type, and then sends a second write request to the second core to cause the second core to write the second data into the first sub-cache. The second snooping channel is set between the local cache of the second core and the shared cache. In response to the second synchronization information, reading the second data from the first sub-cache and synchronizing it to the copy cache.

10. The method according to claim 9, characterized in that, The shared cache further includes a second sub-cache, and the second sub-cache is used to store the data corresponding to the shared second function type.

11. The method according to claim 8, wherein The local cache of the first core is further provided with a private cache, and the private cache is used to store the data corresponding to the third function type, and the data corresponding to the third function type is for private use among the first cores.

12. The method according to claim 11, wherein, The cache line size of the copy cache is 128 bytes, the cache line size of the first sub-cache is 128 bytes, and the cache line size of the private cache is 128 bytes.

13. The method according to claim 10, wherein The cache line size of the second sub-cache is 64 bytes, and the cache line size of the local cache of the second core is 64 bytes.

14. A cache coherence method for a multi-core and multi-thread heterogeneous system, characterized in that Applied to the second core in a heterogeneous system, the method includes: Receiving first synchronization information sent by a synchronization control device, where the first synchronization information is sent by the synchronization control device when it snoops through a first snooping channel that the copy cache writes the first data corresponding to the first function type, and then sends a first write request to the first core in the heterogeneous system to cause the first core to write the first data into the first sub-cache. The copy cache is set in the local cache to which the first core belongs, and the first snooping channel is set between the first core and the shared cache of the heterogeneous system. The shared cache includes the first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is used to cache the data corresponding to the shared first function type. In response to the first synchronization information, read the first data from the first sub-cache and synchronize it to the local cache.

15. The method according to claim 14, wherein The method further includes: Receiving a second write request sent by the synchronization control device, where the second write request is sent when the synchronization control device snoops through a second snooping channel that the local cache of the second core writes the second data corresponding to the first function type, and the second snooping channel is set between the local cache of the second core and the shared cache; In response to the second write request, write the second data into the first sub-cache.

16. The method according to claim 15, wherein The shared cache further includes a second sub-cache for storing data corresponding to a shared second function type; the method further includes: Receiving a third write request sent by the synchronization control device, where the third write request is sent when the synchronization control device snoops through the second snooping channel that the local cache of the second core writes the third data corresponding to the second function type; In response to the third write request, write the third data into the second sub-cache.

17. The method according to claim 14, wherein A private cache is further set in the local cache of the first core, and the private cache is used to store data corresponding to a third function type, and the data corresponding to the third function type is for private use among the first cores.

18. The method according to claim 17, wherein The cache line size of the replica cache is 128 bytes, the cache line size of the first sub-cache is 128 bytes, and the cache line size of the private cache is 128 bytes.

19. The method according to claim 16, wherein The cache line size of the second sub-cache is 64 bytes, and the cache line size of the local cache of the second core is 64 bytes.

20. A cache coherence device for a multi-core and multi-thread heterogeneous system, characterized in that, It includes: A snooping module for snooping on the replica cache through a first snooping channel, where the replica cache is set in the local cache of the first core in the heterogeneous system, a first snooping channel is set between the first core and the shared cache of the heterogeneous system, and the shared cache includes a first sub-cache that matches and corresponds to the replica cache and is used to cache data corresponding to a shared first function type; A first communication module for, when snooping that the replica cache writes the first data corresponding to the first function type, sending a first write request to the first core so that the first core writes the first data into the first sub-cache; The first communication module is used to send first synchronization information to the second core in the heterogeneous system so that the second core reads the first data from the first sub-cache and synchronizes it to the local cache.

21. A cache coherence device for a multi-core and multi-thread heterogeneous system, characterized in that, It includes: A second communication module for receiving a first write request sent by the synchronization control device, where the first write request is sent when the synchronization control device snoops through the first snooping channel that the replica cache writes the first data corresponding to the first function type, the replica cache is set in the local cache of the first core, a first snooping channel is set between the first core and the shared cache of the heterogeneous system, and the shared cache includes a first sub-cache that matches and corresponds to the replica cache and is used to cache the shared data corresponding to the first function type; A write module, configured to write the first data into the first sub-cache in response to the first write request.

22. A cache coherence device for a multi-core and multi-thread heterogeneous system, characterized in that Comprising: A third communication module, configured to receive first synchronization information sent by a synchronization control device. The first synchronization information is sent by the synchronization control device to a first core in the heterogeneous system to cause the first core to write the first data into the first sub-cache after the synchronization control device snoops, through a first snooping channel, that a copy cache writes the first data corresponding to a first function type. The copy cache is set in a local cache to which the first core belongs. The first snooping channel is set between the first core and a shared cache of the heterogeneous system. The shared cache includes the first sub-cache, and the first sub-cache matches and corresponds to the copy cache and is configured to cache data corresponding to a shared first function type. A read module, configured to read the first data from the first sub-cache and synchronize the first data to the local cache in response to the first synchronization information.

23. An electronic device, characterized in that, Comprising: A memory storing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the cache coherence method of the multi-core and multi-thread heterogeneous system according to any one of claims 1-19.

24. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, the steps of the method according to any one of claims 1-19 are implemented.

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