Stacked chip architecture modeling method and stacked chip architecture modeling system

Abstract

The present invention provides a stacked chip architecture modeling method and stacked chip architecture modeling system. The method includes dividing an on-chip chip to be modeled into multiple cores; modeling the chip using a three-level joint modeling approach, performing core-level modeling, dielectric layer modeling, and substrate-level modeling respectively; arranging the placement of each core based on the timing of critical paths, total bus length, and factors such as overlong paths; optimizing the positions of components within the core based on the internal and external connections of the core, and based on the weights of the core's internal and external netlists or user input information, and adjusting the positions of microbumps mapped to each component; automatically routing based on the arrangement of each core, removing conflicting networks in the routing, performing maze routing in the removed areas, and finding the optimal routing path. The system is used to implement the above method. The present invention provides a one-stop chip design EDA tool that can improve chip design accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of stacked chip production and manufacturing, and in particular to a stacked chip architecture modeling method and a stacked chip architecture modeling system for implementing the method. Background Art

[0002] With the development of chip technology, three-dimensional stacked chips have been widely used. The design process of three-dimensional stacked chips requires modeling of the three-dimensional chip. Currently, the most common modeling method is to use electronic design automation (EDA) tools. However, existing EDA tools are technically closed and have high licensing fees. In addition to the two issues mentioned above, current EDA tools also commonly suffer from the following problems:

[0003] First, the modeling process is fragmented and lacks system-level integration. Existing EDA tools mostly focus on single-step operations, such as through-silicon via modeling, thermal analysis, or signal integrity simulation. They lack full-process integration, from architectural design and physical modeling to multi-physics simulation. This forces designers to stitch data across platforms, resulting in low stacked chip design efficiency. Multiple data conversions, such as those required for electrical-thermal-stress coupling analysis during interposer design, often affect the design accuracy of the stacked chip.

[0004] Second, lack of customizability and adaptability. Current EDA tools struggle to adapt to the diverse process requirements of chip designers and manufacturers. For example, they cannot meet requirements for heterogeneous chip integration and custom chiplet interconnects. Existing modeling systems typically pre-set fixed parameter templates and lack support for emerging materials (such as glass substrates) or special packaging structures (such as partial shielding layers), limiting chip design flexibility.

[0005] Third, they consume large amounts of resources and have high technical barriers to entry. Because stacked chip modeling involves massive meshing and multi-physics field calculations, existing EDA tools rely heavily on hardware resources (such as GPU acceleration and distributed computing). Manufacturers and designers need computers with very high hardware resources to use existing EDA tools, limiting their widespread application. Summary of the Invention

[0006] A first object of the present invention is to provide a stacked chip architecture modeling method that can avoid the need to convert data back and forth during the design process, thereby affecting the design accuracy.

[0007] A second object of the present invention is to provide a stacked chip architecture modeling system for implementing the above-mentioned stacked chip architecture modeling method.

[0008] To achieve the first purpose of the present invention, the stacked chip architecture modeling method provided by the present invention includes dividing the on-chip chip to be modeled into multiple core particles; modeling the chip using a three-level joint modeling method: when modeling at the core particle level, each divided bare chip is modeled, and the internal components of the core particle are placed according to the connection relationship of the netlist; when modeling at the dielectric layer level, the dielectric layer is modeled according to the factor of the idle area, and the size of the dielectric layer is determined; when modeling at the substrate level, the substrate is modeled according to the factor of the idle area; the placement position of each core particle is arranged according to the timing of the critical path, the total bus length and the ultra-long path factors; according to the connection relationship between the inside and outside of the core particle, and according to the weight of the internal netlist and external netlist of the core particle or user input information, the position of the internal components of the core particle is optimized, and the position of the micro-bump mapped to each component is adjusted; automatic routing is performed based on the arrangement position of each core particle, and the conflicting networks in the routing are removed, maze routing is performed on the area where the routing is removed, and the optimal routing path is found.

[0009] It can be seen from the above scheme that the present invention provides a one-stop complete design solution for the design of stacked chips. From chip division, core particle arrangement to automated wiring, all can be implemented in the same EDA tool. Designers do not need to switch back and forth between multiple different tools, avoiding the loss of accuracy caused by time switching, thereby ensuring that the designed stacked chips have higher accuracy.

[0010] In addition, the present invention adopts a three-level joint modeling method to model the chip, which makes the chip modeling more efficient and allows designers to quickly complete the steps of arranging the internal components of the core particle, determining the size of the dielectric layer, and completing the substrate modeling.

[0011] A preferred solution is that in the process of modeling the chip using a three-level joint modeling method, when modeling at the medium level or the substrate level, if it is confirmed that the placement of the components inside each core particle is unreasonable during the core particle level modeling, the core particle level modeling steps are re-executed, and the medium level modeling and substrate level modeling are re-executed based on the results of the re-executed core particle level modeling.

[0012] It can be seen that an iterative approach is adopted in the three-level joint modeling process. Once it is found that the completed core particle planning is unreasonable, a new round of iterative calculation will be performed according to the new parameters to optimize the modeling effect.

[0013] A further solution is to place the components inside the chip according to the connection relationship of the netlist, including: preliminarily placing the IP circuits and instances inside the chip according to the connection relationship of the netlist, and then planning the position of the micro-bumps of the chip.

[0014] It can be seen that the IP circuit and the instance inside the core particle are preliminarily arranged, and the present invention also plans the position of the micro-bumps of the chip, so as to reasonably plan the position of each micro-bump.

[0015] A further solution is to divide the on-chip chip to be modeled into multiple core particles, including: constructing a hypergraph of the core particles, with the vertices of the hypergraph representing the core particle component modules, and the edges of the hypergraph representing the connections of signal lines or pins; when constructing the hypergraph, the weights of the vertices and edges of the hypergraph are configured according to the obtained demand information.

[0016] It can be seen that when constructing a hypergraph, the present invention can obtain information input by designers to configure the weights of vertices and hyperedges in the hypergraph, realize the combination of manual intervention and algorithm automation, and realize multi-dimensional segmentation of stacked chips.

[0017] A further solution is to arrange the placement of each core particle and then perform the following: joint simulation to conduct thermal analysis of the chip, and optimize the placement of the chip based on the evaluation results, and add redundant micro-bumps.

[0018] It can be seen that during the design process of stacked chips, EDA tools can perform thermal analysis on the current chip structure and integrate simulation analysis functions into the design steps, thereby avoiding the situation where chip design and chip simulation analysis are operated separately from each other, and thus avoiding the loss of design accuracy due to data format conversion.

[0019] A further solution is to perform electromagnetic simulation and thermal simulation of the chip while automatically routing based on the arrangement position of each core particle. If the simulation results do not meet the preset requirements, the wiring is removed and re-routing is performed.

[0020] It can be seen that EDA tools can perform electromagnetic simulation, thermal simulation and other operations after the preliminary design of the chip is completed, and once the simulation effect is found to be poor, the wiring can be removed and re-wired in time, thereby completing the chip design and simulation operations within a set of EDA tools, and the wiring can be adjusted quickly.

[0021] A further solution is to perform power consumption simulation analysis after automatic routing based on the arrangement position of each chip to estimate the power distribution of each chip.

[0022] This shows that after the chip design is completed, EDA tools can quickly implement power simulation analysis, and then estimate the power distribution of each chip, providing a basis for the optimized design of the chip.

[0023] A further solution is to perform real-time cost calculation in the core particle segmentation stage, core particle modeling stage and wiring stage to calculate the chip manufacturing cost, packaging cost and testing cost.

[0024] Since manufacturing cost, packaging cost and testing cost can be calculated at each stage of chip design, designers can estimate the cost of the chip at each design stage, thereby providing basic data for the optimized design of the chip.

[0025] To achieve the above-mentioned second purpose, the stacked chip architecture modeling system provided by the present invention includes a core particle division module, a modeling module, a chip layout planning module, a layout implementation module and an automatic routing module, wherein the core particle division module is used to divide the on-chip chip to be modeled into multiple core particles; the modeling module adopts a three-level joint modeling method to model the chip: when modeling at the core particle level, each divided bare die is modeled, and the internal components of the core particle are placed according to the connection relationship of the netlist; when modeling at the dielectric layer level, the dielectric layer is modeled according to the factor of the idle area and the size of the dielectric layer is determined; when modeling at the substrate level, The substrate is modeled based on the factors of idle areas; the chip layout planning module is used to arrange the placement of each core particle based on the timing of the critical path, the total bus length and the factors of the super-long path; the layout implementation module is used to optimize the position of the internal components of the core particle based on the internal and external connection relationship of the core particle, and according to the weight of the core particle's internal and external network tables or user input information, and adjust the position of the micro-bumps mapped to each component; the automatic routing module is used to automatically route based on the arrangement position of each core particle, remove the conflicting networks in the routing, perform maze routing on the area where the routing is removed, and find the optimal routing path.

[0026] A preferred solution is that the system is further provided with a multi-physics field simulator for performing thermal simulation and electromagnetic simulation on the chip.

[0027] It can be seen that the present invention, by integrating a multi-physics field simulator, can perform electromagnetic analysis, thermal analysis and other simulation analyses on the chip during the chip design process, making it convenient for designers to optimize the chip design based on the results of the simulation analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural block diagram of an embodiment of the stacked chip architecture modeling system of the present invention.

[0029] Figure 2 It is a flow chart of an embodiment of the stacked chip architecture modeling method of the present invention.

[0030] Figure 3 This is an interface diagram when dividing the chip in an embodiment of the stacked chip architecture modeling method of the present invention.

[0031] Figure 4 This is an interface diagram when wiring the chip in an embodiment of the stacked chip architecture modeling method of the present invention.

[0032] Figure 5It is an interface diagram of the entire chip cost analysis tree diagram when performing cost analysis on the chip in the embodiment of the stacked chip architecture modeling method of the present invention.

[0033] Figure 6 This is an interface diagram of a single die cost analysis pie chart when performing cost analysis on a chip in an embodiment of the stacked chip architecture modeling method of the present invention.

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0035] The stacked chip architecture modeling system of the present invention is used to model stacked chips and provide a one-stop design solution. From the division of core particles, chip arrangement to automatic wiring, all can be implemented in a set of EDA tools, and the stacked chip architecture modeling system can also perform electromagnetic analysis, thermal analysis and other operations on the designed chip, avoiding the need for designers to continuously perform simulation analysis during the chip design process, which leads to the need to transfer data between multiple different software, and in order to meet the format problems between different software, the data involved needs to be format converted. Once the format conversion is performed, it is easy to cause the loss of accuracy of the design data, resulting in insufficient accuracy of the designed chip. The stacked chip architecture modeling method of the present invention is applied to the above-mentioned stacked chip architecture modeling system.

[0036] Stacked chip architecture modeling system embodiment:

[0037] See also Figure 1 The stacked chip architecture modeling system 10 of this embodiment is implemented on a set of EDA tools, so that users can complete the design and testing of stacked chips by relying solely on a set of EDA tools. In particular, it can realize core particle division, wiring and other operations of stacked chips, and can also realize electromagnetic simulation, thermal simulation and other operations through the simulator, avoiding designers from switching back and forth between multiple tools during the design process and avoiding the loss of design accuracy due to data format conversion.

[0038] This embodiment includes a core particle partitioning module 11 , a modeling module 12 , a chip layout planning module 13 , a layout implementation module 14 , an automatic wiring module 15 , a multi-physics field simulator 16 , and a cost optimization control module 17 .

[0039] The core particle partitioning module 11 is used to partition the chip to be modeled into multiple core particles, for example, by establishing a hypergraph and combining manual and algorithmic automation to partition the stacked chip to be modeled into multiple core particles.

[0040] The modeling module 12 uses a three-level joint modeling method to model the chip, namely core-level modeling, dielectric layer modeling and substrate-level modeling. When modeling at the core-level, each divided bare chip is modeled, and the internal components of the core are placed according to the connection relationship of the netlist; when modeling at the dielectric layer, the dielectric layer is modeled according to the factors of the idle area, and the size of the dielectric layer is determined; when modeling at the substrate level, the substrate is modeled according to the factors of the idle area.

[0041] The chip layout planning module 13 is used to arrange the placement of each chip according to multiple factors such as the timing of the critical path, the total length and the super-long path, and thus complete the preliminary layout design of the chip.

[0042] The layout implementation module 14 is used to optimize the positions of the components inside the core particle according to the connection relationship between the inside and outside of the core particle and the weights of the internal and external network tables of the core particle or user input information. In addition, the layout implementation module 14 is also used to adjust the positions of the micro-bumps mapped to each component.

[0043] The automatic routing module 15 is used to automatically perform routing based on the placement of each chiplet, including both full and detailed routing. During the global routing phase, the module first generates a global routing solution based on a pattern routing algorithm. It then removes conflicting nets and reroutes the removed nets through a maze-based routing process to find the optimal path and output a routing guide. During the detailed routing phase, the module then searches for the optimal routing solution within the maze-based routing guide output from the global routing.

[0044] The multi-physics simulator 16 integrates multiple simulators, such as an electromagnetic simulator, a thermal simulator, a power simulator, etc., so that designers can perform electromagnetic simulation, thermal simulation, power simulation, etc. on the chip during the chip design process.

[0045] The cost optimization control module 17 is used to calculate cost indicators in real time at each stage of chip design, identify key cost factors through sensitivity analysis, automatically adjust design parameters to make the cost converge to the target range, and generate a detailed cost breakdown report, so that designers can clearly understand the chip manufacturing cost, packaging cost and testing cost at each stage of chip design.

[0046] Example of stacked chip architecture modeling method:

[0047] The stacked chip architecture modeling method of this embodiment can be run on a computer device, specifically, it can be implemented by an EDA tool. Figure 2 Describes the steps of a stacked chip architecture modeling methodology.

[0048] First, execute step S1 to divide the chip on chip to be modeled into multiple core particles, that is, execute the operation of the core particle division stage. Specifically, a large chip on chip (SoC) is divided into multiple small core particles. This process can be implemented using the Partition algorithm based on the existing open source tool hmetis. During implementation, the software constructs an input hypergraph and hmetis performs the division. In the process of constructing the hypergraph, the vertices of the hypergraph represent component modules, and the edges (hyperedges) of the hypergraph represent signal lines or pin connections, thereby forming a multi-module network. In addition, when constructing the hypergraph, the weights of the vertices and hyperedges of the hypergraph can be configured according to requirements to control the results of the division. When configuring the weights of the hypergraph vertices, it is necessary to consider the area factor of the component module, and when configuring the weights of the hyperedges, factors such as the timing of the netlist and the number of ports of the netlist are considered.

[0049] In addition, when constructing the hypergraph, designers are also allowed to pre-allocate. For example, designers can specify the division of certain circuit modules and let the EDA tool complete the allocation of the remaining components. Therefore, when the core grain division module divides the core grains, it can combine manual intervention with algorithm automation to achieve multi-dimensional division of the chip. The operation interface of the core grain division stage is as follows Figure 3 shown.

[0050] Then, step S2 is executed to model the chip using a three-level joint modeling method, that is, the core particles, dielectric layers, and substrates are modeled at the same time. When modeling at the core particle level, each segmented die is modeled, and the internal components of the core particles are placed according to the connection relationship of the netlist. Specifically, each segmented die is independently parameterized and modeled to determine the shape and size of each core particle. Then, according to the connection relationship of the netlist, the internal components of the core particles are preliminarily placed, including the IP and instance inside the core particles. Then, the position of the micro bumps of the core particles is planned.

[0051] When modeling at the dielectric level, the dielectric layer is modeled based on the idle area and its dimensions are determined. Specifically, after initially positioning the modeled core particles based on connection relationships, line lengths, and thermal effects, the dielectric layer is modeled based on the idle area to determine its shape and size. When modeling at the substrate level, the substrate is modeled based on the idle area. Specifically, the substrate needs to be modeled based on factors such as the idle area and fan-out.

[0052] Furthermore, the three-level joint modeling process is iterative. That is, during dielectric-level modeling or substrate-level modeling, if it is determined that the placement of components within each core particle during core-level modeling is not appropriate, the core-level modeling steps are re-executed, and based on the results of the re-executed core-level modeling, dielectric-level modeling and substrate-level modeling are re-executed, thus achieving iterative calculations. This approach makes the resulting stacked chip model more reasonable.

[0053] Next, step S3 is executed to arrange the placement of each chiplet based on the critical path timing, bus length, and extra-long paths, i.e., performing the layout planning phase. Specifically, when placing the chiplets, factors such as the critical path timing, bus length, and extra-long paths are taken into consideration. For example, chiplets with high-frequency interactions on critical paths should be placed adjacent to each other, timing-critical modules should be preferentially placed near the clock source, dedicated routing channels should be reserved for critical paths across die, the total length of global signal lines should meet the bus length required by the process, and extra-long signal lines should be avoided during layout. Furthermore, factors such as thermal management requirements and manufacturability should also be considered.

[0054] After completing the initial placement, a joint simulation will be conducted to evaluate and optimize the placement results in hotspot areas. Redundant micro-bumps will be added, primarily targeting micro-bumps in hotspots. More redundant micro-bumps will be allocated to act as diversion points. These redundant micro-bumps maintain voltage stability in the power / ground network, reducing voltage fluctuations and ensuring power integrity. Redundant micro-bumps in the clock network prevent single-point failures that can cause clock signal loss, reducing bit error rates for high-speed signal transmission. These redundant micro-bumps can also be reserved for design considerations. After the chip placement is complete, data metrics including thermal maps, routing resource assessments, and key signal timing are provided for designers to analyze, assessing the rationale of the current layout and providing guidance for subsequent processes.

[0055] Then, step S4 is executed to optimize the positions of the components within the core particle based on the internal and external connection relationships of the core particle, and based on the weights of the core particle's internal and external netlists or user input information, and adjust the positions of the micro-bumps mapped to each component. Specifically, during the layout implementation phase, the internal and external connection relationships of the core particle are simultaneously considered, and the positions of the components within the core particle are optimized and adjusted using the default weights of the core particle's internal and external netlists or information input by the user, while also adjusting the positions of the micro-bumps mapped to these components, thereby optimizing the planning results of the entire core particle.

[0056] Finally, execute step S5, perform automatic routing based on the arrangement position of each core particle, remove the conflicting networks in the routing, perform maze routing on the area where the routing is removed, and find the optimal routing path, that is, perform the operation of the automatic routing stage. Specifically, the automatic routing module adopts a combination of global routing and detailed routing to perform adaptive routing, and adopts a shredded and re-routed routing framework. In the global routing stage, a global routing solution is first obtained based on the pattern routing algorithm, and then the conflicting networks are removed, and then a maze routing is performed on the removed networks based on the Dijkstra algorithm to find the optimal path and output a routing guide. In the detailed routing stage, the optimal routing solution is found using the maze routing based on the Dijkstra algorithm kernel in the routing guide output by the global routing. The interface diagram for routing using EDA tools is as follows: Figure 4 shown.

[0057] For different types of networks, the order of wiring will be different. For example, you can do power wiring first, then process the critical path, and then do the rest of the wiring operations. During the wiring process, electromagnetic simulation and thermal simulation can be performed at any time, and then the wiring can be removed and re-routed according to the simulation results. The wiring process is iterative, convergent, and continuously optimized. This embodiment will simultaneously consider the wiring results of the global core, dielectric layer, and substrate. For example, by considering the wiring on the substrate layer, the wiring of the dielectric layer can be modified in turn. Finally, the design file (.def) and layout file (.gds) corresponding to each core, dielectric layer, and substrate can be output for subsequent production and manufacturing processes.

[0058] It's important to note that EDA tools integrate multiple analysis functions into a unified environment, enabling signal integrity analysis and automatically identifying potential crosstalk and latency issues. For example, EDA tools can analyze chip power consumption and accurately estimate the power consumption distribution of each chip. For thermal analysis, EDA tools can predict system-level temperature fields and identify hotspots. Cost analysis can also track material, manufacturing, and testing costs in real time. Furthermore, various simulation tools can be used in real time during the modeling process, and analysis results are intuitively displayed through a visual interface, supporting design decisions and allowing designers to adjust and optimize chip designs based on simulation results.

[0059] In addition, this embodiment also proposes a closed-loop cost optimization mechanism, and the iteration of the entire system will also be based on the premise of cost convergence. The EDA tool establishes a full cost model including manufacturing, packaging, and testing. Real-time cost calculation is performed at each stage of chip design, including the core particle division stage, core particle modeling stage, and wiring stage. The manufacturing cost, packaging cost, and testing cost of the chip are calculated. Through sensitivity analysis, key cost factors are identified, and design parameters are automatically adjusted to make the cost converge to the target range. A detailed cost decomposition report is generated, such as a tree diagram of cost analysis. Figure 5As shown in the pie chart of single die cost analysis Figure 6 shown.

[0060] Compared to traditional EDA tools, this invention can partition an on-chip chip into multiple cores and perform modeling, making chip modeling more flexible. Furthermore, this invention integrates chip design and simulation, outputting information such as electrothermal signal simulation results, heat maps, critical path timing, and wiring resource assessment after layout. It can also add redundant micro-bumps based on hotspot areas.

[0061] In addition, after chip layout planning, the present invention also optimizes and adjusts the position of the modules and micro-bumps inside the core particle, and can support the coordinated wiring of the core particle to the dielectric layer and substrate during automatic wiring. In addition, during the core particle design process, a collaborative iteration method is used, that is, when the subsequent design link finds that the previous design link is unreasonable, the design of the previous link is adjusted. In addition, during the design process, simulation tools can be called to simulate the current design and optimize and adjust the current design based on the simulation results. Finally, the present invention can perform cost estimation at each stage of chip design, making it convenient for designers to optimize the design based on the estimated cost.

[0062] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A stacked chip architecture modeling method, characterized in that: include: Divide the chip to be modeled into multiple cores; The chip is modeled using a three-level joint modeling approach: at the core-level modeling, each segmented die is modeled, and the components inside the core are placed according to the connection relationship of the netlist; When modeling at the medium level, the medium layer is modeled according to the factors of the idle area, and the size of the medium layer is determined; when modeling at the substrate level, the substrate is modeled according to the factors of the idle area; Arranging the positions of the core particles according to the timing of the critical path, the total length and the factors of the super-long path; Optimizing the positions of the components inside the core particle according to the connection relationship between the inside and outside of the core particle and the weights of the internal and external network tables of the core particle or user input information, and adjusting the positions of the micro-bumps mapped to each component; Automatic routing is performed based on the arrangement positions of the core particles, and conflicting networks in the routing are removed, maze routing is performed on the area where the routing is removed, and an optimal routing path is found; In the process of modeling a chip using a three-level joint modeling approach, if, during the dielectric-level modeling or substrate-level modeling, it is determined that the placement of the components inside each core particle during the core-level modeling is unreasonable, the core-level modeling step is re-executed, and the dielectric-level modeling and substrate-level modeling are re-executed based on the results of the re-executed core-level modeling. The above-mentioned core particle division, chip arrangement and automatic wiring operations are all implemented in a set of EDA tools.

2. The stacked chip architecture modeling method according to claim 1, wherein: Placing the components inside the core particle according to the connection relationship of the netlist includes: preliminarily arranging the IP circuit and the instance inside the core particle according to the connection relationship of the netlist, and then planning the position of the micro-bumps of the chip.

3. The stacked chip architecture modeling method according to claim 1 or 2, wherein: Dividing the chip to be modeled into a plurality of core particles includes: constructing a hypergraph of the core particles, wherein the vertices of the hypergraph represent the core particle component modules, and the edges of the hypergraph represent the connections of signal lines or pins; When constructing the hypergraph, the weights of the vertices and edges of the hypergraph are configured according to the acquired demand information.

4. The stacked chip architecture modeling method according to claim 1 or 2, wherein: After arranging the placement positions of the core particles, the following steps are further performed: performing a joint simulation to perform a thermal analysis on the chip, and optimizing the placement positions of the chip according to the evaluation results, and adding redundant micro-bumps.

5. The stacked chip architecture modeling method according to claim 1 or 2, wherein: When automatic wiring is performed based on the arrangement positions of the core particles, electromagnetic simulation and thermal simulation of the chip are also performed. If the simulation results do not meet the preset requirements, the wiring is removed and re-wired.

6. The stacked chip architecture modeling method according to claim 1 or 2, wherein: After automatic routing is performed based on the arrangement positions of the chiplets, power consumption simulation analysis is performed to estimate the power distribution of the chiplets.

7. The stacked chip architecture modeling method according to claim 1 or 2, wherein: Real-time cost calculation is performed in the core particle partitioning stage, the core particle modeling stage and the routing stage to calculate the manufacturing cost, packaging cost and testing cost of the chip.

8. A stacked chip architecture modeling system implemented on a set of EDA tools, characterized in that: include: A core particle partitioning module is used to partition the chip to be modeled into multiple core particles; The modeling module uses a three-level joint modeling approach to model the chip: at the core-level, each segmented die is modeled, and the components inside the core are placed according to the connection relationship of the netlist; During medium-level modeling, the medium layer is modeled based on the idle area factor, and the size of the medium layer is determined; during substrate-level modeling, the substrate is modeled based on the idle area factor; in the three-level joint modeling process, during medium-level modeling or substrate-level modeling, if it is determined that the placement of the internal components of each core particle during core-level modeling is unreasonable, the core-level modeling step is re-executed, and the medium-level modeling and substrate-level modeling are re-executed based on the results of the re-executed core-level modeling; A chip layout planning module is used to arrange the placement of each of the core particles based on the timing of the critical path, the total length and the factors of the super-long path; A layout implementation module is used to optimize the positions of the components inside the core particle according to the internal and external connection relationship of the core particle and the weights of the internal and external network tables of the core particle or user input information, and adjust the positions of the micro-bumps mapped to each component; The automatic wiring module is used to automatically perform wiring based on the arrangement position of each of the core particles, remove conflicting networks in the wiring, perform maze wiring on the area where the wiring is removed, and find the optimal wiring path.

9. The stacked chip architecture modeling system according to claim 8, wherein: The system is also provided with a multi-physics field simulator for performing thermal simulation and electromagnetic simulation on the chip.

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